Capacitor chip structure

Abstract

The embodiment of the utility model provides a capacitor chip structure. The capacitor chip structure comprises a glass substrate; the first conducting layer is positioned on the first surface of the glass substrate; the capacitor dielectric layer is positioned on one side, far away from the glass substrate, of the first conductive layer; the capacitor dielectric layer also covers the side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole; the second conductive layer is positioned on one side, far away from the first conductive layer, of the capacitor dielectric layer; the boundary of the second conductive layer shrinks inwards towards the center of the capacitor chip structure relative to the boundary of the first conductive layer; the insulating layer is positioned on one side, far away from the capacitor dielectric layer, of the second conductive layer; the insulating layer is provided with a second through hole and a third through hole which penetrate through the insulating layer; the first electrical connection structure is electrically connected with the second conductive layer; the second electrical connection structure is electrically connected with the first conductive layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a capacitor chip structure. Background Art

[0002] Multi-layer ceramic capacitors (MLCCs) are made by stacking ceramic dielectric diaphragms with printed electrodes (inner electrodes) in an offset manner. After a one-time high-temperature sintering, a ceramic chip is formed. A metal layer (outer electrode) is then sealed at both ends of the chip to form a structure similar to a monolithic structure, hence the name monolithic capacitor.

[0003] Currently, the substrate of the capacitor chip structure in chip-type multilayer ceramic capacitors mostly uses a silicon substrate. The supporting strength of the silicon substrate is not strong enough, and the capacitor chip structure needs to be packaged twice before it can be used. Utility Model Content

[0004] The present disclosure provides a capacitor chip structure to improve the support strength of a substrate in the capacitor chip structure and reduce packaging difficulty.

[0005] The present disclosure provides a capacitor chip structure, comprising:

[0006] The glass substrate comprises a first surface and a second surface opposite to each other;

[0007] a first conductive layer, wherein the first conductive layer is located on a first surface of the glass substrate;

[0008] a capacitor dielectric layer, the capacitor dielectric layer being located on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covering a sidewall of the first conductive layer; and the capacitor dielectric layer being provided with a first through hole, the first through hole penetrating the capacitor dielectric layer and exposing a portion of a surface of the first conductive layer;

[0009] a second conductive layer, the second conductive layer being located on a side of the capacitor dielectric layer away from the first conductive layer; a boundary of the second conductive layer being retracted inward toward the center of the capacitor chip structure relative to a boundary of the first conductive layer;

[0010] an insulating layer, the insulating layer being located on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer further covering a sidewall of the second conductive layer, a side of the capacitor dielectric layer away from the first conductive layer, a sidewall of the capacitor dielectric layer, and a sidewall of the first through hole; the insulating layer being provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposing a portion of a surface of the second conductive layer;

[0011] a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate and electrically connected to the second through hole and the second conductive layer; and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate;

[0012] The second electrical connection structure has a central portion located at the third through hole and electrically connected to the first conductive layer, and an edge portion located at a surface of the insulating layer away from the glass substrate.

[0013] Optionally, it further includes a third conductive layer, wherein the third conductive layer and the second conductive layer are provided on the same layer;

[0014] The third conductive layer and the second conductive layer are insulated by the insulating layer;

[0015] The central portion of the third conductive layer is located at the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located at a side of the capacitor dielectric layer away from the first conductive layer;

[0016] A central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

[0017] Optionally, the insulating layer includes a passivation layer;

[0018] The passivation layer is located on a side of the second conductive layer away from the capacitor dielectric layer. The passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first through hole.

[0019] Optionally, the insulating layer further includes a buffer layer, which is located on a side of the passivation layer away from the second conductive layer, and the buffer layer further covers the sidewalls of the passivation layer in the second through hole and the third through hole.

[0020] Optionally, the insulating layer includes a passivation layer;

[0021] The passivation layer is located on a side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer is also located on a side of the third conductive layer away from the first conductive layer;

[0022] The passivation layer also covers the sidewalls of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewalls of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer;

[0023] The third conductive layer and the second conductive layer are insulated from each other by the passivation layer.

[0024] Optionally, the insulating layer further includes a buffer layer, which is located on a side of the passivation layer away from the second conductive layer and the third conductive layer, and the buffer layer further covers the sidewalls of the passivation layer in the second through hole and the third through hole.

[0025] Optionally, the capacitor chip structure includes two oppositely disposed first long sides and two oppositely disposed first short sides in a cross-sectional diagram parallel to the first surface, the first long sides and the first short sides are perpendicularly disposed, and the length of the first long side is greater than the length of the first short side;

[0026] The second through hole is located at the first end of the capacitor chip structure, the third through hole is located at the second end of the capacitor chip structure, and the direction from the first end of the capacitor chip structure to the second end of the capacitor chip structure is parallel to the first long side.

[0027] Optionally, the first electrical connection structure includes a fourth conductive layer and a first pad;

[0028] The fourth conductive layer is located in the second through hole and on a portion of the surface of the insulating layer away from the glass substrate;

[0029] The first pad is located on a side of the fourth conductive layer away from the insulating layer.

[0030] Optionally, a cross-sectional diagram of the first pad on the first surface includes two oppositely disposed second long sides and two oppositely disposed second short sides, the second long sides are parallel to the first short sides, the second short sides are parallel to the first long sides, and the length of the second long side is greater than the length of the second short side;

[0031] The length of the second short side is less than one third of the length of the first long side.

[0032] Optionally, the length of the second short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0033] And / or, the length of the second long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

[0034] Optionally, on one side of the first end of the capacitor chip structure, a distance between the second long side and the first short side close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns;

[0035] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

[0036] Optionally, the second electrical connection structure includes a fifth conductive layer and a second pad;

[0037] The fifth conductive layer is located in the third through hole and on a portion of the surface of the insulating layer away from the glass substrate;

[0038] The second pad is located on a side of the fifth conductive layer away from the insulating layer.

[0039] Optionally, the cross-sectional pattern of the second solder pad on the first surface includes two oppositely arranged third long sides and two oppositely arranged third short sides, the third long sides are arranged parallel to the first short sides, the third short sides are arranged parallel to the first long sides, the length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one third of the length of the first long side.

[0040] Optionally, the length of the third short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0041] And / or, the length of the third long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

[0042] Optionally, on one side of the second end of the capacitor chip structure, a distance between the third long side close to the second end of the capacitor chip structure and the first short side is greater than or equal to 15 microns and less than or equal to 40 microns;

[0043] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

[0044] Optionally, the thickness of the first pad is greater than or equal to 15 microns and less than or equal to 60 microns.

[0045] Optionally, the thickness of the second pad is greater than or equal to 15 microns and less than or equal to 60 microns.

[0046] Optionally, a value by which a boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to a boundary of the first conductive layer is greater than or equal to 3 micrometers.

[0047] The capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate as a substrate, which can provide greater structural strength relative to a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and enables the capacitor chip structure to have a better quality factor (Q value). Wherein, the capacitor dielectric layer is used to insulate the first conductive layer and the second conductive layer, the first conductive layer serves as the first plate of the capacitor, and obtains an electrical signal through the second electrical connection structure; the second conductive layer serves as the second plate of the capacitor, and obtains an electrical signal through the first electrical connection structure. The boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer, so that the surface and sidewalls of the non-electrically connected part of the first conductive layer and the second electrical connection structure are covered by the capacitor dielectric layer, thereby achieving better electrical isolation of the first conductive layer and the second conductive layer. Wherein, the insulating layer covers the surface and sidewalls of the capacitor dielectric layer that are not covered by the second conductive layer, and the insulating layer also covers the surface and sidewalls of the non-electrically connected part of the second conductive layer and the first electrical connection structure, as well as the surface of the non-electrically connected part of the first conductive layer and the second electrical connection structure. The capacitor dielectric layer and the insulating layer play the role of insulating packaging for the capacitor chip structure. Furthermore, the first electrical connection structure and the second electrical connection structure are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0048] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following detailed description of the drawings illustrating the embodiments is provided. It should be noted that the drawings described below relate only to the embodiments of the present disclosure and are not intended to limit the present disclosure. It should also be noted that the various features shown in the drawings are not drawn to scale. In fact, for clarity, it is sometimes necessary to arbitrarily increase or decrease the dimensions of various features.

[0050] Figure 1 : A top view of a capacitor chip structure.

[0051] Figure 2 : A cross-sectional diagram of a capacitor chip structure. Figure 1 AA' section of the plan view shown.

[0052] Figure 3 : A top view of a capacitor structure.

[0053] Figure 4 : A cross-sectional diagram of a capacitor chip structure. Figure 3AA' section of the plan view shown.

[0054] Figures 1 to 4 The reference numerals in the figures are as follows:

[0055] 100: glass substrate; 101: first surface; 102: second surface; 110: first conductive layer; 120: capacitor dielectric layer; 130: second conductive layer; 301: insulating layer; 135: passivation layer; 140: buffer layer; 300: first through hole; 150: second through hole; 160: third through hole; 302: first electrical connection structure; 303: second electrical connection structure; 170: fourth conductive layer; 190: first solder pad; 180: fifth conductive layer; 200: second solder pad; 304: first long side; 305: first short side; 306: second long side; 307: second short side; 308: third long side; 309: third short side; L1: length of the first long side; W1: length of the first short side; L2: length of the second short side; W2: length of the second long side; L3: length of the third short side; W3: length of the third long side; 400: third conductive layer. DETAILED DESCRIPTION

[0056] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference purposes only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through a number of details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display. It should be noted that, in the absence of conflict, the embodiments of the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0057] In order to improve the support strength of the substrate in the capacitor chip structure and reduce the packaging difficulty, the embodiments of the present disclosure provide the following technical solutions:

[0058] Figure 1 The figure shows a top view of a capacitor chip structure, where the position of the AA′ section is marked. Figure 2 A cross-sectional schematic diagram of a capacitor chip structure.

[0059] The following combination Figure 1 and Figure 2 As shown, the structural features of the capacitor chip structure of the embodiment of the present disclosure (Embodiment 1) are described in detail.

[0060] The capacitor chip structure includes: a glass substrate 100, including a first surface 101 and a second surface 102 arranged opposite to each other; a first conductive layer 110, the first conductive layer 110 is located on the first surface 101 of the glass substrate 100; a capacitor dielectric layer 120, the capacitor dielectric layer 120 is located on a side of the first conductive layer 110 away from the glass substrate 100; the capacitor dielectric layer 120 also covers the sidewall of the first conductive layer 110, and the capacitor dielectric layer 120 is provided with a first through hole 300, the first through hole 300 passes through the capacitor dielectric layer 120 and exposes a portion of the surface of the first conductive layer 110; a second conductive layer 130, the second conductive layer 130 is located on a side of the capacitor dielectric layer 120 away from the first conductive layer 110; the boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110; an insulating layer 301, the insulating layer 301 is located on a side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the insulating layer 301 is provided on the side of the second conductive layer 130 away from the capacitor dielectric layer 120. 01 also covers the sidewalls of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the sidewalls of the capacitor dielectric layer 120 and the sidewalls of the first through-hole 300; the insulating layer 301 is provided with a second through-hole 150 and a third through-hole 160 that penetrate the insulating layer 301, the second through-hole 150 exposes a portion of the surface of the second conductive layer 130, and the third through-hole 160 is connected to the first through-hole 300; a first electrical connection structure 302, the center portion of the first electrical connection structure 302 is located at the second through-hole 150 and is electrically connected to the second conductive layer 130, and the edge portion of the first electrical connection structure 302 is located at the surface of the insulating layer 301 away from the glass substrate 100; a second electrical connection structure 303, the center portion of the second electrical connection structure 303 is located at the third through-hole 160 and is electrically connected to the first conductive layer 110, and the edge portion of the second electrical connection structure 303 is located at the surface of the insulating layer 301 away from the glass substrate 100.

[0061] The capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate 100 as a substrate, which can provide greater structural strength than a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and enables the capacitor chip structure to have a better quality factor (Q value). Among them, the capacitor dielectric layer 120 is used to insulate the first conductive layer 110 and the second conductive layer 130. The first conductive layer 110 serves as the first plate of the capacitor and obtains the electrical signal through the second electrical connection structure 303; the second conductive layer 130 serves as the second plate of the capacitor and obtains the electrical signal through the first electrical connection structure 302. The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, so that the surface and sidewall of the non-electrically connected part of the first conductive layer 110 and the second electrical connection structure 303 are covered by the capacitor dielectric layer 120, thereby achieving better electrical isolation of the first conductive layer 110 and the second conductive layer 130. The insulating layer 301 covers the surface and sidewalls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The insulating layer 301 also covers the surface and sidewalls of the portion of the second conductive layer 130 that is not electrically connected to the first electrical connection structure 302, as well as the surface of the portion of the first conductive layer 110 that is not electrically connected to the second electrical connection structure 303. The capacitor dielectric layer 120 and the insulating layer 301 provide an insulating package for the capacitor chip structure. Furthermore, the first electrical connection structure 302 and the second electrical connection structure 303 are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0062] Optionally, the first conductive layer 110 includes any one of polysilicon, Ti, Al, Cu, Cr, Mo, W, and TiW, or a stack of two or more thereof. The capacitor dielectric layer 120 includes any one of silicon oxide and silicon nitride, or a stack of a combination thereof. The second conductive layer 130 includes any one of Ti, Al, Cu, Cr, Mo, W, and TiW, or a stack of two or more thereof. Preferably, the surface material of the second conductive layer 130 is any one of Ti, Cr, and TiW, or a stack of two or more thereof, so that its surface has good adhesion, which is conducive to good adhesion to the material attached to its surface, thereby increasing the reliability of the structure.

[0063] Optional, such as Figure 2 As shown, the insulating layer 301 includes a passivation layer 135; the passivation layer 135 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 also covers the side wall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the side wall of the capacitor dielectric layer 120, and the side wall of the first through hole 300.

[0064] Specifically, the passivation layer 135 covers the surface and sidewalls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The passivation layer 135 also covers the surface and sidewalls of the portion of the second conductive layer 130 that is not electrically connected to the first electrical connection structure 302, as well as the surface of the portion of the first conductive layer 110 that is not electrically connected to the second electrical connection structure 303. The capacitor dielectric layer 120 and the passivation layer 135 serve as an insulating package for the capacitor chip structure. The passivation layer 135 includes either silicon oxide or silicon nitride, or a combination thereof.

[0065] Optional, such as Figure 2 As shown, the insulating layer 301 also includes a buffer layer 140, which is located on the side of the passivation layer 135 away from the second conductive layer 130. The buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160, so that the capacitor dielectric layer 120, the passivation layer 135 and the buffer layer 140 play an insulating packaging role for the capacitor chip structure. The buffer layer 140 can provide stress buffering during the use of the capacitor chip structure patch, thereby improving the reliability of the capacitor chip structure. Optionally, the buffer layer 140 includes an organic material such as polyimide.

[0066] The passivation layer 135 is provided with a sub-through hole 300a, exposing the second conductive layer 130. The passivation layer 135 is further provided with a sub-through hole 300b, which is connected to the first through hole 300, exposing the first conductive layer 110.

[0067] Optional, such as Figure 1 As shown, the capacitor chip structure includes two oppositely disposed first long sides 304 and two oppositely disposed first short sides 305 in a cross-sectional diagram parallel to the first surface 101. The first long sides 304 and the first short sides 305 are arranged perpendicularly, and the length L1 of the first long side 304 is greater than the length W1 of the first short side 305. Figure 2 As shown, the second through hole 150 is located at the first end of the capacitor chip structure, the third through hole 160 is located at the second end of the capacitor chip structure, and the first end of the capacitor chip structure points to the direction of the second end of the capacitor chip structure and is arranged parallel to the first long side 304.

[0068] Specifically, the second through hole 150 and the third through hole 160 are respectively located at the two ends of the capacitor chip structure along the direction of the first long side 304, so that the first electrical connection structure 302 and the second electrical connection structure 303 are respectively located at the two ends of the capacitor chip structure along the direction of the first long side 304, and the distance between the first electrical connection structure 302 and the second electrical connection structure 303 can be set farther, thereby better realizing the electrical isolation between the first electrical connection structure 302 and the second electrical connection structure 303.

[0069] Optional, such as Figure 2 As shown, the first electrical connection structure 302 includes a fourth conductive layer 170 and a first pad 190; the fourth conductive layer 170 is located in the second through hole 150 and on a portion of the surface of the insulating layer 301 away from the glass substrate 100; the first pad 190 is located on a side of the fourth conductive layer 170 away from the insulating layer 301.

[0070] Specifically, fourth conductive layer 170 is used to transmit electrical signals to second conductive layer 130, and first solder pad 190 is used to connect the capacitor chip structure to other electrical components. Optionally, fourth conductive layer 170 includes a Ti and Cu stack, or a Ti, Cu, and Ni stack. First solder pad 190 includes a SnAg alloy.

[0071] Optional, such as Figure 1 As shown, the cross-sectional pattern of the first pad 190 on the first surface 101 includes two oppositely arranged second long sides 306 and two oppositely arranged second short sides 307, the second long sides 306 and the first short sides 305 are arranged in parallel, the second short sides 307 and the first long sides 304 are arranged in parallel, the length W2 of the second long side 306 is greater than the length L2 of the second short side 307; the length L2 of the second short side 307 is less than one-third of the length L1 of the first long side 304, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0072] Optional, such as Figure 1 As shown, the length L2 of the second short side 307 is greater than or equal to 10% of the length L1 of the first long side 304, and less than or equal to 30% of the length L1 of the first long side 304; and / or, the length W2 of the second long side 306 is greater than or equal to 40% of the length W1 of the first short side 305, and less than or equal to 90% of the length W1 of the first short side 305, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0073] Optional, such as Figure 1 As shown, on one side of the first end of the capacitor chip structure, the spacing d1 between the second long side 306 and the first short side 305 close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; and / or, on one side of the first end of the capacitor chip structure, the shortest spacing d2 between the second short side 307 and the first long side 304 is greater than or equal to 15 microns and less than or equal to 40 microns, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0074] Optional, such as Figure 2As shown, the second electrical connection structure 303 includes a fifth conductive layer 180 and a second pad 200; the fifth conductive layer 180 is located in the third through hole 160 and on a portion of the surface of the insulating layer 301 away from the glass substrate 100; the second pad 200 is located on a side of the fifth conductive layer 180 away from the insulating layer 301.

[0075] Specifically, the fifth conductive layer 180 is used to transmit electrical signals to the first conductive layer 110, and the second pad 200 is used to connect the capacitor chip structure to other electrical components. Optionally, the fifth conductive layer 180 includes a Ti and Cu stack or a Ti, Cu, and Ni stack. The second pad 200 includes a SnAg alloy.

[0076] Optional, such as Figure 1 As shown, the cross-sectional pattern of the second pad 200 on the first surface 101 includes two relatively arranged third long sides 308 and two relatively arranged third short sides 309, the third long side 308 and the first short side 305 are arranged in parallel, the third short side 309 and the first long side 304 are arranged in parallel, the length W3 of the third long side 308 is greater than the length L3 of the third short side 309, and the length L3 of the third short side 309 is less than one-third of the length L1 of the first long side 304, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0077] Optional, such as Figure 1 As shown, the length L3 of the third short side 309 is greater than or equal to 10% of the length of the first long side 304 and less than or equal to 30% of the length of the first long side 304; and / or, the length W3 of the third long side 308 is greater than or equal to 40% of the length W1 of the first short side 305 and less than or equal to 90% of the length of the first short side 305, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0078] Optional, such as Figure 1 As shown, on one side of the second end of the capacitor chip structure, the spacing d3 between the third long side 308 and the first short side 305 close to the second end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; and / or, on one side of the first end of the capacitor chip structure, the shortest spacing d4 between the third short side 309 and the first long side 304 is greater than or equal to 15 microns and less than or equal to 40 microns, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0079] Optional, such as Figure 2 As shown, the thickness of the first pad 190 is greater than or equal to 15 microns and less than or equal to 60 microns, which facilitates mounting and connection with other electrical components.

[0080] Optional, such as Figure 2 As shown, the thickness of the second pad 200 is greater than or equal to 15 microns and less than or equal to 60 microns, which is convenient for mounting and connecting with other electrical components.

[0081] Optional, such as Figure 2 As shown, the boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure by an amount greater than or equal to 3 micrometers relative to the boundary of the first conductive layer 110 .

[0082] The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure by a value greater than or equal to 3 microns relative to the boundary of the first conductive layer 110, so as to provide more space for the insulating layer 301 covering the surface of the capacitor dielectric layer 120, so that the capacitor dielectric layer 120 covers the surface and side walls of the non-electrically connected parts of the first conductive layer 110 and the second electrical connection structure 303, thereby achieving better electrical isolation between the first conductive layer 110 and the second conductive layer 130.

[0083] Figure 3 The figure shows a top view of a capacitor chip structure, where the position of the AA′ section is marked. Figure 4 A cross-sectional schematic diagram of a capacitor chip structure.

[0084] The following combination Figure 3 and Figure 4 As shown, the structural features of the capacitor chip structure of the embodiment of the present disclosure (Embodiment 2) are described in detail.

[0085] like Figure 3 and Figure 4 The structural features of the capacitor chip of the second embodiment shown are similar to Figure 1 and Figure 2 The differences of the first embodiment shown are as follows:

[0086] 1) The capacitor chip structure also includes a third conductive layer 400, which is arranged on the same layer as the second conductive layer 130; the third conductive layer 400 and the second conductive layer 130 are insulated by an insulating layer 301; the central portion of the third conductive layer 400 is located in the first through-hole 300 and is electrically connected to the first conductive layer 110, and the edge portion of the third conductive layer 400 is located on the side of the capacitor dielectric layer 120 away from the first conductive layer 110; the central portion of the second electrical connection structure 303 is located in the third through-hole 160 and is electrically connected to the first conductive layer 110 through the third conductive layer 400.

[0087] The third conductive layer 400 and the second conductive layer 130 are provided in the same layer, which means that the third conductive layer 400 and the second conductive layer 130 are formed by the same metal layer through an etching process.

[0088] 2) The insulating layer 301 includes a passivation layer 135; the passivation layer 135 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 is also located on the side of the third conductive layer 400 away from the first conductive layer 110; the passivation layer 135 also covers the sidewalls of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the sidewalls of the capacitor dielectric layer 120, and a portion of the surface of the third conductive layer 400 away from the first conductive layer 110; the third conductive layer 400 and the second conductive layer 130 are insulated by the passivation layer 135.

[0089] 3) The insulating layer 301 further includes a buffer layer 140 , which is located on a side of the passivation layer 135 away from the second conductive layer 130 and the third conductive layer 400 . The buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160 .

[0090] The capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate 100 as a substrate, which can provide greater structural strength than a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and makes the capacitor chip structure have a better quality factor (Q value). Among them, the capacitor dielectric layer 120 is used to insulate the first conductive layer 110 and the second conductive layer 130. The first conductive layer 110 serves as the first plate of the capacitor and obtains electrical signals through the third conductive layer 400 and the second electrical connection structure 303; the second conductive layer 130 serves as the second plate of the capacitor and obtains electrical signals through the first electrical connection structure 302. The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, so that the surface and sidewall of the non-electrically connected part of the first conductive layer 110 and the second electrical connection structure 303 are covered by the capacitor dielectric layer 120, thereby achieving better electrical isolation of the first conductive layer 110 and the second conductive layer 130. The insulating layer 301 covers the surface and sidewalls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The insulating layer 301 also covers the surface and sidewalls of the portion of the second conductive layer 130 that is not electrically connected to the first electrical connection structure 302, as well as the surface of the portion of the first conductive layer 110 that is not electrically connected to the second electrical connection structure 303. The capacitor dielectric layer 120 and the insulating layer 301 provide an insulating package for the capacitor chip structure. Furthermore, the first electrical connection structure 302 and the second electrical connection structure 303 are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0091] The passivation layer 135 is provided with a sub-via hole 300 a exposing the second conductive layer 130 . The passivation layer 135 is also provided with a sub-via hole 300 b exposing the third conductive layer 400 .

[0092] It must be noted that the above is only a specific implementation method of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A capacitor chip structure, characterized in that: include: The glass substrate comprises a first surface and a second surface opposite to each other; a first conductive layer, wherein the first conductive layer is located on a first surface of the glass substrate; a capacitor dielectric layer, the capacitor dielectric layer being located on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covering a sidewall of the first conductive layer; and the capacitor dielectric layer being provided with a first through hole, the first through hole penetrating the capacitor dielectric layer and exposing a portion of a surface of the first conductive layer; a second conductive layer, the second conductive layer being located on a side of the capacitor dielectric layer away from the first conductive layer; a boundary of the second conductive layer being retracted inward toward the center of the capacitor chip structure relative to a boundary of the first conductive layer; an insulating layer, the insulating layer being located on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer further covering a sidewall of the second conductive layer, a side of the capacitor dielectric layer away from the first conductive layer, a sidewall of the capacitor dielectric layer, and a sidewall of the first through hole; the insulating layer being provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposing a portion of a surface of the second conductive layer; a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate and electrically connected to the second through hole and the second conductive layer; and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate; The second electrical connection structure has a central portion located at the third through hole and electrically connected to the first conductive layer, and an edge portion located at a surface of the insulating layer away from the glass substrate.

2. The capacitor chip structure according to claim 1, characterized in that: It also includes a third conductive layer, wherein the third conductive layer and the second conductive layer are provided on the same layer; The third conductive layer and the second conductive layer are insulated by the insulating layer; The central portion of the third conductive layer is located at the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located at a side of the capacitor dielectric layer away from the first conductive layer; A central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

3. The capacitor chip structure according to claim 1, characterized in that: The insulating layer includes a passivation layer; The passivation layer is located on a side of the second conductive layer away from the capacitor dielectric layer. The passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first through hole.

4. The capacitor chip structure according to claim 3, characterized in that: The insulating layer further includes a buffer layer. The buffer layer is located on a side of the passivation layer away from the second conductive layer. The buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

5. The capacitor chip structure according to claim 2, characterized in that: The insulating layer includes a passivation layer; The passivation layer is located on a side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer is also located on a side of the third conductive layer away from the first conductive layer; The passivation layer also covers the sidewalls of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewalls of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer; The third conductive layer and the second conductive layer are insulated from each other by the passivation layer.

6. The capacitor chip structure according to claim 5, characterized in that: The insulating layer further includes a buffer layer, which is located on a side of the passivation layer away from the second conductive layer and the third conductive layer. The buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

7. The capacitor chip structure according to claim 1, characterized in that: The capacitor chip structure includes two oppositely disposed first long sides and two oppositely disposed first short sides in a cross-sectional diagram parallel to the first surface, wherein the first long sides and the first short sides are perpendicularly disposed, and the length of the first long side is greater than the length of the first short side; The second through hole is located at the first end of the capacitor chip structure, the third through hole is located at the second end of the capacitor chip structure, and the direction from the first end of the capacitor chip structure to the second end of the capacitor chip structure is parallel to the first long side.

8. The capacitor chip structure according to claim 7, characterized in that: The first electrical connection structure includes a fourth conductive layer and a first pad; The fourth conductive layer is located in the second through hole and on a portion of the surface of the insulating layer away from the glass substrate; The first pad is located on a side of the fourth conductive layer away from the insulating layer.

9. The capacitor chip structure according to claim 8, characterized in that: The cross-sectional shape of the first pad on the first surface includes two oppositely disposed second long sides and two oppositely disposed second short sides, the second long sides are parallel to the first short sides, the second short sides are parallel to the first long sides, and the length of the second long side is greater than the length of the second short side; The length of the second short side is less than one third of the length of the first long side.

10. The capacitor chip structure according to claim 9, characterized in that: The length of the second short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; And / or, the length of the second long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

11. The capacitor chip structure according to claim 9, characterized in that: On one side of the first end of the capacitor chip structure, a distance between the second long side and the first short side close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

12. The capacitor chip structure according to claim 7, characterized in that: The second electrical connection structure includes a fifth conductive layer and a second pad; The fifth conductive layer is located in the third through hole and on a portion of the surface of the insulating layer away from the glass substrate; The second pad is located on a side of the fifth conductive layer away from the insulating layer.

13. The capacitor chip structure according to claim 12, wherein: The cross-sectional pattern of the second solder pad on the first surface includes two oppositely arranged third long sides and two oppositely arranged third short sides, the third long sides are arranged parallel to the first short sides, the third short sides are arranged parallel to the first long sides, the length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one third of the length of the first long side.

14. The capacitor chip structure according to claim 13, characterized in that: The length of the third short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; And / or, the length of the third long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

15. The capacitor chip structure according to claim 13, wherein: On one side of the second end of the capacitor chip structure, a distance between the third long side close to the second end of the capacitor chip structure and the first short side is greater than or equal to 15 microns and less than or equal to 40 microns; And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

16. The capacitor chip structure according to claim 8, characterized in that: The thickness of the first pad is greater than or equal to 15 micrometers and less than or equal to 60 micrometers.

17. The capacitor chip structure according to claim 12, wherein: The thickness of the second pad is greater than or equal to 15 micrometers and less than or equal to 60 micrometers.

18. The capacitor chip structure according to claim 1, wherein: The value by which the boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer is greater than or equal to 3 micrometers.

Images