Semiconductor structure

Abstract

A semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between a first isolation structure and a second isolation structure in a substrate. The semiconductor structure includes a gate structure disposed on the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure to the first isolation structure, wherein the first gate extension has a first depth measured from the top surface of the substrate. The semiconductor structure also includes a second gate extension protruding from the gate structure into the second isolation structure, wherein the second gate extension has a second depth different from the first depth.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor structure. Background Art

[0002] The semiconductor industry is experiencing rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from repeated reductions in minimum feature size, which allows more components or devices to be integrated into a given area. Although existing strategies for integrating devices into static random-access memory (SRAM) cells are generally adequate, they are not completely satisfactory in all aspects. For example, achieving various performance goals (such as improved read margin and write margin) in integrated SRAM devices remains a challenge. Utility Model Content

[0003] One embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed on the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, wherein the first gate extension has a first depth measured from a top surface of the substrate. The semiconductor structure also includes a second gate extension protruding from the gate structure into the second isolation structure, wherein the second gate extension has a second depth measured from the top surface of the substrate, the second depth being different from the first depth.

[0004] Another embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region and a second active region disposed in a substrate. The semiconductor structure includes an isolation structure interposed between the first active region and the second active region. The semiconductor structure includes a first gate structure disposed on the first active region. The semiconductor structure includes a first gate extension extending from the first gate structure into the isolation structure, wherein the first gate extension has a first depth. The semiconductor structure includes a second gate structure disposed on the second active region. The semiconductor structure also includes a second gate extension extending from the second gate structure to the isolation structure, wherein the second gate extension has a second depth greater than the first depth.

[0005] Another embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed on the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, wherein the first gate extension has a first depth measured from the top surface of the substrate. The semiconductor structure also includes a second gate extension protruding from the gate structure into the second isolation structure, wherein the second gate extension has a second depth measured from the top surface of the substrate, the second depth being different from the first depth, wherein a ratio of the second depth to the first depth is 1.7 to 55. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of some embodiments of the present disclosure may be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 a flow chart illustrating an exemplary method of fabricating a semiconductor device according to some embodiments;

[0008] Figure 2A 、 Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12A 、 Figure 12B 、 Figure 13A and Figure 13B The exemplary semiconductor devices according to some embodiments are respectively described in Figure 1 a first cross-sectional view of an intermediate stage of an exemplary method;

[0009] Figure 14 and Figure 15 The exemplary semiconductor devices according to some embodiments are respectively described in Figure 1 a second cross-sectional view of an intermediate stage of the exemplary method;

[0010] Figure 16 an exemplary circuit diagram illustrating an exemplary memory cell according to some embodiments;

[0011] Figure 17 Description of some embodiments Figure 16 An exemplary layout of an exemplary memory cell corresponding to the circuit diagram of

[0012] Figure 18 、 Figure 19 、 Figure 20 and Figure 21 Exemplary memory cells according to some embodiments are respectively described along Figure 17 A cross-sectional view taken along line AA' of the exemplary layout;

[0013] Figure 22 an exemplary circuit diagram illustrating an exemplary memory cell according to some embodiments;

[0014] Figure 23 Description of some embodiments Figure 22 An exemplary layout of an exemplary memory cell corresponding to the circuit diagram of

[0015] Figure 24 、 Figure 25 、 Figure 26 and Figure 27 Exemplary memory cells according to some embodiments are respectively described along Figure 23 sectional view along line AA' of the exemplary layout.

[0016]

Explanation of symbols

[0017] 10: Method

[0018] 12, 14, 16, 18, 20, 22, 24, 25A, 25B, 26, 28, 30, 32: Operation

[0019] 50: First etching process

[0020] 200:Semiconductor device

[0021] 202:Substrate

[0022] 202A, 202B, 202C, 202D, 202E: doped regions

[0023] 202S: bottom area

[0024] 203B, 203C: Channel area

[0025] 204A, 204B, 204C, 204D, 204E: Isolation structure

[0026] 206, 208, 216, 226: dielectric layer

[0027] 212, 222, 224: Depression

[0028] 220A, 220B, 220C: Patterned masks

[0029] 222A: First depression

[0030] 222B: Second depression

[0031] 228: Interface layer

[0032] 230: Gate dielectric layer

[0033] 232: Gate electrode

[0034] 234A, 244B: Gate structure

[0035] 234B, 244C: Gate structure

[0036] 234C: Gate structure

[0037] 252A, 252B, 252C: Gate extension

[0038] 254A, 254B, 254C: Gate extension

[0039] 260, 262, 560, 562, 564, 570, 572, 574, 660, 662, 664, 668, 670, 672, 674, 678: Source / drain structures

[0040] 270, 272: Gate spacer

[0041] 400, 450: Circuit diagram

[0042] 500: memory unit

[0043] 502:Substrate

[0044] 502A, 502B, 502C: doped regions

[0045] 504: Isolation Structure

[0046] 540N, 540P, 542N, 550N, 550P, 552N: Gate structure

[0047] 582: first gate extension

[0048] 584: Second gate extension

[0049] 586: Third gate extension

[0050] 588: Fourth gate extension

[0051] 600: memory unit

[0052] 602:Substrate

[0053] 602A, 602B, 602C, 602D, 602E: doped regions

[0054] 604: Isolation Structure

[0055] 640N, 640P, 642N, 644N, 650N, 650P, 652N, 654N: Gate structure

[0056] 682: First gate extension

[0057] 684: Second gate extension

[0058] 686: Third gate extension

[0059] A-A', B-B': line

[0060] BBL, / BLA, / BLB: bit line

[0061] BL, BLA, BLB: bit lines

[0062] D1, D2, D3, D4: Depth

[0063] F1: First Device

[0064] F2: Second Device

[0065] PD1, PU1, PD2, PU2, PG1, PG2, PG3, PG4: Transistors

[0066] R1, R2: device area

[0067] Vdd: power supply voltage

[0068] Vss: ground

[0069] W': Depression width

[0070] WL: character line

[0071] WLA, WLB: character line

[0072] X: axis

[0073] Y: axis

[0074] Z: axis DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify some embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, some embodiments of the present disclosure may repeat element symbols or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0076] Furthermore, for ease of description, some embodiments of the present disclosure may use spatially relative terms, such as "below," "beneath," "below," "above," and "above," to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0077] Figure 1 A flowchart illustrating a method 10 for forming a semiconductor device 200 according to one or more embodiments of the present disclosure. In some embodiments, the operations of the method 10 may be performed with the semiconductor device 200 formed on a plane defined by the Y axis and the Z axis. Figures 2A to 13B The cross-sectional views of the semiconductor device 200 at different fabrication stages are depicted along a plane defined by the X-axis and the Z-axis. Figure 14 and Figure 15 It should be noted that the method 10 is only an example and is not intended to limit some embodiments of the present disclosure. Therefore, it should be understood that in Figure 1 Additional operations may be provided before, during, and after method 10, and certain other operations may be described only briefly in some embodiments of the present disclosure.

[0078] See Figure 1 、 Figure 2A and Figure 2BAt operation 12, a substrate 202 is provided for the semiconductor device 200. The substrate 202 may include a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 202 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 202 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0079] In some embodiments, substrate 202 includes a plurality of doped regions (or doped wells) 202A, 202B, 202C, 202D, and 202E (collectively referred to as doped regions 202A-202E) disposed on a bottom region 202S, with bottom region 202S enclosed by a dashed line for illustrative purposes only. Because doped regions 202A-202E are used to provide active devices, such as transistors in a memory device, doped regions 202A-202E are also referred to as active regions 202A-202E. Doped regions 202A-202E can be formed by performing a series of patterning and doping processes. For example, a patterned mask layer (not depicted) can be formed on substrate 202 to expose portions of the underlying substrate 202. The patterned mask layer can include a photoresist material that can be patterned using lithography techniques. Typically, lithography techniques utilize a photoresist material that is deposited, irradiated (or exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material forming the patterned mask layer protects the underlying material from subsequent processing steps, such as doping or etching.For example, the patterned mask layer may alternatively include a dielectric material, such as an oxide patterned by lithographic techniques.

[0080] The patterned mask is then used to dope the exposed portions of substrate 202 and form doped regions 202A-202E. The exposed portions of substrate 202 may be doped by implantation, diffusion, or the like. In some embodiments, subsets of doped regions 202A-202E are used to provide semiconductor devices (e.g., transistors) of different conductivity types. For example, doped region 202C may include n-type dopants to form an n-type well (or n-well) for a p-type device (e.g., a pull-up transistor in an SRAM cell), and doped regions 202A, 202B, 202D, and 202E may each include p-type dopants to form p-type wells (or p-wells) for n-type devices, such as a pull-down transistor and a pass transistor in an SRAM cell. In some embodiments, doped regions 202A-202E include the same dopant (n-type or p-type) to provide devices of the same conductivity type. Exemplary p-type dopants may include boron, gallium, indium, or the like, or combinations thereof, while exemplary n-type dopants may include phosphorus, arsenic, or the like, or combinations thereof.

[0081] As depicted, doped regions 202A-202E are formed in the upper portion of substrate 202, leaving bottom region 202S undoped or substantially undoped. In other words, doped regions 202A-202E do not extend through the entire substrate 202. During the doping process, the depth of each doped region 202A-202E can be controlled by adjusting parameters such as implantation energy. In some embodiments, doped regions 202A-202E having the same type of dopant can be doped with different concentrations of the dopant.

[0082] In some embodiments, after forming the doped regions 202A-202E, a mask layer comprising a pad oxide layer and an overlying pad nitride layer is formed on the substrate 202, for example, to protect the underlying material during subsequent processing steps. The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process, a chemical oxidation process, chemical vapor deposition (CVD), or a combination thereof. The pad oxide layer may serve as an adhesion layer between the substrate 202 and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. The pad nitride layer may be formed using CVD, low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or a combination thereof.

[0083] Still see Figure 1 、 Figure 2A and Figure 2BIn operation 14, a plurality of isolation structures 204A, 204B, 204C, and 204D (collectively referred to as isolation structures 204A-204D) are formed in substrate 202, wherein each isolation structure 204A-204D separates two adjacent doped regions 202A-202E along a lateral direction (e.g., along the Y-axis) and extends vertically (e.g., along the Z-axis) across the bottom surface of each doped region 202A-202E. In other words, isolation structures 204A-204D penetrate the bottom region 202S of substrate 202, thereby electrically isolating adjacent doped regions 202A-202E from each other.

[0084] In some embodiments, isolation structures 204A-204D have a multi-layer structure and include a dielectric layer 208 disposed on dielectric layer 206, wherein dielectric layer 206 and dielectric layer 208 have different compositions. In some embodiments, each of dielectric layer 206 and dielectric layer 208 comprises an oxide, such as silicon oxide (SiO and / or SiO2), a nitride, or a combination thereof. In some embodiments, isolation structure 204 has a single-layer structure. In some embodiments, isolation structures 204A-204D comprise shallow trench isolation (STI) structures.

[0085] The isolation structures can be formed by patterning a mask layer to expose portions of the substrate 202 between adjacent doped regions 202A-202E. The mask layer can be patterned by a lithography process similar to the etching of the substrate 202 described above, followed by an etching process that forms trenches (not depicted) through the substrate 202 using the patterned mask layer as an etch mask. The etching process can include dry etching, wet etching, reactive ion etching (RIE), or the like, or a combination thereof. Subsequently, the dielectric layers 206 and 208 can be deposited in the trenches by any suitable process, such as high-density plasma CVD (HDPCVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system followed by an annealing or curing process to densify the deposited material into another material, such as an oxide), spin coating, or the like, or a combination thereof. Other dielectric materials and / or other formation processes can be used to form the isolation structures 204A-204D.

[0086] A planarization process, such as a chemical-mechanical polish / planarization (CMP) process, can remove any excess dielectric material from dielectric layer 206 and dielectric layer 208. The patterned mask layer on the top surface of substrate 202 can also be removed by the planarization process. Figure 2B As shown in Detail A depicted in FIG, during the planarization process, portions of isolation structures 204A-204D near the interface between each isolation structure 204A-204D and an adjacent doped region may be inadvertently consumed (or over-etched) to form recesses (or depressions) 212. In this regard, a pair of recesses 212 may exist in each isolation structure 204A-204D. In some embodiments, each recess 212 is formed in dielectric layer 206 and dielectric layer 208. Recesses 212 may be defined by a depth D1 measured from the top surface of substrate 202 (e.g., the top surface of doped regions 202A-202E). In some examples, depth D1 may be approximately 0.1 nm to approximately 0.5 nm. In some examples, depth D1 may be less than approximately 0.1 nm and negligible relative to the depth of isolation structures 204A-204D. In some examples, recesses 212 may not be formed by the planarization process.

[0087] See Figure 1 and Figure 3 At operation 16, a dielectric layer 216 is formed on substrate 202, thereby filling recess 212. Dielectric layer 216 may include an oxide material, such as SiO and / or SiO2, and may be used as a gate oxide material for I / O devices disposed in device region R1 of substrate 202. Device region R1 is disposed adjacent to device region R2 for providing core devices, including memory devices such as SRAM devices. Dielectric layer 216 may be formed by any suitable process, such as CVD, FCVD, spin coating, or a combination thereof.

[0088] See Figure 1 and Figure 4 At operation 18, a patterned mask 220A is formed on substrate 202 to expose a portion of dielectric layer 216 in device region R2. Patterned mask 220A may comprise a photoresist material and be patterned using the lithography techniques described in detail above with respect to patterning substrate 202. For illustrative purposes only, patterned mask 220A is depicted as covering isolation structure 204A and isolation structure 204B and exposing isolation structure 204C and isolation structure 204D.

[0089] Then, see Figure 1 、 Figure 5A 、 Figure 5B and Figure 5CAt operation 20, a first etching process 50 is applied to the semiconductor device 200. The first etching process 50 is used to remove exposed portions of the dielectric layer 216 from the device region R2, which includes the isolation structures 204C and 204D, and at least portions of the doped regions 202C, 202D, and 202E. The first etching process 50 may include any suitable method, such as wet etching, dry etching, or the like. In some embodiments of the present disclosure, the first etching process 50 includes a wet etching process performed using a wet etchant to selectively remove the dielectric layer 216 and the isolation structures 204A-204D (e.g., dielectric layers 206 and 208), without removing or substantially removing the semiconductor material of the doped regions 202C-202E in the device region R2. In some embodiments, the first etching process 50 is performed using a wet etchant containing hydrofluoric acid (HF), such as dilute HF (DHF). After performing the first etching process 50 , the patterned mask 220A is removed from the semiconductor device 200 by any suitable method, such as plasma ashing or photoresist stripping.

[0090] As depicted, the first etching process 50 is controlled to remove the portion of the dielectric layer 216 on the top surface of the substrate 202 and the portion of the dielectric layer 216 formed in the recess 212, thereby re-exposing the recess 212. In some embodiments of the present disclosure, see Figure 5B and Figure 5C After removing a portion of the dielectric layer 216 from the recess 212, the first etching process 50 is controlled to further remove the portion of the isolation structure 204C and the isolation structure 204D exposed in the recess 212, thereby forming a first recess 222A (such as Figure 5B Detail B in FIG) and the second recess 222B (as shown in FIG). Figure 5C(as shown in detail C in FIG. 1 ). In some embodiments, the duration of the first etching process 50 is extended, for example, to form a first recess 222A and a second recess 222B (collectively, recess 222) after the dielectric layer 216 is removed. For example, the first etching process 50 is allowed to continue after the dielectric layer 216 is removed while other etching parameters, such as the type and concentration of the wet etchant, remain unchanged. Recess 222 can be defined by a depth D2 measured from the top surface of the substrate 202 and a recess width W' measured at the top opening of recess 222, respectively, where depth D2 is greater than depth D1. In some embodiments, depth D2 is approximately 0.1 nanometers (nm) to approximately 1.5 nm, and recess width W' is approximately 20 nm to approximately 25 nm, although some embodiments of the present disclosure are not limited to such ranges. In one example, depth D1 can be approximately 0.1 nm, and depth D2 can be approximately 0.5 nm. In some embodiments, the first etching process 50 may not deepen or expand the recess 212, and thus the depth D2 of the first recess 222A and the second recess 222B is similar to or the same as the depth of the recess 212. For embodiments in which the recess 212 is not observed, the first etching process 50 may remove the exposed corner portions of the isolation structure 204C and the isolation structure 204D.

[0091] See Figure 1 and Figure 6 In operation 22 , a patterned mask 220B is formed on a portion of the device region R1 and the device region R2 .

[0092] Patterned mask 220B can be similar to patterned mask 220A and include a patternable photoresist material. Patterned mask 220B can be formed using a process similar to that used to pattern substrate 202. As depicted, a portion of patterned mask 220B fills first recess 222A but not second recess 222B. In other words, second recess 222B is exposed by patterned mask 220B.

[0093] See Figure 1 、 Figure 7A and Figure 7B At operation 24 , a second etching process 52 is applied to the semiconductor device 200 to selectively deepen the second recess 222B, thereby forming a recess 224 in the isolation structure 204D.

[0094] The second etching process 52 is used to remove portions of the isolation structures 204A-204D exposed by the patterned mask 220B, the patterned mask 220B including, for example, the isolation structures 204C and 204D. The second etching process 52 may be similar to the first etching process 50 and may include any suitable process, such as wet etching, dry etching, etc. In some embodiments of the present disclosure, the second etching process 52 includes performing a wet etching process using a similar or identical wet etchant as used in the first etching process 50. Exemplary wet etchants that can be used for the first etching process 50 and the second etching process 52 include hydrofluoric acid (HF), such as dilute HF (DHF). In some embodiments, the first etching process 50 and the second etching process 52 are performed using different etchants (e.g., different wet etchants). After performing the second etching process 52, the patterned mask 220B is removed from the semiconductor device 200 by any suitable method, such as plasma ashing or photoresist stripping.

[0095] See Figure 7A and Figure 7B , second etch process 52 selectively removes portions of isolation structure 204D (e.g., dielectric layer 206 and dielectric layer 208) exposed in second recess 222B without removing or substantially removing material from doped region 202D and doped region 202E, thereby forming recess 224 in isolation structure 204D. As depicted, recess 224 can be defined by a depth D3 measured from the top surface of substrate 202 and a recess width W' measured at a top opening of the recess, respectively, where depth D3 is greater than depth D2. In some embodiments, depth D3 ranges from approximately 2.5 nm to approximately 5.5 nm, and recess width W' ranges from approximately 20 nm to approximately 25 nm, although some embodiments of the present disclosure are not limited to these ranges. In some embodiments, a ratio of depth D3 to depth D2 ranges from approximately 1.7 to approximately 55, although some embodiments of the present disclosure are not limited to these ranges. In some embodiments, recess width W' remains relatively constant after performing second etch process 52.

[0096] In some embodiments, if the first etching process 50 and the second etching process 52 are implemented using the same wet etchant, such as HF (e.g., DHF), and the duration of the etching processes remains substantially the same, the HF used in the second etching process 52 is used to have a greater concentration than the concentration used in the first etching process 50. In some embodiments, if the first etching process 50 and the second etching process 52 are implemented using the same wet etchant (e.g., HF) with substantially the same concentration, the second etching process 52 is performed for a longer time than the first etching process 50. Whether the first etching process 50 and the second etching process 52 vary based on the concentration of the wet etchant or the duration of the etching process, each of the first etching process 50 and the second etching process 52 is controlled to ensure that the depth D3 is greater than the depth D2 according to some embodiments of the present disclosure. As will be discussed in detail below, the difference between the depth D2 and the depth D3 corresponds to the difference in the channel widths of the respective gate structures formed on the doped region 202D and the doped region 202E.

[0097] In some embodiments, see Figure 1 After removing patterned mask 220B, in operation 25A, another recess mask (not depicted) may be formed over recess 224 to expose some of first recess 222A (not depicted). Subsequently, in operation 25B, a third etching process (not depicted) may be performed to deepen the exposed first recess 222A to a depth different from depth D2 and depth D3. In some examples, this depth may be within a range similar to depth D3. In some examples, this depth may be greater than depth D2 but less than depth D3. Thus, operations 20-25B provide a method for forming recesses of three different depths. In some embodiments, operations 25A and 25B are omitted from method 10.

[0098] See Figure 1 、 Figure 8 and Figure 9 At operation 26 , a dielectric layer 226 and an interface layer 228 are formed on the device region R1 and the device region R2 , thereby at least partially filling the recess 222 in the device region R1 and the recess 224 in the device region R2 .

[0099] Dielectric layer 226 may include a gate oxide material having a composition similar to or identical to dielectric layer 216 discussed in detail above. Interfacial layer 228 may also include an oxide material, such as silicon oxide (SiO and / or SiO2), conformally formed on substrate 202 in device region R1 and device region R2. Therefore, dielectric layer 226 and interfacial layer 228 may be collectively referred to as oxide layers. In some embodiments, dielectric layer 216, dielectric layer 226, and interfacial layer 228 have the same composition and each include silicon oxide. In some embodiments, dielectric layer 226 is formed on substrate 202 to a thickness T1 that is less than the thickness T2 of dielectric layer 216. In some embodiments, dielectric layer 226 is omitted from semiconductor device 200. Dielectric layer 226 and interfacial layer 228 may each be conformally deposited by any suitable method, such as thermal oxidation, chemical oxidation, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof.

[0100] See Figure 1 and Figure 10 At operation 28 , a gate dielectric layer 230 is formed on the interface layer 228 .

[0101] In some embodiments of the present disclosure, the gate dielectric layer 230 includes a high-k dielectric material having a dielectric constant, or k value, greater than approximately 3.9 (the dielectric constant of silicon dioxide (SiO2)). In this regard, the gate dielectric layer 230 may alternatively be referred to as a high-k (gate) dielectric layer 230. In some examples, the high-k dielectric material may have a dielectric constant greater than approximately 7.0. The high-k dielectric material may include gold oxide or a metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or the like, or a combination thereof. In some embodiments, the gate dielectric layer 230 may alternatively or additionally include silicon oxide, silicon nitride, or a multilayer thereof. The gate dielectric layer 230 may be formed by any suitable process, such as ALD, CVD, PVD, PECVD, molecular beam deposition (MBD), or the like, or a combination thereof.

[0102] Still see Figure 1 and Figure 10 In operation 30, a gate electrode 232 is formed on the gate dielectric layer 230 to complete the formation of a first gate structure 234A in the device region R1 and a second gate structure 234B and a third gate structure 234C in the device region R2. In some embodiments of the present disclosure, each of the gate structures 234A-234C is joined to a subsequently formed source / drain structure in its respective doped region to form a device, such as a transistor.

[0103] In some embodiments, gate electrode 232 includes a conductive material (e.g., a metal) such as polysilicon, tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), or the like, or a combination thereof. In some embodiments, each of gate structures 234A-234C further includes one or more work function metal layers (not depicted) disposed between gate dielectric layer 230 and gate electrode 232. The work function metal layers may include any suitable conductive material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or the like, or a combination thereof. The work function metal layers may be used to provide a p-type metal gate (PMG) structure for p-type devices or an n-type metal gate (NMG) structure for n-type devices.

[0104] In some embodiments, the gate electrode 232 includes polysilicon, and the gate structures 234A-234C serve as dummy gate structures that are subsequently replaced by corresponding metal gate structures, each of which includes one or more work function metal layers and a conductive gate electrode after forming other components of the semiconductor device 200, such as the source / drain structures in the doped regions 202A-202E.

[0105] In some embodiments, see Figure 10 Depending on the thickness of each of dielectric layer 226, interfacial layer 228, and gate dielectric layer 230, in operations 26-30, recess 222 and recess 224 are at least partially filled with one or more of these layers to form a pair of second gate extensions 254A in isolation structure 204C and a pair of second gate extensions 254A and 254B in isolation structure 204D. Because the first gate extensions 252A and 252B and the second gate extensions 254A and 254B protrude along the Z-axis, they may be referred to as vertical gate extensions. In some embodiments of the present disclosure, the first gate extensions 252A and 252B extend (or protrude) to a depth D2 below the top surface of substrate 202, and the second gate extensions 254A and 254B extend (or protrude) to a depth D3 below the top surface of substrate 202. Accordingly, each of the first gate extensions 252A and 252B extends the second gate structure 234B along the sidewall of the doped region 202D by a shorter vertical distance (i.e., depth D2) than each of the second gate extensions 254A and 254B extends the third gate structure 234C along the sidewall of the doped region 202E (i.e., depth D3).

[0106] In some embodiments, the method 10 provides processing flexibility with respect to applying the second etching process 52 to the semiconductor device 200. For example, see Figure 11 , in operation 22, a patterned mask 220C is formed to replace Figure 6 The patterned mask 220C is different from the patterned mask 220B in that the patterned mask 220C is laterally extended to cover only one of the second recesses 222B formed in the isolation structure 204D. Figure 12A and Figure 12B In operation 24 , a second etching process 52 is performed to selectively deepen only the exposed second recess 222B to form a recess 224 having a depth D3 , while the covered second recess 222B is substantially unaffected by the second etching process 52 (ie, has a depth D2 ).

[0107] After completing steps 26 to 30, refer to Figure 13A , in a similar Figure 10 The depicted isolation structure 204C has a pair of first gate extensions 252A and 252B formed therein, and an additional first gate extension 252C and one of the second gate extensions 254B formed in the isolation structure 204D. The isolation structure 204D is configured similarly to the Figure 10 In some embodiments, still refer to Figure 13A In operations 22-30, an additional second gate extension 254C is formed in the isolation structure 204E adjacent to the doped region 202E to correspond to the second gate extension 254B formed in the isolation structure 204D.

[0108] Therefore, refer to FIG. Figure 13B , the first gate structure 244B is bonded to the sidewall of the doped region 202D along the first gate extensions 252B and 252C, and the second gate structure 244C is bonded to the sidewall of the doped region 202E along the second gate extensions 254B and 254C. Furthermore, as depicted, the first gate structure 244B laterally passes through the doped region 202D along the channel region 203B, and the second gate structure 244C laterally passes through the doped region 202E along the channel region 203C, wherein the channel widths W of the channel regions 203B and 203C, measured laterally along the Y-axis, are substantially the same. In some embodiments, as Figure 13B As depicted, the effective channel width W of the second gate structure 244C is effThe effective channel width W is determined based on the channel width W and the total distance ΔW traversed vertically (i.e., depth D3) and laterally (i.e., recess width W′) through the surfaces of the second gate extensions 254B and 254C. Therefore, the effective channel width W can be fine-tuned by adjusting the parameters of at least one of the first etching process 50 and the second etching process 52. eff In some embodiments of the present disclosure, since the depth D2 is substantially smaller than the depth D3 and, as described above, the recess widths W' of the recesses 222 and 224 are substantially constant, the effective channel width W is eff Greater than the channel width W.

[0109] Then, at operation 32, additional operations may be performed. For example, Figure 13A and Figure 13B The embodiment described in is taken as an example, and see Figure 14 and Figure 15 , a gate spacer 270 may be formed along the sidewalls of the first gate structure 244B, and a gate spacer 272 may be formed along the sidewalls of the second gate structure 244C. Each of the gate spacers 270 and 272 may include any suitable dielectric material, such as an oxide, a nitride, or a combination thereof. The gate spacers 270 and 272 may be formed by first depositing a dielectric blanket layer on the semiconductor device 200 and then performing an anisotropic etching process to remove a portion of the dielectric layer, thereby forming the gate spacers 270 and 272. In some embodiments, each of the gate spacers 270 and 272 includes a multi-layer structure.

[0110] Subsequently, a source / drain (S / D) structure 260 is formed in the doped region 202D, and a source / drain structure 262 is formed in the doped region 202E through a series of patterning and epitaxial processes. The source / drain structure 260 is bonded to the first gate structure 244B to form a first device (e.g., a field-effect transistor (FET)) F1, and the source / drain structure 262 is bonded to the second gate structure 244C to form a second device F2. The source / drain structure 260 and the source / drain structure 262 can be formed by etching portions of the doped region 202D and the doped region 202E, respectively, to form source / drain recesses (not depicted), and then performing one or more epitaxial growth processes to form the source / drain structure 260 and the source / drain structure 262 in the respective source / drain recesses. The epitaxial growth process may be implemented using any suitable process, such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof. In some embodiments, the source / drain structure 260 and the source / drain structure 262 are configured to provide devices of the same conductivity type. In some embodiments, the source / drain structure 260 and the source / drain structure 262 are configured to provide devices of different conductivity types. For example, to provide a p-type device, the source / drain structure 260 and / or the source / drain structure 262 may include silicon germanium (SiGe) doped with a p-type dopant as described above. To provide an n-type device, the source / drain structure 260 and / or the source / drain structure 262 may include silicon (Si) doped with an n-type dopant as described above. Source / drain structures 260 and source / drain structures 262 may be referred to individually or collectively as sources or drains, depending on the context.

[0111] Thereafter, an interlayer dielectric (ILD) layer (not depicted) may be formed over the source / drain structures 260 and 262 and planarized to expose the top surfaces of the first gate structure 244B and the second gate structure 244C. If the first gate structure 244B and the second gate structure 244C are used as dummy gate structures, a gate replacement process may be performed to replace the polysilicon-containing gate electrode 232 with the metal-containing gate electrode described above. In some embodiments, performing the gate replacement process includes depositing and optionally patterning one or more work function metal layers before forming the metal-containing gate electrode. The combination of the one or more work function metal layers may be selected based on the conductivity type of the first device F1 and the second device F2. For example, if the first device F1 (or the second device F2) is used as a p-type device (e.g., a PFET), the work function metal layer may be selected to form a p-type metal gate (PMG). If the first device F1 (or the second device F2) is used as an n-type device (e.g., an NFET), the work function metal layer may be selected to form an n-type metal gate (NMG). The first device F1 and the second device F2 may have the same conductivity type. Alternatively, the first device F1 and the second device F2 may have different conductivity types. In addition, the first device F1 and the second device F2 may be formed as transistors of an SRAM cell. It should be noted that Figure 14 and Figure 15 This is for illustrative purposes only, as each depicts one device formed on substrate 202. Additional devices formed on substrate 202 using the disclosed method 10 may include structures similar to first device F1 and second device F2.

[0112] In some embodiments of the present disclosure, the first device F1 formed by the first gate structure 244B can be considered a planar device (e.g., a planar FET), and the second device F2 formed by the second gate structure 244C can be considered a quasi-fin device (e.g., a quasi-FinFET). The difference in channel width (i.e., the channel width W and the effective channel width W) eff The difference between the two allows the formation of planar and quasi-FinFET devices on the same substrate to achieve different performance goals (e.g., low leakage current, high speed, etc.) in integrated structures (e.g., multi-transistor SRAM cells). In addition, different effective channel widths W can be formed by fine-tuning the depth of the recess formed by the disclosed method 10 (e.g., depth D2 and depth D3). eff devices to achieve these performance goals to varying degrees.

[0113] In some embodiments of the present disclosure, depth D2 is from about 0.1 nm to about 1.5 nm, and depth D3 is from about 2.5 nm to about 5.5 nm, resulting in a ratio of depth D3 to depth D2 of from about 1.7 to about 55, as described above. If the ratio of depth D3 to depth D2 is less than about 1.7, the structures of second gate extensions 254B and 254C may not be sufficiently distinguishable from first gate extensions 252B and 252C, and the improved device performance (e.g., higher device speed) provided by second gate extensions 254B and 254C may not be realized in semiconductor device 200. If the ratio of depth D3 to depth D2 is greater than about 55, recess 224 may become too deep (i.e., have a high aspect ratio) and may not be completely filled with the various material layers of the gate structure, including dielectric layer 226, interfacial layer 228, gate dielectric layer 230, and gate electrode 232.

[0114] In some embodiments of the present disclosure, the semiconductor device 200 provides planar devices and quasi-FinFET devices on the same substrate, thereby flexibly tuning multiple devices to have different structures and achieve different device performance suitable for different applications. For example, on the one hand, compared to the quasi-FinFET device (e.g., the second device F2; including the second gate extensions 254B and 254C), the planar device (e.g., the first device F1; including the first gate extensions 252B and 252C) generally exhibits lower leakage current and thus has better reliability. On the other hand, the improved gate control in the quasi-FinFET device can result in higher device speed (e.g., higher current) compared to the planar device. In this regard, integrating planar devices and quasi-FinFET devices on the same substrate can improve existing designs that only include planar devices or quasi-FinFET devices. One example application includes an SRAM cell including multiple transistors of different conductivity types (e.g., n-type or p-type) integrated to meet various design requirements, such as improved read margin and write margin.

[0115] In one instance, see Figure 16, a circuit diagram 400 illustrating a memory cell (memory bit or bit cell) 500. According to some embodiments of the present disclosure, the memory cell 500 is implemented as an SRAM cell including six transistors (6T), and is therefore referred to as a 6T SRAM cell. In some embodiments, the memory cell 500 can be implemented as any of a variety of SRAM cells, such as a two-transistor-two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, and the like. Although the present disclosure is discussed with respect to SRAM cells, it is understood that other embodiments of the present disclosure can also be applied to any memory cell, such as a dynamic random access (DRAM) memory cell. Figure 17 An exemplary layout of a memory cell 500 is depicted, including six transistors arranged in a configuration according to circuit diagram 400 .

[0116] like Figure 16 and Figure 17 As shown, the memory cell 500 includes six transistors: PU1, PD1, PU2, PD2, PG1, and PG2. Transistor PU1 and transistor PD1 form a first inverter, and transistor PU2 and transistor PD2 form a second inverter, wherein the first inverter and the second inverter are cross-coupled with each other. In some embodiments, see Figure 16 The first and second inverters are coupled between a power supply voltage Vdd and a ground Vss. In addition to being coupled to the first and second inverters, transistors PG1 and PG2 are each coupled to a word line (WL). Transistors PG1 and PG2 are further coupled to a bit line (BL) and a bit bar line (BBL), respectively.

[0117] In some embodiments, transistor PU1 and transistor PU2 are referred to as pull-up transistors of memory cell 500; transistor PD1 and transistor PD2 are referred to as pull-down transistors of memory cell 500; and transistor PG1 and transistor PG2 are referred to as access or pass-gate transistors of memory cell 500. In some embodiments, transistors PD1, PD2, PG1, and PG2 respectively include n-type FETs (n-type FETs, NFETs), and transistor PU1 and transistor PU2 respectively include p-type FETs (p-type FETs, PFETs). NFETs and PFETs are referred to as n-type metal-oxide-semiconductor (NMOS) transistors and p-type metal-oxide-semiconductor (PMOS) transistors, respectively. In some embodiments, as described in some embodiments of the present disclosure, memory cell 500 includes four NFETs and two PFETs. In some embodiments, memory cell 500 includes two NFETs and four PFETs. Although Figure 17 The illustrative embodiment shows that the transistor of the memory cell 500 is an NFET or a PFET, but any of various transistors or devices suitable for a memory device can be implemented as at least one transistor, such as a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc.

[0118] Access transistors PG1 and PG2 have gates (e.g., gate layers or gate electrodes) coupled to respective word lines WL. The gates of transistors PG1 and PG2 receive pulse signals via respective word lines WL to respectively allow or prevent access to memory cell 500. Transistors PD1 and PG1 are coupled to each other at the Q bar (Q bar, QB) node, with the drain of transistor PD1 and the source of transistor PG1 coupled to each other. Transistors PD1 and PG2 are coupled to each other at the Q node, with the drain of transistor PD2 and the source of transistor PG2 coupled to each other.

[0119] See Figures 17 to 21 , an embodiment of a memory cell 500 showing a detailed arrangement of various transistors is described. Figure 17 depicts a top view of an exemplary layout of memory cell 500, and Figures 18 to 21 Memory cells 500 are depicted along Figure 17 1 is a cross-sectional view of the line AA' extending through the transistor PD2, the transistor PU2 and the transistor PG1. It should be noted that for clarity, Figures 17 to 21Part of the memory cell 500 may be omitted in one or more of the memory cells 500. For example, part of the isolation structure 504 separating adjacent transistors may be omitted in the memory cell 500. Figures 18 to 21 Depicted in Figure 17 Omitted in .

[0120] Still see Figures 17 to 21 Memory cell 500 is disposed on a substrate 502 similar to substrate 202 described above. Substrate 502 includes a plurality of doped regions (or active regions) 502A, 502B, and 502C laterally separated by isolation structures 504. Doped regions 502A and 502C are doped with p-type dopants to provide NFETs, such as transistors PD1, PD2, PG1, and PG2, and doped region 502B is doped with n-type dopants to provide PFETs, such as transistors PU1 and PU2. In doped region 502C, gate structure 540N is bonded to source / drain structure 562 to form transistor PD1, and gate structure 542N is bonded to source / drain structure 564 to form transistor PG1. In doped region 502B, gate structure 540P is bonded to source / drain structure 560 to form transistor PU1, and gate structure 550P is bonded to source / drain structure 570 to form transistor PU2. In doped region 502A, gate structure 550N is joined to source / drain structure 572 to form transistor PD2, and gate structure 552N is joined to source / drain structure 574 to form transistor PG2. In some embodiments of the present disclosure, gate structures 540N, 540P, 542N, 550N, 550P, and 552N may be formed on a channel region (not depicted) interposed between a pair of corresponding source / drain structures. Gate structures 540N, 540P, 542N, 550N, 550P, and 552N may be similar in structure and formation method (e.g., method 10) to first gate structure 544B or second gate structure 544C, described in detail above. Source / drain structures 560 , 562 , 564 , 570 , 572 , and 574 may be formed in corresponding doped regions and may be similar in structure and formation method (eg, method 10 ) to source / drain structure 260 or 262 , described in detail above.

[0121] Typically, the performance of an SRAM device can be enhanced by increasing the read margin and write margin of a memory cell. The read margin can be evaluated based on the β ratio, where the β ratio is the saturation current (I sat ) and the I sat The ratio (ie, β = I sat _PD / I sat_PG). The write margin can be evaluated based on the α ratio, where the α ratio is the I / O ratio of the transistor PU in a given memory cell. sat With transistor PG's I sat The ratio (that is, α = I sat _PU / I sat _PG). In many cases, increasing the β ratio results in an increase in read margin, while decreasing the α ratio results in an increase in write margin. sat _PD, reduce I sat _PG or both can improve the read margin. Similarly, by reducing I sat _PU, increase I sat _PG or both can improve write margin. In addition, reducing I sat _PU and increase I sat _PD can improve read margin and write margin.

[0122] With respect to SRAM cells, such as memory cell 500, each transistor has an I sat By increasing the effective channel width of the transistor (eg, the W of the second gate structure 244C described above), eff ) can be increased independently, the effective channel width can be achieved by vertically extending the corresponding gate structure toward the underlying isolation structure to form a gate extension. In this regard, a deeper gate extension results in a larger effective channel width, which in turn produces a larger I sat For example, a planar device (e.g., first device F1) with little or no gate extension (e.g., depth D2) typically exhibits lower I than a quasi-fin device (e.g., second device F2) with a substantial gate extension (e.g., depth D3). sat Therefore, taking the memory cell 500 as an example, independently tuning the gate extension depths of the transistors PD, PG, and PU can improve the read margin, write margin, or both of the memory cell 500 .

[0123] For example, in some embodiments, see Figure 18, gate structure 550P corresponding to transistor PU2 includes a first gate extension 582 extending along the sidewalls of doped region 502B, and gate structures 550N and 542N corresponding to transistors PD2 and PG1, respectively, each including a second gate extension 584 extending along the sidewalls of doped region 502A and doped region 502C, respectively, into isolation structure 504. In some embodiments of the present disclosure, first gate extension 582 is similar to first gate extension 252 and is defined by a depth D2, respectively, and second gate extension 584 is similar to second gate extension 254 and is defined by a depth D3, respectively, where depths D2 and D3 are as described above. For example, depth D2 may range from approximately 0.1 nm to approximately 1.5 nm, and depth D3 may range from approximately 2.5 nm to approximately 5.5 nm. In this regard, transistor PU2, similar to the first device F1 described above, is considered a planar device, while transistor PD2 and transistor PG1, similar to the second device F2 described above, are each considered a quasi-fin device. Therefore, I sat _PD&I sat _PG relative to I sat _PU increases, thereby improving the read margin (ie, increased β ratio).

[0124] In some embodiments, see Figure 19 , gate structure 550P includes a first gate extension 582, gate structure 550N includes a second gate extension 584, and gate structure 542N includes a third gate extension 586 extending along the sidewall of doped region 502C into isolation structure 504. In some embodiments of the present disclosure, third gate extension 586 is similar to first gate extension 252 and is defined by a depth D2. In this regard, transistor PU2 and transistor PG1, which are similar to the first device F1 described above, are considered planar devices, while transistor PD2, which is similar to the second device F2 described above, is considered a quasi-fin device. Therefore, relative to I sat _PG and I sat _PU,I sat _PD will increase, thereby improving the read margin (ie, increased β ratio).

[0125] In some embodiments, see Figure 20, gate structure 550P includes a first gate extension 582, gate structure 550N includes a second gate extension 584, and gate structure 542N includes a fourth gate extension 588 extending into the isolation structure 504 along the sidewall of the doped region 502C. In some embodiments of the present disclosure, the fourth gate extension 588 is similar to the second gate extension 584 and is defined by a depth D4. In some embodiments of the present disclosure, depth D4 is greater than depth D2 but less than depth D3. For example, depth D4 may range from about 2.5 nm to about 5.5 nm, wherein the ratio of depth D3 to depth D4 may range from about 1.04 to about 2.2. In this regard, transistor PU2 similar to the first device F1 described above is considered a planar device, while transistor PD2 and transistor PG1 similar to the second device F2 described above are considered quasi-fin devices, even though their respective gate extensions have different depths. Therefore, I sat _PD&I sat _PG relative to I sat _PU increases, although I sat _PD increases more than I sat _PG increases, thereby improving the read margin (ie, increased β ratio).

[0126] In some embodiments, if the ratio of depth D3 to depth D4 is less than about 1.04, then I sat On the other hand, if the ratio of depth D3 to depth D4 is greater than 2.2, the process of forming the fourth gate extension 588 may be subject to processing limitations, such as challenges in material deposition in a recess with a high aspect ratio.

[0127] In some embodiments, see Figure 21 , gate structure 550P includes a first gate extension 582, gate structure 542N includes a second gate extension 584, and gate structure 550N includes the aforementioned fourth gate extension 588. In this regard, transistor PU2, which is similar to the aforementioned first device F1, is considered a planar device, while transistor PD2 and transistor PG1, which are similar to the aforementioned second device F2, are considered quasi-fin devices, even though their respective gate structures include gate extensions of different depths. Therefore, I sat _PD&I sat _PG relative to I sat _PU increases, although I sat _PG increases more than I sat _PD is increased, thereby improving the write margin (ie, reduced α ratio).

[0128] In another example, see Figure 22, illustrating a circuit diagram 450 of a memory cell (memory bit or bit cell) 600. According to some embodiments of the present disclosure, the memory cell 600 is implemented as an SRAM cell including eight transistors (8T), and is therefore referred to as an 8T SRAM cell. Figure 23 An exemplary layout of a memory cell 600 is depicted, including eight transistors arranged in a configuration according to circuit diagram 450. Although the memory cell 600 is depicted as an 8T two read / write (2RW) dual-port memory cell, some embodiments of the present disclosure are also applicable to 8T SRAM cells of other configurations.

[0129] like Figure 22 and Figure 23 As shown, memory cell 600 includes eight transistors: PU1, PD1, PU2, PD2, PG1, PG2, PG3, and PG4. In some embodiments, transistor PU1 and transistor PU2 are referred to as pull-up transistors of memory cell 600; transistor PD1 and transistor PD2 are referred to as pull-down transistors of memory cell 600; and transistor PG1, transistor PG2, transistor PG3, and transistor PG4 are referred to as access or pass transistors of memory cell 600, wherein the pull-up transistors, pull-down transistors, and access transistors are similar to the pull-up transistors, pull-down transistors, and access transistors of memory cell 500 described above. Transistor PU1 and transistor PD1 form a first inverter, and transistor PU2 and transistor PD2 form a second inverter, wherein the first and second inverters are cross-coupled with each other. In some embodiments, see Figure 22 The first and second inverters are coupled between a power supply voltage Vdd and ground Vss. In addition to being coupled to the first and second inverters, transistors PG1 and PG3 are coupled to word line WLA, and transistors PG2 and PG4 are coupled to word line WLB. Transistors PG1, PG3, PG2, and PG4 are further coupled to bit line BLA, bit line / BLA, bit line BLB, and bit line / BLB.

[0130] See Figures 23 to 27 , an embodiment of a memory cell 600 showing a detailed arrangement of various transistors is described. Figure 23 depicts a top view of an exemplary layout of memory cell 600, and Figures 24 to 27 The memory cells 600 are depicted along Figure 23 1 is a cross-sectional view of the line BB' extending through the transistors PG3, PG1, PU2 and PD2. It should be noted that for clarity, Figures 23 to 27 Part of the memory cell 600 may be omitted in one or more of the memory cells 600. For example, part of the isolation structure 604 separating adjacent transistors may be omitted in the memory cell 600. Figures 24 to 27 Depicted in Figure 23 Omitted in .

[0131] Still see Figures 23 to 27 Memory cell 600 is disposed on a substrate 602 similar to substrate 202 described above. Substrate 602 includes a plurality of doped regions (or active regions) 602A, 602B, 602C, 602D, and 602E laterally separated by isolation structures 604. Doped regions 602A, 602B, 602D, and 602E are doped with p-type dopants and provide NFETs, such as transistors PD1, PD2, PG1, PG2, PG3, and PG4, and doped region 602C is doped with n-type dopants and provides PFETs, such as transistors PU1 and PU2. In doped region 602A, gate structure 654N is bonded to source / drain structure 678 to form transistor PG3. In doped region 602B, gate structure 650N is bonded to source / drain structure 672 to form transistor PD1, and gate structure 652N is bonded to source / drain structure 674 to form transistor PG1. In doped region 602C, gate structure 650P is joined to source / drain structure 670 to form transistor PU1, and gate structure 640P is joined to source / drain structure 660 to form transistor PU2. In doped region 602D, gate structure 642N is joined to source / drain structure 662 to form transistor PG4, and gate structure 640N is joined to source / drain structure 664 to form transistor PD2. In doped region 602E, gate structure 644N is joined to source / drain structure 668 to form transistor PG2. In some embodiments of the present disclosure, gate structures 640N, 642N, 644N, 640P, 650P, 650N, 652N, and 654N may each be formed on a channel region (not depicted) interposed between a pair of corresponding source / drain structures. The gate structures 640N, 642N, 644N, 640P, 650P, 650N, 652N, and 654N may be similar in structure and formation method (e.g., method 10) to the first gate structure 544B or the second gate structure 544C, as described in detail above. The source / drain structures 660, 662, 664, 668, 670, 672, 674, and 678 may be formed in the corresponding doped regions and may be similar in structure and formation method (e.g., method 10) to the source / drain structures 260 or 262, as described in detail above.

[0132] Similar to the memory cell 500 described above, independently tuning the gate extension depths of transistors PD, PG, and PU in the memory cell 600 can improve the read margin, write margin, or both in the memory cell 600. For example, in some embodiments, see Figure 24, gate structure 640P corresponding to transistor PU2 includes a first gate extension 682 extending along the sidewalls of doped region 602C, and gate structures 654N, 652N, and 640N corresponding to transistors PG3, PG1, and PD2, respectively, each including a second gate extension 684 extending along the sidewalls of doped regions 602A, 602B, and 602D into isolation structure 604. In some embodiments of the present disclosure, first gate extension 682 is similar to first gate extension 252 and is defined by a depth D2, respectively, and second gate extension 684 is similar to second gate extension 254 and is defined by a depth D3, respectively, where depths D2 and D3 are as described above. For example, depth D2 may range from approximately 0.1 nm to approximately 1.5 nm, and depth D3 may range from approximately 2.5 nm to approximately 5.5 nm. In this regard, transistor PU2 similar to the first device F1 described above is considered a planar device, while transistors PG3, PG1, and PD2 similar to the second device F2 described above are considered quasi-fin devices. sat _PD&I sat _PG relative to I sat _PU is increased, thereby improving the read margin (ie, increased β ratio).

[0133] In some embodiments, see Figure 25 , gate structure 640P includes a first gate extension 682, gate structure 640N includes a second gate extension 684, and each of gate structure 654N and gate structure 652N includes a third gate extension 686 extending into isolation structure 604 along the sidewalls of doped region 602A and doped region 602B, respectively. In some embodiments of the present disclosure, third gate extension 686 is similar to first gate extension 252 and is defined by a depth D2. In this regard, transistors PG3, PG1, and PU2 similar to the first device F1 described above are considered planar devices, while transistor PD2 similar to the second device F2 described above is considered a quasi-fin device. Therefore, I sat _PD relative to I sat _PG and I sat _PU will increase, thereby improving the read margin (ie, increased β ratio).

[0134] In some embodiments, see Figure 26, gate structure 640P includes a first gate extension 682, gate structure 640N includes a second gate extension 684, and each of gate structures 654N and 652N includes a fourth gate extension 688 extending into the isolation structure 604 along the sidewalls of the doped regions 602A and 602B, respectively. In some embodiments of the present disclosure, the fourth gate extension 688 is similar to the second gate extension 684 and is defined by a depth D4, which has been described in detail above with respect to the memory cell 500. For example, the depth D4 is greater than the depth D2 but less than the depth D3. In some embodiments, the depth D4 ranges from about 2.5 nm to about 5.5 nm, wherein the ratio of the depth D3 to the depth D4 may range from about 1.04 to about 2.2. The significance of such a range has been described in detail above with respect to the memory cell 500. In this regard, transistor PU2, which is similar to the first device F1 described above, is considered a planar device, while transistors PG3, PG1, and PD2, which are similar to the second device F2 described above, are considered quasi-fin devices, even though the respective gate extensions have different depths. Thus, I sat _PD&I sat _PG relative to I sat _PU increases, although I sat _PD increases more than I sat _PG increases, thereby improving the read margin (ie, increased β ratio).

[0135] In some embodiments, see Figure 27 , gate structure 640P includes a first gate extension 682, each of gate structure 654N and gate structure 652N includes a second gate extension 684, and gate structure 640N includes the aforementioned fourth gate extension 688. In this regard, transistor PU2, similar to the aforementioned first device F1, is considered a planar device, while transistors PG3, PG1, and PD2, similar to the aforementioned second device F2, are considered quasi-fin devices, although their respective gate extensions have different depths. Thus, I sat _PD&I sat _PG relative to I sat _PU increases, although I sat _PG increases more than I sat _PD is increased, thereby improving the write margin (ie, reduced α ratio).

[0136] One embodiment of the present disclosure relates to a method for manufacturing a semiconductor structure. The method includes providing a substrate including a doped region. The method includes forming a first isolation structure and a second isolation structure in the substrate along a plurality of corresponding sidewalls of the doped region. The method includes performing a first etching process to form a first recess in the first isolation structure and a second recess in the second isolation structure, wherein each of the first recess and the second recess has a first depth measured from the top surface of the substrate and extends along the corresponding sidewalls of the doped region. The method includes forming a patterned mask on the first recess to expose the second recess. The method includes performing a second etching process to deepen the second recess to a second depth. The method also includes forming a gate structure on the substrate, resulting in the first gate extending in the first recess and the second gate extending in the second recess. In some embodiments, the patterned mask is a first patterned mask. The method also includes forming an oxide layer on the substrate after forming the first isolation structure and the second isolation structure. Before performing the first etching process, a second patterned mask is formed on the oxide layer to expose a portion of the oxide layer over the first and second isolation structures, wherein the first etching process removes the exposed portion of the oxide layer, thereby exposing the first and second isolation structures. In some embodiments, the first etching process is performed to form a third recess having a first depth, and the method further includes forming a third patterned mask over the first and second recesses. A third etching process is performed to deepen the third recess to a third depth, wherein the third depth is greater than the first depth but less than the second depth, and wherein forming the gate structure results in the third gate extending into the third recess. In some embodiments, the first etching process is performed using a wet etchant having a first concentration, and the second etching process is performed using a wet etchant having a second concentration greater than the first concentration. In some embodiments, the wet etchant includes hydrofluoric acid. In some embodiments, the first etching process is performed for a first duration, and the second etching process is performed for a second duration greater than the first duration. In some embodiments, forming the gate structure includes forming an interfacial layer over the first and second recesses. A gate dielectric layer is formed over the interfacial layer. A gate electrode is formed over the gate dielectric layer. In some embodiments, the gate structure passes through a channel in the doped region, and the method further includes forming a plurality of gate spacers along a plurality of sidewalls of the gate structure. A pair of source / drain structures are formed in the doped region, such that the channel is located between the source / drain structures.

[0137] Another embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed on the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, wherein the first gate extension has a first depth measured from the top surface of the substrate. The semiconductor structure also includes a second gate extension protruding from the gate structure into the second isolation structure, wherein the second gate extension has a second depth measured from the top surface of the substrate, the second depth being different from the first depth. In some embodiments, each of the first gate extension and the second gate extension has a width in a range of 20 nanometers to 25 nanometers. In some embodiments, the first depth is in a range of 0.1 nanometers to 1.5 nanometers. In some embodiments, the second depth is in a range of 2.5 nanometers to 5.5 nanometers. In some embodiments, the ratio of the second depth to the first depth is 1.7 to 55. In some embodiments, the semiconductor structure further includes a second doped region, a third isolation structure, a third gate structure, and the third gate extension. The second doped region is disposed in the substrate. The third isolation structure is adjacent to the second doped region. The third gate structure is disposed on the second doped region. A third gate extension protrudes from the third gate structure into the third isolation structure, the third gate extension having a third depth greater than the first depth but less than the second depth. In some embodiments, the gate structure includes an oxide layer, a gate dielectric layer, and a gate electrode. The oxide layer is located on the doped region. The gate dielectric layer is located on the oxide layer. The gate electrode is located on the gate dielectric layer, wherein the first gate extension and the second gate extension include at least one of the oxide layer, the gate dielectric layer, and the gate electrode.

[0138] Another embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region and a second active region disposed in a substrate. The semiconductor structure includes an isolation structure interposed between the first active region and the second active region. The semiconductor structure includes a first gate structure disposed on the first active region. The semiconductor structure includes a first gate extension extending from the first gate structure into the isolation structure, wherein the first gate extension has a first depth. The semiconductor structure includes a second gate structure disposed on the second active region. The semiconductor structure also includes a second gate extension extending from the second gate structure into the isolation structure, wherein the second gate extension has a second depth greater than the first depth. In some embodiments, the semiconductor structure further includes a plurality of first source / drain structures and a plurality of second source / drain structures. The first source / drain structure is bonded to the first gate structure to form a first transistor. The second source / drain structure is bonded to the second gate structure to form a second transistor. In some embodiments, the first transistor functions as a pull-up transistor, and the second transistor functions as a pull-down transistor, wherein the pull-up transistor and the pull-down transistor form an inverter in a static random access memory cell. In some embodiments, the first transistor functions as a pull-up transistor, and the second transistor functions as a pass transistor in the static random access memory cell. In some embodiments, a ratio of the second depth to the first depth is 1.7 to 55.

[0139] Another embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region inserted between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed on the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, wherein the first gate extension has a first depth measured from the top surface of the substrate. The semiconductor structure also includes a second gate extension protruding from the gate structure into the second isolation structure, wherein the second gate extension has a second depth measured from the top surface of the substrate, the second depth being different from the first depth, wherein a ratio of the second depth to the first depth is 1.7 to 55. In some embodiments, the first depth is in a range of 0.1 nanometers to 1.5 nanometers, and the second depth is in a range of 2.5 nanometers to 5.5 nanometers.

[0140] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of some embodiments of the present disclosure. Those skilled in the art will understand that those skilled in the art can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and that these equivalent constructions can be variously changed, substituted, and modified without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that Include: A first isolation structure and a second isolation structure are disposed in a substrate; a doped region inserted between the first isolation structure and the second isolation structure in the substrate; a gate structure disposed on the doped region; a first gate extension protruding from the gate structure into the first isolation structure, the first gate extension having a first depth measured from a top surface of the substrate; and A second gate extension protrudes from the gate structure into the second isolation structure, the second gate extension having a second depth measured from the top surface of the substrate, the second depth being different from the first depth.

2. The semiconductor structure according to claim 1, wherein Each of the first gate extension and the second gate extension has a width in a range of 20 nanometers to 25 nanometers.

3. The semiconductor structure according to claim 1, wherein: Also includes: a second doped region located in the substrate; a third isolation structure adjacent to the second doped region; a third gate structure located on the second doped region; and A third gate extension protrudes from the third gate structure into the third isolation structure, wherein the third gate extension has a third depth greater than the first depth but less than the second depth.

4. The semiconductor structure according to claim 1, wherein: The gate structure includes: an oxide layer located on the doped region; a gate dielectric layer located on the oxide layer; and A gate electrode is located on the gate dielectric layer, wherein the first gate extension and the second gate extension include at least one of the oxide layer, the gate dielectric layer and the gate electrode.

5. A semiconductor structure, characterized in that Include: A first active region and a second active region are disposed in a substrate; an isolation structure inserted between the first active region and the second active region; a first gate structure disposed on the first active region; a first gate extension extending from the first gate structure into the isolation structure, the first gate extension having a first depth; a second gate structure disposed on the second active region; and A second gate extension extends from the second gate structure into the isolation structure, and the second gate extension has a second depth greater than the first depth.

6. The semiconductor structure according to claim 5, wherein: Also includes: a plurality of first source / drain structures joined to the first gate structure to form a first transistor; and A plurality of second source / drain structures are coupled to the second gate structure to form a second transistor.

7. The semiconductor structure according to claim 6, wherein: The first transistor is used as a pull-up transistor, and the second transistor is used as a pull-down transistor. The pull-up transistor and the pull-down transistor form an inverter in a static random access memory cell.

8. The semiconductor structure according to claim 6, wherein: The first transistor is used as a pull-up transistor, and the second transistor is used as a pass transistor in a static random access memory cell.

9. A semiconductor structure, characterized in that Include: A first isolation structure and a second isolation structure are disposed in a substrate; a doped region inserted between the first isolation structure and the second isolation structure in the substrate; a gate structure disposed on the doped region; a first gate extension protruding from the gate structure into the first isolation structure, the first gate extension having a first depth measured from a top surface of the substrate; and A second gate extension protrudes from the gate structure into the second isolation structure, the second gate extension having a second depth measured from the top surface of the substrate, the second depth being different from the first depth, wherein a ratio of the second depth to the first depth is 1.7 to 55.

10. The semiconductor structure according to claim 9, wherein: The first depth is in a range of 0.1 nm to 1.5 nm, and the second depth is in a range of 2.5 nm to 5.5 nm.

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