Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a substrate, a first gate structure, a first epitaxial structure and a first gap wall structure. The substrate comprises an active region and shallow trench isolation, and the shallow trench isolation comprises at least one groove. The first gate structure is arranged on the shallow trench isolation and comprises a first gate dielectric layer and a first gate layer which are stacked in sequence. The first epitaxial structure is arranged in the active region at two sides of the first gate structure. The first gap wall structure is arranged on the side wall of the first gate structure and located in the groove of the shallow trench isolation, and the lowest point of the first gap wall structure is lower than the lowest point of the first gate structure. Therefore, the structural stability of the gap wall is enhanced, the isolation effect of the gap wall is improved, and the semiconductor device can achieve more optimized operation performance.

Description

Technical Field

[0001] The utility model relates to a semiconductor device, in particular to a semiconductor device with a composite spacer. Background Art

[0002] Semiconductor devices, such as field-effect transistors (FETs), are continuously miniaturizing. This trend is evident in various types of FETs, including metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOSs). However, the miniaturization of semiconductor devices has led to various electrical and / or process limitations. To address this issue, the industry has developed various improvement technologies to address the defects caused by the shrinking line widths in order to improve the distance between adjacent gate structures. Utility Model Content

[0003] The present invention aims to provide a semiconductor device in which a composite spacer structure is arranged on the sidewall of a gate structure to enhance the structural stability of the spacer and improve its isolation effect, so that the semiconductor device can achieve more optimized operating performance.

[0004] An embodiment of the present invention provides a semiconductor device, comprising a substrate, a first gate structure, a first epitaxial structure, and a first spacer structure. The substrate comprises an active area and a shallow trench isolation, wherein the shallow trench isolation comprises at least one groove. The first gate structure is disposed on the shallow trench isolation, and comprises a first gate dielectric layer and a first gate layer stacked in sequence. The first epitaxial structure is disposed in the active area on both sides of the first gate structure. The first spacer structure is disposed on the sidewalls of the first gate structure and is located in the groove of the shallow trench isolation, wherein the lowest point of the first spacer structure is lower than the lowest point of the first gate structure.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate, the substrate comprising an active area and a shallow trench isolation; forming a first gate structure on the shallow trench isolation, the first gate structure comprising a first gate dielectric layer and a first gate layer stacked in sequence; forming a first epitaxial structure in the active area on both sides of the first gate structure; forming a first spacer structure on the sidewall of the first gate structure, the first spacer structure contacting the shallow trench isolation, and the bottommost surface of the first spacer structure being lower than the bottommost surface of the first gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0007] Figure 1 Schematic cross-sectional view of a semiconductor device in a first embodiment of the present invention;

[0008] Figure 2 This is a schematic cross-sectional view of the semiconductor device provided by the present invention after forming a gate structure;

[0009] Figure 3 This is a schematic cross-sectional view of the semiconductor device provided by the present invention after trenches are formed;

[0010] Figure 4 This is a cross-sectional schematic diagram of the semiconductor device provided by the present invention after forming an epitaxial structure;

[0011] Figure 5 A schematic cross-sectional view of the semiconductor device provided by the present invention after the first etching process is performed;

[0012] Figure 6 A schematic cross-sectional view of the semiconductor device provided by the present invention after the second etching process is performed;

[0013] Figure 7 A schematic cross-sectional view of the semiconductor device provided by the present invention after a deposition process is performed;

[0014] Figure 8 A schematic cross-sectional view of the semiconductor device provided by the present invention after the thinning process is performed;

[0015] Figure 9 This is a cross-sectional schematic diagram of the semiconductor device provided by the present invention after forming a stop layer;

[0016] Figure 10 A schematic cross-sectional view of the semiconductor device provided by the present invention after the second etching process is performed;

[0017] Figure 11 A schematic cross-sectional view of the semiconductor device provided by the present invention after the thinning process is performed;

[0018] Figure 12 It is a cross-sectional schematic diagram of a semiconductor device in the second embodiment of the present invention.

[0019] Description of reference numerals:

[0020] 10, 30: semiconductor devices;

[0021] 100: substrate;

[0022] 100t: top surface;

[0023] 102: active region;

[0024] 104: shallow trench isolation;

[0025] 104t: top surface;

[0026] 106: groove;

[0027] 110: first gate structure;

[0028] 110b: lowest point;

[0029] 112: first gate dielectric layer;

[0030] 114: first gate layer;

[0031] 120: first epitaxial structure;

[0032] 122: first metal silicide layer;

[0033] 130: first spacer structure;

[0034] 130b: lowest point;

[0035] 132: first spacer;

[0036] 132b: bottommost surface;

[0037] 134: second spacer;

[0038] 134b: bottommost surface;

[0039] 136: third interstitial wall;

[0040] 136b: bottommost surface;

[0041] 136s: gap;

[0042] 140: contact stop etch layer;

[0043] 142: first stop etching layer;

[0044] 144: second stop etching layer;

[0045] 150: second gate structure;

[0046] 160: second epitaxial structure;

[0047] 170: second spacer structure;

[0048] 172: first spacer;

[0049] 172b: bottommost surface;

[0050] 174: second spacer;

[0051] 174b: bottommost surface;

[0052] 176: third interstitial wall;

[0053] 176b: bottommost surface;

[0054] 178: fourth interstitial wall;

[0055] 178b: bottommost surface;

[0056] 180, 186: plug structure;

[0057] 182: barrier layer;

[0058] 184: conductive layer;

[0059] 190: interlayer dielectric layer;

[0060] 210, 250: gate structure;

[0061] 212, 252: gate dielectric layer;

[0062] 214, 254: gate layer;

[0063] 214t, 254t: top surface;

[0064] 216, 256: insulation layer;

[0065] 218, 258: cap layer;

[0066] 220, 260: groove;

[0067] 230, 270: spacer stacking structure;

[0068] 232, 234, 236, 238: spacer material layer;

[0069] 242: first stop etching the material layer;

[0070] 244: second stop etching the material layer;

[0071] 272, 274, 276, 278: spacer material layer;

[0072] 280: first material layer;

[0073] 282: second material layer;

[0074] 330: first spacer structure;

[0075] 332: first spacer;

[0076] 332b: bottommost surface;

[0077] 332t: top surface;

[0078] 334: second spacer;

[0079] 334b: bottommost surface;

[0080] 334t: top surface;

[0081] 336: third interstitial wall;

[0082] 336s: gap;

[0083] 338: fourth interstitial wall;

[0084] 370: second spacer structure;

[0085] 372: first spacer;

[0086] 372t: top surface;

[0087] 374: second spacer;

[0088] 374t: top surface;

[0089] 376: third interstitial wall;

[0090] B1: lowest point;

[0091] D1: horizontal direction;

[0092] D2: opposite direction;

[0093] S1: distance;

[0094] T1: thickness;

[0095] V1: stoma;

[0096] Y: vertical direction. DETAILED DESCRIPTION

[0097] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, reorganized, or combined to create other embodiments without departing from the spirit of the present invention.

[0098] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 10 according to a first embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a first gate structure 110, a first epitaxial structure 120, and a first spacer structure 130. The substrate 100 may be, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials. At least one shallow trench isolation (STI) 104 is disposed in the substrate 100, and an active area (AA) 102 is defined in the substrate 100, but the present invention is not limited thereto. The first gate structure 110 is disposed on the STI 104 in the substrate 100 and includes, in detail, a first gate dielectric layer 112 and a first gate layer 114 stacked in sequence. The first epitaxial structure 120 is disposed within the active region 102 on both sides of the first gate structure 110 and may include, for example, a doped or undoped semiconductor material such as silicon, silicon germanium (SiGe), silicon phosphor (SiP), silicon carbon, or the like. It should be noted that the shallow trench isolation 104 further includes at least one recess 106 located on one side of the first gate structure 110. The first spacer structure 130 is disposed on the sidewalls of the first gate structure 110 and partially located within the recess 106 of the shallow trench isolation 104. Thus, the lowest point 130b of the first spacer structure 130 is lower than the lowest point 110b of the first gate structure 110. Under this configuration, the first gate structure 110 can serve as a dummy gate line (passing gate) and be arranged across the corresponding shallow trench isolation 104. With the help of the first spacer structures 130 on both sides, they partially extend into the groove 106 of the shallow trench isolation 104 to obtain better isolation effect and have enhanced structural stability to resist stress from the epitaxial structure, so that the semiconductor device 10 can achieve more optimized operating performance.

[0099] In one embodiment, the first gate dielectric layer 112 comprises, for example, a high-k dielectric material, and the first gate layer 114 comprises, for example, a semiconductor material such as, but not limited to, doped polysilicon, doped silicon, or doped amorphous silicon. The first gate layer 114 has, for example, a thickness T1 in a direction Y perpendicular to the substrate 100. A distance S1 between the lowest point 110b of the first gate structure 110 and the lowest point 130b of the first spacer structure 130 is not less than 0.5 times the thickness T1, to ensure that the first spacer structure 130 can effectively extend into the recess 106, thereby achieving effective structural stability and electrical isolation. Specifically, the shallow trench isolation 104 includes, for example, two recesses 106, one located on opposite sides of the first gate structure 110. The first spacer structure 130 is disposed on opposite sidewalls of the first gate structure 110 and partially extends into the two recesses 106.

[0100] The first spacer structure 130 includes a first spacer 132, a second spacer 134, and a third spacer 136, which are sequentially disposed on two opposite sidewalls of the first gate structure 110 in the horizontal direction D1 or the opposite direction D2. In one embodiment, the first spacer 132, the second spacer 134, and the third spacer 136 are each made of a different insulating material, such as silicon oxide, silicon nitride, or silicon carbonitride, but the present invention is not limited thereto. Among them, the first spacer 132 is directly set on the top surface 104t of the shallow trench isolation 104, so that the bottommost surface 132b of the first spacer 132 physically contacts the top surface 104t of the shallow trench isolation 104, while the second spacer 134 and the third spacer 136 partially extend into the groove 106 of the shallow trench isolation 104 and are sandwiched between the first epitaxial structure 120 and the shallow trench isolation 104 in the horizontal direction D1, so that the bottommost surface 136b of the third spacer 136 is lower than the bottommost surface 132b of the first spacer 132, and the bottommost surface 134b of the second spacer 134 is lower than the bottommost surface 132b of the first spacer 132 and the bottommost surface 136b of the third spacer 136. Furthermore, in one embodiment, the third spacer 136 further includes a gap 136S extending into the recess 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104, wherein the lowest point B1 of the gap 136S is lower than the top surface 100t of the substrate 100. Figure 1 shown.

[0101] For example Figure 1As shown, the semiconductor device 10 further includes a second gate structure 150 and a second spacer structure 170 disposed on the active region 102, and a second epitaxial structure 160 disposed within the active region 102. The second gate structure 150 includes, in detail, a second gate dielectric layer 152 and a second gate layer 154 sequentially stacked on the active region 102. The second gate dielectric layer 152, for example, includes a high-k dielectric material, preferably the same material as the first gate dielectric layer 112, and the second gate layer 154 includes, for example, doped polysilicon, doped silicon, doped amorphous silicon, etc., preferably the same material as the first gate layer 114, but is not limited thereto. The second spacer structure 170 is entirely disposed on the top surface 100t of the substrate 100 and on two opposite sidewalls of the second gate structure 150. The second spacer structure 170 further includes a first spacer 172, a second spacer 174, a third spacer 176, and a fourth spacer 178 sequentially disposed along the two opposite sidewalls of the second gate structure 150 in the horizontal direction D1 or the opposite direction D2. The bottommost surface 172b of the first spacer 172, the bottommost surface 174b of the second spacer 174, the bottommost surface 176bt of the third spacer 176, and the bottommost surface 178b of the fourth spacer 178 all physically contact the top surface 100t of the substrate 100 and are flush with the bottommost surface 132b of the first spacer 132.

[0102] It should be noted that the fourth spacer 178 covers the first spacer 172, the second spacer 174, and the third spacer 176, and is partially disposed between the third spacer 176 and the second epitaxial structure 160, and further includes a pore V1 sandwiched between the third spacer 176 and the second epitaxial structure 160. In one embodiment, the first spacer 172, the second spacer 174, the third spacer 176, and the fourth spacer 178 respectively comprise different insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc. The first spacer 172 and the third spacer 176 of the second spacer structure 170 and the first spacer 132 of the first spacer structure 130 preferably comprise the same insulating material, and the fourth spacer 178 of the second spacer structure 170 and the second spacer 134 of the first spacer structure 130 preferably comprise the same insulating material, but the present invention is not limited thereto. Furthermore, the second epitaxial structure 160 is disposed within the active region 102 on opposite sides of the second gate structure 150 and may comprise, for example, a doped or undoped semiconductor material such as silicon, silicon germanium, silicon phosphorus, silicon carbon, or the like. In a preferred embodiment, the second epitaxial structure 160 and the first epitaxial structure 120 include, for example, but not limited to, dopants of the same conductivity type, such as P-type dopants.

[0103] The semiconductor device 10 further includes a first metal silicide layer 122 disposed on the first gate structure 110 and the first epitaxial structure 120, respectively, and a second metal silicide layer 162 disposed on the second gate structure 150 and the second epitaxial structure 160, respectively. The contact stop etch layer 140 and the interlayer dielectric layer 190 integrally cover the substrate 100, the first gate structure 110, the second gate structure 150, the first spacer structure 130, the second spacer structure 170, the first epitaxial structure 120, and the second epitaxial structure 160, as well as a plurality of plug structures 180 and 186 electrically connecting the second epitaxial structure 160 and the second gate structure 150, respectively. In one embodiment, the first metal silicide layer 122 and the second metal silicide layer 162 include, for example, but not limited to, silicides of metal materials such as tungsten, aluminum, copper, titanium, tantalum, cobalt, nickel, platinum, or alloys thereof. The contact etch stop layer 140 conformally covers the substrate 100, the first gate structure 110, the second gate structure 150, the first spacer structure 130, the second spacer structure 170, the first epitaxial structure 120, and the second epitaxial structure 160. The contact etch stop layer 140 specifically includes a first etch stop layer 142 and a second etch stop layer 144 stacked in sequence. In one embodiment, the first etch stop layer 142 and the second etch stop layer 144 each comprise different insulating materials, such as silicon oxide, silicon nitride, or silicon carbonitride, but the present invention is not limited thereto.

[0104] The interlayer dielectric layer 190 further overlies the contact stop etch layer 140 and has a generally flat top surface. In one embodiment, the interlayer dielectric layer 190 comprises an insulating material such as silicon oxide, silicon nitride, or silicon carbonitride, preferably, but not limited to, an insulating material different from the first or second stop etch layer 142, 144. The plug structures 180 and 186 are each disposed within the interlayer dielectric layer 190, penetrating the contact stop etch layer 140 and physically contacting the underlying second metal silicide layer 162. In another embodiment, the plug structures 180 and 186 each comprise a barrier layer 182 and a conductive layer 184 disposed in sequence, wherein the barrier layer 182 comprises, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum, and / or tantalum oxide, and the conductive layer 184 comprises, for example, but not limited to, copper, aluminum, tungsten, or other suitable low-resistivity conductive material.

[0105] According to the semiconductor device 10 of this embodiment, since the second epitaxial structure 160 includes P-type dopants, the second gate structure 150, the second epitaxial structure 160, and the second spacer structure 170 can collectively form a P-type transistor component (PMOS), while the first gate structure 110 can serve as a dummy gate line for another P-type transistor component. Thus, by disposing the first spacer structure 130, which partially extends into the recess 106 of the shallow trench isolation 104, on the sidewall of the dummy gate line (the first gate structure 110), the dummy gate line can achieve better isolation and enhanced structural stability by virtue of the first spacer structure 130 to resist stress from the epitaxial structure, thereby enabling the semiconductor device 10 to achieve more optimized operating performance. A person skilled in the art should readily understand that, although the semiconductor device 10 of this embodiment is described using a P-type transistor component as a specific implementation, the semiconductor device 10 of the present invention is not limited thereto. In another embodiment, N-type transistor components with opposite conductivity may be optionally provided on other active regions 102 of the semiconductor device 10, and dummy gate lines may be provided across corresponding shallow trench isolations 104, thereby achieving the desired operational performance.

[0106] In order to enable a person skilled in the art to easily understand the semiconductor device 10 of the present invention, a method for manufacturing the semiconductor device 10 of the present invention will be further described below.

[0107] See also Figures 2 to 9 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a preferred embodiment of the present invention. First, as Figure 2 As shown, a substrate 100 is provided, and at least one shallow trench isolation 104 is formed on the substrate 100, thereby defining an active region 102 within the substrate 100. Next, two gate structures 210 and 250 are formed on the substrate 100 using a similar process, separated from each other and located on the shallow trench isolation 104 and the active region 102, respectively. Spacer stack structures 230 and 270 are then formed on the sidewalls of the two gate structures 210 and 250, respectively. In one embodiment, the process for fabricating the gate structures 210 and 250 includes, but is not limited to, the following steps. First, a dielectric material layer (not shown, for example, including dielectric materials such as silicon oxide and silicon oxynitride), a semiconductor material layer (not shown, for example, including semiconductor materials such as doped polysilicon, doped silicon, and doped amorphous silicon), an insulating material layer (not shown, for example, including insulating materials such as silicon oxide and silicon oxynitride), and a capping material layer (not shown, for example, including insulating materials such as silicon nitride or silicon carbonitride) are sequentially stacked on the substrate 100. Finally, a patterning process is performed to simultaneously form the following: Figure 2The gate structures 210 and 250 are shown. The gate structure 210 includes a gate dielectric layer 212, a gate layer 214, an insulating layer 216, and a capping layer 218 stacked in order from bottom to top in the vertical direction Y, while the gate structure 250 includes a gate dielectric layer 252, a gate layer 254, an insulating layer 256, and a capping layer 258 stacked in order from bottom to top in the vertical direction Y.

[0108] In another embodiment, the fabrication process of the spacer stack structures 230 and 270 includes, but is not limited to, the following steps: First, multiple deposition and etch-back processes are performed on the substrate 100 to sequentially deposit and etch back a first spacer material layer (e.g., silicon oxide, silicon oxynitride), a second spacer material layer (e.g., silicon nitride, silicon carbonitride), a third spacer material layer (e.g., silicon oxide, silicon oxynitride), and a fourth spacer material layer (e.g., silicon nitride, silicon carbonitride) on the gate structures 210 and 250, respectively. Finally, the spacer stack structures 230 and 270 are formed on opposite sidewalls of the gate structures 210 and 250, respectively. Among them, the details of the spacer stack structure 230 include a spacer material layer 232, a spacer material layer 234, a spacer material layer 236 and a spacer material layer 238 formed in sequence on the two opposite side walls of the gate structure 210 in the horizontal direction D1 or the opposite direction D2, and the details of the spacer stack structure 270 include a spacer material layer 272, a spacer material layer 274, a spacer material layer 276 and a spacer material layer 278 formed in sequence on the two opposite side walls of the gate structure 250 in the horizontal direction D1 or the opposite direction D2. It should be noted that since the spacer stacking structures 230 and 270 can be formed simultaneously, the film thickness and material of the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238 of the spacer stacking structure 230 are, for example, respectively equivalent to the film thickness and material of the spacer material layer 272, the spacer material layer 274, the spacer material layer 276 and the spacer material layer 278 of the spacer stacking structure 270, and the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 preferably include the same material, and the spacer material layer 234, the spacer material layer 238, the spacer material layer 274, and the spacer material layer 278 preferably include materials different from the aforementioned materials, but are not limited to this.

[0109] like Figure 3As shown, an etching process is performed through a mask layer (not shown) to simultaneously form trenches 220 and 260 in the substrate 100, which are located on opposite sides of the gate structures 210 and 250, respectively, and then the mask layer is completely removed. It should be noted that when forming the trench 220, the etching selectivity of the etching process is adjusted so that the shallow trench isolation 104 adjacent to the trench 220 and the spacer stack structure 230 above it (for example, at least including the bottom of the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238, etc.) are etched simultaneously, and a groove 106 is formed in the shallow trench isolation 104. The groove 106 is, for example, located between the two trenches 220 and the gate structure 250 in the horizontal direction D1 or its opposite direction D2, as shown in FIG. Figure 3 shown.

[0110] like Figure 4 As shown, an epitaxial growth process is performed to form a first epitaxial structure 120 in the trench 220, and a second epitaxial structure 160 in the trench 260. The first epitaxial structure 120 and the second epitaxial structure 160 may comprise, for example, doped or undoped semiconductor materials such as silicon, silicon germanium, silicon phosphorus, silicon carbon, or the like, and may preferably include dopants of the same conductivity type, such as, but not limited to, P-type dopants.

[0111] like Figure 5 As shown, a first removal process is performed, such as a dry etching process, a wet etching process, or a dry etching process and a wet etching process performed in sequence, to selectively remove the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 comprising silicon oxide material from the spacer stack structures 230 and 270. It should be noted that when performing the first removal process, etching is performed inward from the exposed portions of the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276, so that the spacer material layer 232 can be etched from its exposed top and the bottom exposed from the groove 106 at the same time, thereby removing a relatively large portion, while the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 are only etched from their exposed top, thereby removing a relatively small portion, as shown in FIG. Figure 5 shown.

[0112] like Figure 6As shown, a second removal process, such as a dry etching process, a wet etching process, or a dry etching and wet etching process performed in sequence, is performed to selectively remove the spacer material layer 234, spacer material layer 238, spacer material layer 274, and spacer material layer 278 comprising silicon nitride material. It should be noted that when performing the second removal process, etching is also performed from the exposed portions of the spacer material layer 234, spacer material layer 238, spacer material layer 274, and spacer material layer 278 inward, so that the spacer material layer 234, spacer material layer 238, and spacer material layer 278 with a larger exposed area can be completely removed. On the other hand, the spacer material layer 274 can be etched only from its exposed top portion, and a relatively small portion is removed to form the second spacer 174.

[0113] In addition, the etching selectivity of the second removal process can be adjusted simultaneously so that the cap layer 218 and the insulating layer 216 of the gate structure 210 are completely removed simultaneously, leaving only the gate dielectric layer 212 and the gate layer 214. In addition, the remaining portion of the spacer material layer 236 is also completely removed, while the spacer material layer 232 is partially removed to form a first spacer 132. The first spacer 132 is located on the sidewalls of the gate dielectric layer 212 and the gate layer 214, and its top surface is lower than the top surface 214t of the gate layer 214, as shown in FIG. Figure 6 As shown, but not limited to this. On the other hand, the cap layer 258 and the insulating layer 256 of the gate structure 250 are also completely removed simultaneously, leaving only the gate dielectric layer 252 and the gate layer 254, and the spacer material layer 272 and the spacer material layer 276 can also be further partially etched from the exposed top to form a first spacer 172 and a third spacer 176. The first spacer 172, the second spacer 174 and the third spacer 176 are sequentially located on the sidewalls of the gate dielectric layer 252 and the gate layer 254 in the horizontal direction D1 or the opposite direction D2, and the first spacer 172 and the second spacer 174 have flush top surfaces and are lower than the top surface 254t of the gate layer 254, as shown in FIG. Figure 6 As shown, but not limited to.

[0114] like Figure 7As shown, a deposition process is performed to sequentially form a first material layer 280 and a second material layer 282 on the substrate 100, conformally covering the substrate 100, the first epitaxial structure 120, the gate layer 214, the first spacer 132, the gate layer 254, the first spacer 172, the second spacer 174, the third spacer 176, and the second epitaxial structure 160. It should be noted that the first material layer 280 is also formed on the surface of the recess 106, while the second material layer 282 preferably has a relatively large film thickness to further fill the recess 106. In one embodiment, the first material layer 280 and the second material layer 282 respectively include different dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc. For example, the first material layer 280 includes silicon oxide, and the second material layer 282 includes silicon nitride, but the present invention is not limited thereto. It should also be noted that when forming the first material layer 280 , part of the first material layer 280 is partially filled into the space between the third spacer 176 and the second epitaxial structure 160 , thereby forming a pore V1 sandwiched between the third spacer 176 and the second epitaxial structure 160 in the first material layer 280 .

[0115] As shown in FIG8 , an etch-back process is performed to completely remove the second material layer 282 covering the substrate 100, the first epitaxial structure 120, the gate layer 214, and the first spacer 132. The second material layer 282 filling the recess 106 is also thinned to form a third spacer 136. Furthermore, the first material layer 280 covering the substrate 100, the first epitaxial structure 120, the gate layer 214, and the top surface of the first spacer 132 is further removed, leaving only the first material layer 280 covered by the third spacer 136, forming a second spacer 134. In this manner, the first spacer 132, the second spacer 134, and the third spacer 136, stacked sequentially in the horizontal direction D1 or in the opposite direction D2, collectively form the first spacer structure 130. The third spacer 136 further includes a slit 136S extending into the recess 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104. On the other hand, during the etching back process, the second material layer 282 covering the gate layer 254, the first spacer 172, the second spacer 174, the third spacer 176, and the second epitaxial structure 160 is completely removed, and the first material layer 280 covering the top surface of the gate layer 254 and the second epitaxial structure 160 is completely removed, thereby forming a fourth spacer 178 that conformally covers the first spacer 172, the second spacer 174, and the third spacer 176, while retaining the air hole V1 sandwiched between the third spacer 176 and the second epitaxial structure 160. In this way, the first spacer 172, the second spacer 174, the third spacer 176, and the fourth spacer 178 are sequentially stacked on the sidewall of the second gate structure 150 in the horizontal direction D1 or the opposite direction D2, thereby forming the second spacer structure 170.

[0116] Then, after the etching back process, a metal silicide process is performed to form a first metal silicide layer 122 and a second metal silicide layer 162 on the exposed top surfaces of the first epitaxial structure 120, the gate layer 214, the gate layer 254, and the second epitaxial structure 160, respectively. In one embodiment, the metal silicide process includes, but is not limited to, the following steps. First, a selective deposition process is performed to form a metal layer (not shown), such as a metal material suitable for reacting with silicon materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, nickel, platinum, or an alloy thereof. Then, a heat treatment process is performed to allow the metal layer to react with the exposed top surfaces of the first epitaxial structure 120, the gate layer 214, the gate layer 254, and the second epitaxial structure 160, respectively, to form the first metal silicide layer 122 and the second metal silicide layer 162. The unreacted metal layer is then removed. The first metal silicide layer 122 and the second metal silicide layer 162 include, for example, silicides of the aforementioned metal materials, but are not limited thereto. Furthermore, after the first metal silicide layer 122 and the second metal silicide layer 162 are formed, the gate dielectric layer 212 and the gate layer 214 stacked in sequence below the first metal silicide layer 122 form a first gate dielectric layer 112 and a first gate layer 114 stacked in sequence, respectively, to form the first gate structure 110 together, and the gate dielectric layer 252 and the gate layer 254 stacked in sequence below the second metal silicide layer 162 form a second gate dielectric layer 152 and a second gate layer 154 stacked in sequence, respectively, to form the second gate structure 150 together, as shown in FIG. Figure 8 Thus, the second gate structure 150 , the second spacer structure 170 and the second epitaxial structure 160 including P-type dopants together form a P-type transistor component, and the first gate structure 110 can form a dummy gate line of another P-type transistor component.

[0117] As shown in FIG9 , a deposition process is performed to sequentially form a first etch stop material layer 242 and a second etch stop material layer 244 on the substrate 100. The first etch stop material layer 242 and the second etch stop material layer 244 conformally cover the substrate 100, the first gate structure 110, the first spacer structure 130, the second gate structure 150, and the second spacer structure 170, and are in physical contact with the first metal silicide layer 122 and the second metal silicide layer 162 formed on the first gate structure 110 and the second gate structure 150. In one embodiment, the first etch stop material layer 242 and the second etch stop material layer 244 respectively include different etch stop materials, such as silicon oxide, silicon nitride, or silicon carbonitride. For example, the first etch stop material layer 242 includes silicon oxide or silicon oxynitride, and the second etch stop material layer 244 includes silicon nitride or silicon carbonitride, but the present invention is not limited thereto.

[0118] Then, an interlayer dielectric layer 190 and plug structures 180 and 186 (such as the ones shown in FIG. 1 ) are formed on the second stop etching material layer 244 to cover the substrate 100. Figure 1 As shown), it can be formed as Figure 1 The semiconductor device 10 shown, wherein the plug structures 180, 186 are formed in the interlayer dielectric layer 190, and sequentially penetrate the second stop etching material layer 244 and the first stop etching material layer 242 to physically contact the second metal silicide layer 162 below. In one embodiment, the production of the plug structures 180, 186 includes but is not limited to the following steps. First, the interlayer dielectric layer 190, the second stop etching material layer 244 and the first stop etching material layer 242 are partially removed through a mask layer (not shown), and a plurality of plug holes (not shown), a second stop etching layer 144 and a first stop etching layer 142 are simultaneously formed. The first stop etching layer 142 and the second stop etching layer 144 stacked in sequence together form the following. Figure 1 The contact stop etch layer 140 is shown, and each of the plug holes penetrates the interlayer dielectric layer 190 and the contact stop etch layer 140 thereunder. Next, a barrier material layer (not shown, such as a conductive barrier material including titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a conductive material layer (not shown, such as copper, aluminum, tungsten or other suitable low-resistivity conductive material) are sequentially stacked in each of the plug holes. Finally, a planarization process is performed to form the following structure: Figure 1 The barrier layer 182 and the conductive layer 184 are shown to form plug structures 180 , 186 .

[0119] Thus, the fabrication of the semiconductor device 10 of this embodiment is completed. According to the fabrication method of the semiconductor device 10 of this embodiment, when forming the trench 220 of the first epitaxial structure 120, a recess 106 is simultaneously etched in the shallow trench isolation 104, so that the bottom of at least a portion of the spacer stack structure 230 (e.g., including at least the spacer material layer 234, the spacer material layer 236, and the spacer material layer 238) can be exposed from the recess 106, thereby partially accelerating the etching rate and extent of at least a portion of the spacer stack structure 230 in the subsequent first removal process and / or the second removal process. In this way, by forming the first spacer structure 130 partially extending into the recess 106 on the sidewall of the dummy gate line (first gate structure 110), the dummy gate line can have a better isolation effect and enhanced structural stability due to the first spacer structure 130 to resist stress from the epitaxial structure, thereby achieving more optimized operating performance of the semiconductor device 10. Furthermore, a person skilled in the art should readily understand that, although the fabrication method of this embodiment is described using the fabrication steps of a P-type transistor component as an implementation example, the actual fabrication process is not limited thereto. In another embodiment, an N-type transistor component having an opposite conductive form may be formed or formed simultaneously, along with a dummy gate line across the corresponding shallow trench isolation 104, to achieve the desired operational performance.

[0120] A person skilled in the art of the present invention should readily understand that, in order to meet actual product requirements, the semiconductor device and its manufacturing method of the present invention may have other aspects and are not limited to the above. The following further describes other embodiments or variations of the semiconductor device and its manufacturing method of the present invention. To simplify the description, the following description primarily details the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with the same reference numerals to facilitate cross-reference between the various embodiments.

[0121] Please refer to Figures 10 to 122 is a schematic diagram of a method for fabricating a semiconductor device 30 according to a second embodiment of the present invention. The structure and fabrication steps of the semiconductor device 30 according to this embodiment are substantially the same as those of the semiconductor device 10 according to the aforementioned embodiment, with the primary differences being that a first spacer structure 330 disposed on the sidewalls of the first gate structure 110 includes a first spacer 332, a second spacer 334, a fourth spacer 338, and a third spacer 336 sequentially disposed in a horizontal direction D1 or in an opposite direction D2, and a second spacer structure 370 disposed on the sidewalls of the second gate structure 150 includes a first spacer 372, a second spacer 374, and a third spacer 376 sequentially disposed in a horizontal direction D1 or in an opposite direction D2.

[0122] In detail, this embodiment is formed as described above. Figure 4 When the trenches 220 and 260 are formed, by adjusting the etching selectivity of the etching process, the shallow trench isolation 104 adjacent to the trench 220 and the spacer stack structure 230 above it (including the spacer stack structure 230) are simultaneously etched. Figure 4 The bottom of the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238 are formed to form a groove (not shown) that can simultaneously expose the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238. Figure 10 As shown, you can proceed as mentioned above Figure 5 The first removal process shown, and the Figure 6 After the second removal process shown, the spacer material layer 236 and the spacer material layer 238 are completely removed, and the first spacer 332 and the second spacer 334 are formed on the sidewalls of the first gate structure 110, and the spacer material layer 276 and the spacer material layer 278 are completely removed, and the spacer material layer 272 and the spacer material layer 274 are partially removed, and the first spacer 372 and the second spacer 374 are formed on the sidewalls of the second gate structure 150.

[0123] In this operation, the first spacer 372 and the second spacer 374 are disposed above the top surface 104t of the shallow trench isolation 104, and the first spacer 332 and the second spacer 334 have top surfaces 332t / 334t and bottom surfaces 332b / 334b flush with each other, the top surfaces 332t / 334t contact each other and are lower than the top surface of the first gate layer, and the bottom surfaces 332b / 334b contact each other and are higher than the top surface 100t of the substrate 100, as shown in FIG. Figure 10As shown, but not limited to this. On the other hand, the first spacer 372 and the second spacer 374 are arranged on the top surface 100t of the substrate 100, and also have top surfaces 372t / 374t that are flush with each other, wherein the top surface 372t / 374t is lower than the top surface of the second gate layer 154. Then, a deposition process is performed to sequentially form a first material layer 280 and a second material layer 282 on the substrate 100, conformally covering the substrate 100, the first epitaxial structure 120, the first gate layer, the first spacer 332, the second spacer 334, the second gate layer 154, the first spacer 372, the second spacer 374 and the second epitaxial structure 160, wherein the first material layer 280 is conformally formed on the surface of the groove 106, and the second material layer 282 further fills the groove 106, as shown in FIG. Figure 10 shown.

[0124] like Figure 11 As shown, an etch-back process is performed to completely remove the second material layer 282 covering the substrate 100, the first epitaxial structure 120, and the first gate layer, and simultaneously thin the second material layer 282 filling the groove 106 to form a third spacer 336. Furthermore, the first material layer 280 covering the substrate 100, the first epitaxial structure 120, and the top surface of the first gate layer is further removed, while retaining the first material layer 280 covered by the third spacer 336 to form a fourth spacer 338. The fourth spacer 338 directly covers and contacts the top surfaces 332t / 334t and bottom surfaces 332b / 334b of the first and second spacers 332 and 334. In this manner, the first spacer 132, the second spacer 134, the fourth spacer 338, and the third spacer 136 are sequentially stacked in the horizontal direction D1 or the opposite direction D2, thereby forming the first spacer structure 330 of this embodiment. The third spacer 336 further includes a slit 336S extending into the recess 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104. The lowest point B1 of the slit 336S is also lower than the top surface 100t of the substrate 100.

[0125] On the other hand, when the etching back process is carried out, the second material layer 282 covering the second epitaxial structure 160, the second gate layer 154, the first spacer 372 and the second spacer 374 is also completely removed, and the first material layer 280 covering the top surface of the second epitaxial structure 160 and the second gate layer 154 is completely removed to form a third spacer 376 that conformally covers the first spacer 372 and the second spacer 374. In this way, the first spacer 372, the second spacer 374 and the third spacer 376 are stacked in sequence in the horizontal direction D1 or its opposite direction D2, and can together form the second spacer structure 370 of this embodiment. It should be noted that the first spacer 372, the second spacer 374 and the third spacer 376 of the second spacer structure 370 respectively include the same insulating material as the first spacer 132, the second spacer 134 and the fourth spacer 338 of the first spacer structure 330, but are not limited to this. Then, as shown in FIG. Figure 11 As shown, a metal silicide process is performed after the etch-back process to form a first metal silicide layer 122 and a second metal silicide layer 162 on the exposed top surfaces of the first epitaxial structure 120 , the first gate layer, the second epitaxial structure 160 and the second gate layer 154 , respectively.

[0126] like Figure 12 As shown, continue to form as mentioned above Figure 9 The first and second etch-stop material layers 242 and 244 conformally cover the substrate 100, the first gate structure 110, the first spacer structure 330, the second gate structure 150, and the second spacer structure 370. Furthermore, the interlayer dielectric layer 190 and the plug structures 180 and 186 are formed using the same fabrication methods as described in the previous embodiments, thereby forming the semiconductor device 30 of this embodiment. Specifically, the semiconductor device 30 also includes a first spacer structure 330, which partially extends into the recess 106, disposed on the sidewalls of the dummy gate line (the first gate structure 110). This allows the dummy gate line to be better isolated and structurally stable by virtue of the first spacer structure 330, thereby resisting stress from the epitaxial structure and achieving more optimized operating performance. Furthermore, the third spacer 336 of the first spacer structure 330 also includes a gap 336S above the shallow trench isolation 104, with the lowest point B1 being lower than the top surface 100t of the substrate 100. Thus, the third spacers 336 are provided to strengthen the structural stability of the first spacer structure 330 and improve its isolation effect, so that the semiconductor device 30 of this embodiment can achieve more optimized operating performance.

[0127] According to the method for fabricating the semiconductor device 30 of this embodiment, while forming the trench 220 of the first epitaxial structure 120, a recess 106 is simultaneously etched within the shallow trench isolation 104, so that the bottom of the spacer stack structure 230 (including the spacer material layer 232, the spacer material layer 234, the spacer material layer 236, and the spacer material layer 238) can be exposed from the recess 106, thereby accelerating the etching rate and extent of the spacer stack structure 230 in the subsequent first removal process and / or the second removal process. In this way, by forming the first spacer structure 330 partially extending into the recess 106 of the shallow trench isolation 104 on the sidewall of the dummy gate line (the first gate structure 110), the dummy gate line can achieve better isolation and enhanced structural stability due to the first spacer structure 330 to resist stress from the epitaxial structure, thereby achieving more optimized operating performance of the semiconductor device 30.

[0128] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor device comprising: A substrate comprising an active area and shallow trench isolation, wherein the shallow trench isolation comprises at least one groove; A first gate structure, disposed on the shallow trench isolation, comprises a first gate dielectric layer and a first gate layer stacked in sequence; a first epitaxial structure, disposed in the active region on one side of the first gate structure; as well as A first spacer structure is disposed on a sidewall of the first gate structure and located in the groove of the shallow trench isolation, wherein the lowest point of the first spacer structure is lower than the lowest point of the first gate structure.

2. The semiconductor device according to claim 1, wherein The first spacer structure includes: A first spacer, a second spacer and a third spacer are sequentially arranged on the sidewall of the first gate structure in a horizontal direction, wherein the second spacer and the third spacer of the first spacer structure partially extend into the shallow trench isolation and are sandwiched between the shallow trench isolation and the first epitaxial structure.

3. The semiconductor device according to claim 2, wherein The bottommost surface of the first spacer of the first spacer structure physically contacts the top surface of the shallow trench isolation.

4. The semiconductor device according to claim 2, wherein The bottommost surface of the first spacer of the first spacer structure contacts the bottommost surface of the second spacer of the first spacer structure and is higher than the top surface of the substrate.

5. The semiconductor device according to claim 4, wherein The first spacer structure further includes: A fourth spacer is disposed between the second spacer and the third spacer in the horizontal direction, and the fourth spacer of the first spacer structure contacts the bottommost surfaces of the second spacer and the third spacer.

6. The semiconductor device according to claim 2, wherein The bottommost surface of the second spacer of the first spacer structure is lower than the bottommost surface of the first spacer.

7. The semiconductor device according to claim 2, wherein: The bottommost surface of the third spacer of the first spacer structure is lower than the bottommost surface of the first spacer.

8. The semiconductor device according to claim 2, wherein: The third spacer of the first spacer structure further includes a slit disposed on the portion extending into the shallow trench isolation.

9. The semiconductor device according to claim 8, wherein The lowest point of the gap is lower than the top surface of the substrate.

10. The semiconductor device according to claim 1, wherein The first gate layer has a thickness in a direction perpendicular to the substrate, and a distance between the lowest point of the first gate structure and the lowest point of the first spacer structure is not less than 0.5 times the thickness.

11. The semiconductor device according to claim 1, wherein Also includes: a second gate structure, disposed on the active area, comprising a second gate dielectric layer and a second gate layer stacked in sequence; a second epitaxial structure, disposed in the active region on one side of the second gate structure; as well as The second spacer structure is arranged on the sidewall of the second gate structure and is located on the top surface of the substrate.

12. The semiconductor device according to claim 11, wherein The second spacer structure includes: A first spacer, a second spacer, and a third spacer are sequentially arranged on the sidewalls of the second gate structure in a horizontal direction, and the bottommost surfaces of the first spacer, the second spacer, and the third spacer of the second spacer structure all physically contact the top surface of the substrate.

13. The semiconductor device according to claim 12, wherein: Also includes: a first metal silicide layer, disposed on the first epitaxial structure and the first gate layer; as well as A second metal silicide layer is disposed on the second gate layer and the second epitaxial structure.

14. The semiconductor device according to claim 13, wherein: Also includes: a contact stop etch layer conformally covering the substrate, the first gate structure, the first spacer structure, the second gate structure, and the second spacer structure; as well as A plurality of plug structures are respectively arranged on the second gate layer and the second epitaxial structure.

15. The semiconductor device according to claim 14, wherein: The invention further includes a fourth spacer, which is partially disposed between the third spacer and the second epitaxial structure and includes air holes sandwiched between the second epitaxial structure and the third spacer.

16. The semiconductor device according to claim 1, wherein The shallow trench isolation includes two grooves located on both sides of the first gate structure respectively. The first spacer structure is arranged on both sidewalls of the first gate structure and is located in the two grooves of the shallow trench isolation.

Images