Server power supply output control circuit

Abstract

The utility model provides a server power supply output control circuit, and relates to the technical field of server power supplies, the control circuit comprises a CPLD, a first switch tube and a second switch tube; when the CPLD detects that the first power supply and the second power supply connected with the input end of the CPLD meet the preset triggering condition, the CPLD controls the first switch tube to be not conducted and controls the second switch tube to be conducted, so that the level signal of the enabling end of the fan is low level, the fan power supply is disconnected with the fan, and the first power supply or the second power supply is used for carrying out power-down maintenance on the server. The preset triggering condition comprises that a first input power supply state signal of the first power supply is a low level and a second input power supply state signal of the second power supply is changed from a high level to a low level, or the first input power supply state signal and the second input power supply state signal are both low levels. The power supply output holding time can be effectively prolonged, the utilization rate of the power supply is improved, and the use requirement of a high-density power supply is better met.

Description

Technical Field

[0001] The present application relates to the technical field of server power supplies, and in particular to a control circuit for server power output. Background Art

[0002] With the widespread use of servers, dual power inputs are often provided to improve server stability: a primary power source and a backup power source. If the primary power source fails, the backup power source automatically switches to the backup power source. If both power sources fail, a long hold-up time, such as 12 milliseconds (ms), is required to ensure that the power supply can continue to provide stable output to the server.

[0003] Currently, the power supply output hold time can be extended by increasing the capacitance of the capacitor. However, this method cannot meet the requirements of high-density power supply use. Utility Model Content

[0004] The present application provides a control circuit for server power output, which is used to effectively extend the power output retention time, improve the power utilization rate, and better meet the use requirements of high-density power supplies.

[0005] The present application provides a control circuit for a server power output, comprising: a complex programmable logic device (CPLD), a first switch tube, and a second switch tube;

[0006] The output end of the CPLD is connected to the first switch tube, the first switch tube is connected to the second switch tube and connected to the fan power supply of the server, and the second switch tube is connected to the enable end of the fan of the server;

[0007] The CPLD is configured to, upon detecting that a first power supply and a second power supply connected to an input terminal of the CPLD meet a preset trigger condition, control the first switch tube to be non-conductive and control the second switch tube to be conductive, so that a level signal at the enable terminal is low, the fan power supply is disconnected from the fan, and the server is powered off and maintained via the first power supply or the second power supply. The preset trigger condition includes that a first input power supply status signal of the first power supply is low and a second input power supply status signal of the second power supply changes from high to low, or that both the first input power supply status signal and the second input power supply status signal are low.

[0008] In one possible implementation, the output end of the CPLD is connected to the gate of the first switching tube, the drain of the first switching tube is connected to the gate of the second switching tube and is connected to the fan power supply via a first resistor, and the source of the first switching tube is grounded; the drain of the second switching tube is connected to the enable end via a second resistor, and the source of the second switching tube is grounded.

[0009] In one possible implementation, the CPLD is specifically used to: when it is detected that the first power supply and the second power supply meet a preset trigger condition, output a low level to the gate of the first switch tube, control the first switch tube to be non-conductive, and control the second switch tube to be conductive, so that the level signal of the enable end is a low level.

[0010] In one possible implementation, the CPLD is further configured to: when it is detected that both the first power supply and the second power supply do not meet a preset trigger condition, control the first switch tube to be turned on, and control the second switch tube to be turned off, so that the level signal at the enable end is high, and the fan power supply is connected to the fan.

[0011] In one possible implementation, the CPLD is specifically configured to: when the CPLD detects that both the first power supply and the second power supply do not meet a preset trigger condition, output a high level to the gate of the first switch tube to control the first switch tube to be turned on, and control the second switch tube to be turned off, so that the level signal at the enable end is a high level.

[0012] In a possible implementation, the CPLD is further configured to: when detecting that the first input power supply status signal and / or the second input power supply status signal is at a high level, output a level signal of the CPLD at a high level.

[0013] In a possible implementation, when the first power supply is working normally, the first input power supply status signal is at a high level; when the second power supply is working normally, the second input power supply status signal is at a high level.

[0014] In a possible implementation, the first switch tube and the second switch tube are MOS tubes or triodes.

[0015] In a possible implementation, the high level is 3.3V and the low level is 0V.

[0016] In a possible implementation, the duration during which the fan power supply is disconnected from the fan is greater than a first duration threshold and less than a second duration threshold, and the first duration threshold is less than the second duration threshold.

[0017] The control circuit of the server power output provided by the present application includes a CPLD, a first switch tube and a second switch tube; when the CPLD detects that the first power supply and the second power supply connected to the input end of the CPLD meet the preset trigger conditions, the CPLD controls the first switch tube to be non-conductive and controls the second switch tube to be conductive, so that the level signal of the enable end of the fan is low, the fan power supply is disconnected from the fan, that is, the fan stops, and the server is powered off and maintained by the first power supply or the second power supply; wherein the preset trigger conditions include the first input power supply status signal of the first power supply being low and the second input power supply status signal of the second power supply being changed from high to low, or the first input power supply status signal and the second input power supply status signal are both low. The present application can reduce the server load and extend the power output maintenance time by turning off the fan power supply for a short time, without affecting the heat dissipation of the server; while ensuring that the application is risk-free, the utilization rate of the power supply can be effectively improved to better meet the use requirements of high-density power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of a control circuit for a server power output according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a control circuit for server power output provided by another embodiment of the present application.

[0021] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0022] The exemplary embodiments will be described in detail herein, with examples shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements, unless otherwise indicated. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0023] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0024] With the widespread use of servers, to improve server stability, they are typically provided with two power inputs: a primary input and a backup input. If the primary input fails, it automatically switches to the backup input, typically in less than 10ms. If both power inputs lose power, the power output holdup time (a key specification for server power supplies) must be long, such as 12ms, to ensure the power supply can continue to provide stable output to the server. This means that the power output remains within specification within this holdup time, taking into account the phase angle and time required for power recovery.

[0025] At present, as power supplies become increasingly powerful and their density increases, the power supply output hold time is strongly related to the capacitance value of the capacitor and the load. The power supply output hold time can be extended by increasing the capacitance value of the capacitor, but this method cannot meet the requirements of high-density power supplies.

[0026] In addition, the power output maintenance time can be extended by reducing the supported load. However, for current high-power power supplies, it is common to support 70% of the power supply load to ensure that the power supply does not shut down, which causes the server to be unable to perform at its maximum performance.

[0027] In summary, extending the power output retention time through the current method may require taking on the risk of a small probability of power grid failure, or requiring the use of a higher power power supply.

[0028] Based on the above problems, the present application provides a control circuit for the power supply output of a server. When the two power inputs of the server lose power, the server load can be reduced and the power output maintenance time can be extended by short-term shutting down the fan power of the server without affecting the heat dissipation of the server. While ensuring that the application is risk-free, the utilization rate of the power supply can be effectively improved to better meet the use requirements of high-density power supplies.

[0029] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of a control circuit for a server power output according to an embodiment of the present application. Figure 1 As shown, the server power output control circuit 100 of the embodiment of the present application includes: a CPLD 101 , a first switch tube 102 and a second switch tube 103 .

[0031] The output end of the CPLD 101 is connected to the first switch tube 102 , the first switch tube 102 is connected to the second switch tube 103 and connected to the fan power supply of the server, and the second switch tube 103 is connected to the enable end of the fan of the server.

[0032] The CPLD 101 is configured to control the first switch tube 102 to be non-conductive and the second switch tube 103 to be conductive when detecting that the first power supply and the second power supply connected to the input end of the CPLD 101 meet a preset trigger condition, so that the level signal of the enable end of the fan is low, the fan power supply is disconnected from the fan, and the server is powered off and maintained via the first power supply or the second power supply. The preset trigger condition includes that the first input power supply status signal of the first power supply is low and the second input power supply status signal of the second power supply changes from high to low, or that both the first input power supply status signal and the second input power supply status signal are low.

[0033] In the embodiment of the present application, the CPLD 101 of the server is a programmable integrated circuit used to implement specific logical functions of the server, and can be used to control various hardware components in the server, such as fans.

[0034] Optionally, the first switch tube and the second switch tube are MOS tubes or triodes.

[0035] Exemplarily, the MOS transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), and the first switch transistor and the second switch transistor are, for example, MOS transistors. Specifically, the first switch transistor and the second switch transistor are, for example, N-channel MOS transistors. Alternatively, the first switch transistor and the second switch transistor are, for example, triodes.

[0036] In this embodiment, the input terminals of the CPLD 101 are connected to the first power supply and the second power supply, respectively. When the CPLD 101 detects that the first input power supply status signal (Vin_Good signal) of the first power supply is high or the second input power supply status signal of the second power supply is high, the CPLD 101 outputs a high signal. When the CPLD 101 detects that the first input power supply status signal of the first power supply is low and the second input power supply status signal of the second power supply is low, the CPLD 101 outputs a low signal, thereby driving the first switch 102 and the second switch 103 to control the fan state. The Vin_Good signal has the following characteristics: if the power input is within the specification range, the Vin_Good signal is high; if the power input is temporarily powered off or there is no input, the Vin_Good signal is low; after the power input returns to normal, the Vin_Good signal returns to a high signal.

[0037] Specifically, in one example, when CPLD 101 detects that the first input power supply status signal of the first power supply is at a low level and the second input power supply status signal of the second power supply changes from a high level to a low level, it controls the first switch tube 102 to be non-conductive and controls the second switch tube 103 to be conductive, so that the level signal of the fan enable terminal is at a low level, such as 0 volts (V). The fan power supply is disconnected from the fan, that is, the fan stops, and the server can be powered off by the second power supply to ensure that the power output is within the specification range. This example corresponds to a situation where the first power supply fails and the second power supply is triggered to power off due to a power grid interruption.

[0038] In another example, when CPLD 101 detects that both the first input power status signal of the first power supply and the second input power status signal of the second power supply are low, it controls first switch 102 to be non-conductive and controls second switch 103 to be conductive, so that the level signal at the fan enable terminal is low, disconnecting the fan power supply from the fan, i.e., the fan stops. The server can be powered down by either the first power supply or the second power supply to ensure that the power output is within the specification range. This example corresponds to a situation where a power grid interruption simultaneously triggers the power down of the first and second power supplies.

[0039] Based on the above embodiment, since the CPLD 101 stops the fan by controlling the first switch tube 102 and the second switch tube 103 when detecting that the first power supply and the second power supply meet the preset trigger conditions, the utilization rate of the power supply can be effectively improved, thereby effectively extending the power output maintenance time.

[0040] Optionally, the duration during which the fan power supply is disconnected from the fan is greater than a first duration threshold and less than a second duration threshold, and the first duration threshold is less than the second duration threshold.

[0041] Exemplarily, if the first duration threshold is, for example, 12 ms and the second duration threshold is, for example, 1 minute (min), then the duration during which the fan power supply is disconnected from the fan (i.e., the fan off duration, denoted as Toff for example) can be controlled within 12 ms < Toff < 1 min. Specifically, the duration during which the fan power supply is disconnected from the fan is, for example, 100 ms, and the maximum fan off duration depends on the server heat dissipation situation. After the fan off duration, the fan resumes normal operation. By the above method, the server power consumption can be reduced. With less power consumption, the power output holding time can be extended.

[0042] The control circuit for the server power output provided by the embodiment of the present application includes a CPLD, a first switching tube, and a second switching tube; when the CPLD detects that the first power supply and the second power supply connected to the input end of the CPLD meet the preset trigger conditions, the CPLD controls the first switching tube not to conduct and controls the second switching tube to conduct, so that the level signal at the enable end of the fan is at a low level, and the fan power supply is disconnected from the fan, that is, the fan stops rotating, and the server is powered off and maintained by the first power supply or the second power supply; wherein, the preset trigger conditions include that the first input power supply state signal of the first power supply is at a low level and the second input power supply state signal of the second power supply changes from a high level to a low level, or, both the first input power supply state signal and the second input power supply state signal are at a low level. By shutting off the fan power supply for a short time in the embodiment of the present application, the server load can be reduced, the power output holding time can be extended, and the server heat dissipation is not affected at the same time; without risk to the application, the power utilization rate can be effectively improved, and the usage requirements of high-density power supplies can be better met.

[0043] Based on the above embodiment, optionally, the CPLD 101 can also be used to: when detecting that both the first power supply and the second power supply do not meet the preset trigger conditions, control the first switching tube 102 to conduct and control the second switching tube 103 not to conduct, so that the level signal at the enable end is at a high level, and the fan power supply is connected to the fan.

[0044] Exemplarily, when the CPLD 101 detects that both the first power supply and the second power supply are supplying power normally, or any one of the first power supply and the second power supply is supplying power normally, that is, both the first power supply and the second power supply do not meet the preset trigger conditions, the CPLD 101 controls the first switching tube 102 to conduct and controls the second switching tube 103 not to conduct, so that the level signal at the enable end of the fan is at a high level, and the fan power supply is connected to the fan, that is, controls the fan to work normally.

[0045] Based on the above embodiment, optionally, the CPLD 101 can also be used to: when detecting that the first input power supply state signal and / or the second input power supply state signal is at a high level, the level signal output by the CPLD 101 is at a high level.

[0046] For example, when CPLD 101 detects that the first input power supply status signal of the first power supply is at a high level or the second input power supply status signal of the second power supply is at a high level, the level signal output by CPLD 101 is at a high level, so as to control the normal operation of the fan through the first switch tube 102 and the second switch tube 103.

[0047] Based on the above embodiment, optionally, when the first power supply is working normally, the first input power supply status signal is at a high level; when the second power supply is working normally, the second input power supply status signal is at a high level.

[0048] It is understood that when the first power supply is working normally, the first input power supply state signal of the first power supply is high level to control the fan to work normally. When the second power supply is working normally, the second input power supply state signal of the second power supply is high level to control the fan to work normally.

[0049] Optionally, the high level is 3.3V and the low level is 0V.

[0050] For example, taking the first power supply as an example, if the first input power supply status signal of the first power supply is 3.3V, the level signal output by CPLD 101 is 3.3V, which is used to control the normal operation of the fan. If the first input power supply status signal of the first power supply is 0V, the level signal output by CPLD 101 is 0V, which is used to stop the fan.

[0051] Figure 2 This is a schematic diagram of a control circuit for a server power output provided by another embodiment of the present application. Based on the above embodiment, this embodiment of the present application further describes the control circuit 100 for a server power output. Figure 2As shown, in the control circuit 100 of the server power output of the embodiment of the present application, the power supply unit (PSU) 1 is used to represent the first power supply, and the PSU2 is used to represent the second power supply; the first input power status signal of PSU1 (for example, represented by the Vin_Good1 signal) and the second input power status signal of PSU2 (for example, represented by the Vin_Good2 signal) are respectively reserved with input / output (I / O) positions on the CPLD 101 side, and the Vin_Good1 signal of PSU1 and the Vin_Good2 signal of PSU2 can be configured as input ports connected to the CPLD 101 end; accordingly, the logic that the CPLD 101 needs to implement is: when it is detected that the Vin_Good1 signal or the Vin_Good2 signal is at a high level (that is, the Vin_Good signal of one of the PSUs is at a high level), the level signal output by the CPLD 101 is at a high level; when it is detected that the Vin_Good1 signal and the Vin_Good2 signal are both at a low level, the level signal output by the CPLD 101 is at a low level. FAN_VIN represents the fan power supply, and FAN_EN represents the fan enable terminal. The first switch transistor 102 (Q1) and the second switch transistor 103 (Q2) are, for example, MOS transistors. The output terminal of the CPLD 101 is connected to the gate (Gate, G) of the first switch transistor 102. The drain (Drain, D) of the first switch transistor 102 is connected to the gate of the second switch transistor 103 and is connected to the fan power supply via a first resistor (R1). The source (Source, S) of the first switch transistor 102 is grounded. The drain of the second switch transistor 103 is connected to the fan enable terminal via a second resistor (R2), and the source of the second switch transistor 103 is grounded.

[0052] refer to Figure 2 Optionally, the CPLD 101 is specifically used to: when it is detected that the first power supply and the second power supply meet the preset trigger condition, output a low level to the gate of the first switch tube 102, control the first switch tube 102 to be non-conductive, and control the second switch tube 103 to be conductive, so that the level signal of the enable end of the fan is low.

[0053] For example, the high level is 3.3V, and the low level is 0V. When the CPLD 101 detects that the first power supply and the second power supply meet a preset trigger condition, that is, the first input power supply status signal of the first power supply is 0V and the second input power supply status signal of the second power supply changes from 3.3V to 0V, or the first input power supply status signal and the second input power supply status signal are both 0V, the level signal output by the CPLD 101 is 0V, that is, the voltage output by the CPLD 101 to the gate of the first switch tube 102 is 0V, thereby controlling the first switch tube 102 to be non-conductive and controlling the second switch tube 103 to be conductive, so that the level signal of the fan enable terminal FAN_EN is 0V, the fan power supply is disconnected from the fan, and the fan stops.

[0054] Optionally, CPLD 101 is specifically used for: when CPLD detects that both the first power supply and the second power supply do not meet the preset trigger conditions, outputting a high level to the gate of the first switch tube 102, controlling the first switch tube 102 to be turned on, and controlling the second switch tube 103 to be turned off, so that the level signal of the enable end of the fan is a high level.

[0055] For example, the high level is 3.3 V. When the CPLD 101 detects that both the first power supply and the second power supply do not meet the preset trigger condition, that is, both the first power supply and the second power supply are operating normally, or either of the first power supply and the second power supply is operating normally, the CPLD 101 outputs a level signal of 3.3 V, that is, the CPLD 101 outputs 3.3 V to the gate of the first switch tube 102, controls the first switch tube 102 to be turned on, and controls the second switch tube 103 to be turned off, so that the level signal of the fan enable terminal FAN_EN is 3.3 V, the fan power supply is connected to the fan, and the fan operates normally.

[0056] Based on the above embodiments, Table 1 shows comparative data between existing solutions and the server power output control circuit solutions provided by the embodiments of this application. As shown in Table 1, U1 represents the initial voltage value of the capacitor; U2 represents the voltage value at the end of capacitor discharge; C represents the capacitance of the capacitor in microfarads (uF); P represents power; t represents the power output hold time in seconds (s); and the capacitor discharge formula is: 0.5*C(U1*U1-U2*U2)*0.000001=Pt. Taking the server operating power of 2880 watts (W) as an example, the fan power / server power accounts for 20%. Based on the technical solution provided in the embodiment of the present application, before the first power supply and the second power supply of the server are powered off (i.e., before the abnormality occurs), the server runs at a power of 2880W, and the time to detect the power input power failure and trigger the fan shutdown is 2.5ms; after the fan is turned off, the remaining power is 2304W, and the power supply can work for 9.7ms. The total time of the two is 12.2ms, that is, the power output holding time is increased from 10.3ms of the existing technical solution to 12.2ms, which effectively extends the power output holding time, can ensure that the server can switch smoothly and without failure under extreme conditions, and improve the utilization rate of the power supply.

[0057] Table 1

[0058]

[0059]

[0060] Based on the above embodiment, Table 2 shows the comparative data of the power that can be supported by the 3200W power supply specification before improvement (corresponding to the existing solution) and after improvement (corresponding to the solution of the control circuit of the server power output provided in the embodiment of the present application). As shown in Table 2, the percentage in Table 2 (for example, 90%) represents the utilization rate of the power supply. For the case where the power output retention time is required to be 12ms, the power supply of the existing solution can support the server to safely operate with a power of 2400W, and the power output retention time is 12.3ms; and according to the solution of the control circuit of the server power output provided in the embodiment of the present application, the power supply can support the server to safely operate with a power of 2880W, and the power output retention time is 12.2ms, which effectively improves the utilization rate of the power supply.

[0061] Table 2

[0062]

[0063]

[0064] Based on the above embodiments, it can be understood that the control circuit of the server power output provided in the embodiments of the present application can effectively extend the power output maintenance time, and improve the power utilization while ensuring risk-free application. For example, the power utilization can be increased from 70% to 80%~90%, where the amount of improvement depends on the proportion of fan power to power supply power (usually 15%-25%).

[0065] It is understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. In the embodiments of the present application, the order of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit for server power output, characterized in that: include: A complex programmable logic device (CPLD), a first switch tube and a second switch tube; The output end of the CPLD is connected to the first switch tube, the first switch tube is connected to the second switch tube and connected to a fan power supply of the server, and the second switch tube is connected to an enable end of the fan of the server; The CPLD is configured to, upon detecting that a first power supply and a second power supply connected to an input terminal of the CPLD meet a preset trigger condition, control the first switch tube to be non-conductive and control the second switch tube to be conductive, so that the level signal of the enable terminal is low, the fan power supply is disconnected from the fan, and the server is powered off and maintained via the first power supply or the second power supply. The preset trigger condition includes that a first input power supply status signal of the first power supply is low and a second input power supply status signal of the second power supply changes from high to low, or that both the first input power supply status signal and the second input power supply status signal are low.

2. The control circuit according to claim 1, wherein: The output end of the CPLD is connected to the gate of the first switching tube, the drain of the first switching tube is connected to the gate of the second switching tube and is connected to the fan power supply via a first resistor, and the source of the first switching tube is grounded; the drain of the second switching tube is connected to the enable end via a second resistor, and the source of the second switching tube is grounded.

3. The control circuit according to claim 2, characterized in that: The CPLD is specifically used for: When it is detected that the first power supply and the second power supply meet the preset trigger condition, a low level is output to the gate of the first switch tube to control the first switch tube to be non-conductive and the second switch tube to be conductive, so that the level signal of the enable end is a low level.

4. The control circuit according to claim 2, characterized in that: The CPLD is also used for: When it is detected that both the first power supply and the second power supply do not meet the preset trigger condition, the first switch tube is controlled to be turned on and the second switch tube is controlled to be turned off, so that the level signal of the enable end is high and the fan power supply is connected to the fan.

5. The control circuit according to claim 4, characterized in that: The CPLD is specifically used for: When the CPLD detects that neither the first power supply nor the second power supply satisfies the preset trigger condition, it outputs a high level to the gate of the first switch tube to control the first switch tube to be turned on and controls the second switch tube to be turned off, so that the level signal of the enable end is a high level.

6. The control circuit according to any one of claims 1 to 5, characterized in that: The CPLD is also used for: When it is detected that the first input power state signal and / or the second input power state signal is at a high level, the level signal output by the CPLD is at a high level.

7. The control circuit according to any one of claims 1 to 5, characterized in that: When the first power supply is working normally, the first input power supply status signal is at a high level; when the second power supply is working normally, the second input power supply status signal is at a high level.

8. The control circuit according to any one of claims 1 to 5, characterized in that: The first switching tube and the second switching tube are MOS tubes or triodes.

9. The control circuit according to any one of claims 1 to 5, characterized in that: The high level is 3.3V, and the low level is 0V.

10. The control circuit according to any one of claims 1 to 5, characterized in that: The duration of disconnection between the fan power supply and the fan is greater than a first duration threshold and less than a second duration threshold, and the first duration threshold is less than the second duration threshold.

Images