Multi-channel signal acquisition circuit

Abstract

The utility model discloses a multi-channel signal acquisition circuit, relates to the technical field of signal acquisition, and solves the problems of high design complexity and design cost of the existing multi-channel data acquisition system. A multi-channel signal acquisition circuit comprises a synchronous control circuit, a plurality of AD signal acquisition channels, a signal conditioning circuit and a memory. Wherein the output end of each AD acquisition channel is uniquely and correspondingly connected with the signal input end of one signal conditioning circuit, and the output end of each signal conditioning circuit is uniquely and correspondingly connected with the input end of one memory; and each synchronous output end of the synchronous control circuit is uniquely and correspondingly connected with the synchronous control end of one AD acquisition channel so as to provide a synchronous signal for the connected AD acquisition channel.

Description

Technical Field

[0001] The utility model relates to the technical field of signal acquisition, in particular to a multi-channel signal acquisition circuit. Background Art

[0002] At present, multi-channel data acquisition systems are widely used in the fields of signal acquisition, testing and fault detection. They can realize high-speed acquisition of various data, providing a guarantee for timely acquisition of data and subsequent data processing.

[0003] However, the design and implementation of multi-channel data acquisition systems is relatively complex, requiring consideration of signal synchronization and channel configuration. Furthermore, the hardware and software costs of multi-channel data acquisition systems are relatively high, especially for high-precision analog-to-digital converters and digital signal processors. This limits their use in some cost-sensitive applications.

[0004] Therefore, how to reduce the design complexity and design cost of multi-channel data acquisition systems is a technical problem that needs to be solved urgently. Utility Model Content

[0005] In view of the above analysis, the present invention aims to provide a multi-channel signal acquisition circuit to solve the problems of high design complexity and high design cost of existing multi-channel data acquisition systems.

[0006] The purpose of this utility model is mainly achieved through the following technical solutions:

[0007] The utility model provides a multi-channel signal acquisition circuit, which includes: a synchronous control circuit, N-channel AD signal acquisition channels, a signal conditioning circuit and a memory; wherein,

[0008] The output end of each AD acquisition channel is uniquely connected to the signal input end of a signal conditioning circuit, and the output end of each signal conditioning circuit is uniquely connected to the input end of a memory;

[0009] Each synchronization output terminal of the synchronization control circuit is uniquely connected to the synchronization control terminal of an AD acquisition channel, so as to provide a synchronization signal for the connected AD acquisition channel.

[0010] On the basis of the above solution, the present invention also makes the following improvements:

[0011] Furthermore, the multi-channel signal acquisition circuit further includes an FPGA chip; wherein,

[0012] The FPGA chip is connected to the enable control terminal of each AD sampling channel to control the activation or deactivation of the corresponding AD acquisition channel.

[0013] Furthermore, the FPGA chip is also connected to the enable control terminal of the synchronization control circuit to respectively control the activation or deactivation of each synchronization signal output by the synchronization control circuit.

[0014] Furthermore, the AD acquisition channel has a built-in analog-to-digital converter;

[0015] The analog-to-digital converter is used to convert the collected analog signal into a digital signal to obtain a corresponding digital signal.

[0016] Furthermore, the signal conditioning circuit has a built-in filter and a gain amplifier; wherein,

[0017] The digital signal is digitally filtered by the filter to obtain a digitally filtered signal;

[0018] The gain amplifier performs gain amplification on the digitally filtered signal to obtain a conditioned signal.

[0019] Furthermore, the filter is designed as a second-order active Butterworth low-pass filter using a programmable amplifier;

[0020] The gain amplifier uses a high-performance operational amplifier.

[0021] Furthermore, it is used to store the conditioned signal and simultaneously store the corresponding synchronization signal.

[0022] Furthermore, the memory is implemented using Flash memory.

[0023] Furthermore, the synchronous control circuit and the N-channel AD signal acquisition channels are connected via a CAN bus communication.

[0024] Furthermore, the N-channel AD signal acquisition channels, the signal conditioning circuit and the memory are connected by PCI bus communication.

[0025] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0026] The multi-channel signal acquisition circuit provided by the utility model can realize the simultaneous acquisition, conditioning, storage and synchronous control of multiple signals through the mutual cooperation between various components, meet the needs of high-precision and high-stability data acquisition, and effectively solve the problems of high design complexity and high design cost of existing multi-channel data acquisition systems.

[0027] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following content, and some advantages will become apparent from the description or be understood through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the text and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference symbols denote the same components.

[0029] Figure 1 A circuit connection diagram of the multi-channel signal acquisition circuit provided by the present invention;

[0030] Figure 2 This is a circuit connection diagram of another multi-channel signal acquisition circuit provided by the utility model. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0032] A specific embodiment of the present invention discloses a multi-channel signal acquisition circuit, the circuit connection diagram is as follows: Figure 1 As shown, the multi-channel signal acquisition circuit includes: an FPGA chip, a synchronization control circuit, multiple AD signal acquisition channels, a signal conditioning circuit and a memory; wherein, the output end of each AD acquisition channel is uniquely connected to the signal input end of a signal conditioning circuit, and the output end of each signal conditioning circuit is uniquely connected to the input end of a memory; each synchronization output end of the synchronization control circuit is uniquely connected to the synchronization control end of an AD acquisition channel, so as to provide a synchronization signal for the connected AD acquisition channel to ensure the synchronization of multi-channel data acquisition.

[0033] Preferably, the multi-channel signal acquisition circuit may further include an FPGA chip. In this case, the circuit connection diagram is as follows: Figure 2 At this point, the FPGA chip is connected to the enable control terminal of each AD sampling channel to control whether the corresponding AD acquisition channel is enabled or disabled. The FPGA chip is also connected to the enable control terminal of the synchronization control circuit to control whether the synchronization signals output by the synchronization control circuit are enabled or disabled, thus achieving precise control of the entire acquisition system.

[0034] Specifically, in this embodiment, the AD acquisition channel has a built-in analog-to-digital converter for converting the collected analog signal into a corresponding digital signal. For example, the analog-to-digital converter, such as the ADS1278, achieves a system sampling frequency of up to 20kHz and communicates with the FPGA via the SPI protocol or the CAN bus.

[0035] In this embodiment, the output end of each ADC acquisition channel uniquely corresponds to the signal input end of a signal conditioning circuit, ensuring that the signal has been properly conditioned before entering the ADC. The main function of the signal conditioning circuit is to perform signal conditioning operations such as filtering and amplification on the collected analog signal to convert it into a signal suitable for the input voltage range of the ADC chip. This includes amplifying weak signals and performing necessary filtering on the signal to eliminate noise and interference. Preferably, the signal conditioning circuit has a built-in filter and a gain amplifier, and the filter digitally filters the digital signal, and the gain amplifier performs gain amplification on the digitally filtered signal to obtain a conditioned signal. Preferably, the filter uses a programmable amplifier to design a second-order active Butterworth low-pass filter; the gain amplifier uses a high-performance operational amplifier.

[0036] The output of each signal conditioning circuit is uniquely connected to the input of a memory device, for temporarily or directly storing the collected digital signal for subsequent processing or analysis. Preferably, the memory device is used to store the conditioned signal and the corresponding synchronization signal. Preferably, the memory device can be implemented as a Flash memory.

[0037] Preferably, in order to improve the communication efficiency of data acquisition, a CAN bus communication connection can be adopted between the synchronization control circuit and the N-channel AD signal acquisition channels; a PCI bus communication connection is adopted between the N-channel AD signal acquisition channels, the signal conditioning circuit and the memory.

[0038] In summary, the multi-channel signal acquisition circuit can realize the simultaneous acquisition, conditioning, storage and synchronous control of multiple signals through the mutual cooperation between various components, meet the needs of high-precision and high-stability data acquisition, and effectively solve the problems of high design complexity and high design cost of existing multi-channel data acquisition systems.

[0039] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the protection scope of the present invention.

Claims

1. A multi-channel signal acquisition circuit, characterized in that: The multi-channel signal acquisition circuit includes: a synchronization control circuit, N-channel AD signal acquisition channels, a signal conditioning circuit and a memory; wherein, The output end of each AD acquisition channel is uniquely connected to the signal input end of a signal conditioning circuit, and the output end of each signal conditioning circuit is uniquely connected to the input end of a memory; Each synchronization output terminal of the synchronization control circuit is uniquely connected to the synchronization control terminal of an AD acquisition channel, so as to provide a synchronization signal for the connected AD acquisition channel.

2. The multi-channel signal acquisition circuit according to claim 1, characterized in that: The multi-channel signal acquisition circuit also includes an FPGA chip; wherein, The FPGA chip is connected to the enable control terminal of each AD sampling channel to control the activation or deactivation of the corresponding AD acquisition channel.

3. The multi-channel signal acquisition circuit according to claim 2, characterized in that: The FPGA chip is also connected to the enable control terminal of the synchronization control circuit to respectively control the activation or deactivation of each synchronization signal output by the synchronization control circuit.

4. The multi-channel signal acquisition circuit according to any one of claims 1 to 3, characterized in that: AD acquisition channel has built-in analog-to-digital converter; The analog-to-digital converter is used to convert the collected analog signal into a digital signal to obtain a corresponding digital signal.

5. The multi-channel signal acquisition circuit according to claim 4, characterized in that: The signal conditioning circuit has built-in filters and gain amplifiers; among them, The digital signal is digitally filtered by the filter to obtain a digitally filtered signal; The gain amplifier performs gain amplification on the digitally filtered signal to obtain a conditioned signal.

6. The multi-channel signal acquisition circuit according to claim 5, characterized in that: The filter uses a programmable amplifier to design a second-order active Butterworth low-pass filter; The gain amplifier uses a high-performance operational amplifier.

7. The multi-channel signal acquisition circuit according to claim 6, characterized in that: The memory is used to store the conditioned signal and the corresponding synchronization signal at the same time.

8. The multi-channel signal acquisition circuit according to claim 7, characterized in that: Memory: The memory is implemented using Flash memory.

9. The multi-channel signal acquisition circuit according to claim 8, characterized in that: The synchronous control circuit and the N-channel AD signal acquisition channels are connected via CAN bus communication.

10. The multi-channel signal acquisition circuit according to claim 9, characterized in that: The N-channel AD signal acquisition channels, signal conditioning circuits and memories are connected by PCI bus communication.

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