Chip crack detection circuit, chip crack detection device and chip

Abstract

The utility model relates to a chip crack detection circuit, a chip crack detection device and a chip, and the chip crack detection circuit comprises a crack detection loop network which is arranged in a detected chip, the detected chip comprises a bare chip, an intermediate layer and a substrate layer which are stacked together, the crack detection loop network is arranged on at least one of the bare chip, the interposer and the substrate layer; the detection interface group is coupled to the crack detection loop network. According to the invention, a multi-azimuth and multi-level crack detection path is introduced, the crack position in the detected chip can be rapidly and accurately positioned, the detection speed of the chip crack can be improved, and the detection cost can be reduced. According to the invention, one or more detection loops or one or more detection sub-loops can be adopted appropriately according to resource conditions such as the size of the detected chip, and flexible arrangement is carried out according to different packaging structures, so that crack detection of chips with various packaging structures is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a chip crack detection circuit, a chip crack detection device, and a chip. Background Art

[0002] With the development of integrated circuit technology, the size of transistors is gradually approaching the physical limit, making it difficult to continue to miniaturize chips. Moreover, due to the limitations of physical laws, the speed of chip performance improvement is gradually decreasing, and the applicability of Moore's Law in modern integrated circuit technology is gradually weakening.

[0003] To overcome bottlenecks in integrated circuit technology development, researchers are diligently searching for breakthrough technologies from various perspectives, with chip stacking being a key area of ​​focus. However, due to the increasing number of stacked functional layers, limited functional layer sizes, and the limitations of stacked packaging technology, cracks within the chip stack structure are becoming increasingly difficult to detect.

[0004] Therefore, how to quickly detect and identify chip cracks without destroying the chip structure has become an urgent problem to be solved. Utility Model Content

[0005] In view of this, the present disclosure provides a chip crack detection circuit, a chip crack detection device and a chip, which can realize rapid detection and identification of chip cracks without destroying the chip structure for chips using chip stacking technology.

[0006] The technical solution of the present disclosure is achieved as follows:

[0007] According to one aspect of an embodiment of the present disclosure, a chip crack detection circuit is provided, comprising:

[0008] a crack detection circuit network, the crack detection circuit network being arranged in a chip to be inspected, wherein the chip to be inspected includes a bare die, an interposer, and a substrate layer stacked together, and the crack detection circuit network is arranged in at least one of the bare die, the interposer, and the substrate layer;

[0009] A detection interface group is coupled to the crack detection loop network.

[0010] In one possible implementation, the crack detection circuit network includes at least one of a chip detection circuit, an interposer detection circuit, and a substrate detection circuit.

[0011] In one possible implementation, the detection interface group includes solder balls in a ball grid array of the chip being detected and / or a GPIO interface of the chip being detected, the ball grid array is provided on the substrate layer, and the GPIO interface is provided in the bare chip;

[0012] The chip detection circuit includes at least one of a first chip detection sub-circuit and a second chip detection sub-circuit, wherein the first chip detection sub-circuit is coupled to the ball grid array, and the second chip detection sub-circuit is coupled to the GPIO interface;

[0013] The interposer detection loop includes at least one of a first interposer detection sub-loop and a second interposer detection sub-loop, wherein the first interposer detection sub-loop is coupled to the ball grid array, and the second interposer detection sub-loop is coupled to the GPIO interface;

[0014] The substrate detection circuit includes at least one of a first substrate detection sub-circuit and a second substrate detection sub-circuit, wherein the first substrate detection sub-circuit is coupled to the ball grid array, and the second substrate detection sub-circuit is coupled to the GPIO interface.

[0015] In one possible implementation, one end of the first chip detection sub-loop is coupled to a first solder ball in the ball grid array, and extends from the first solder ball through the substrate layer and the interposer to the bare die, and then extends from the bare die through the interposer to the substrate layer again, and the other end of the first chip detection sub-loop is coupled to a second solder ball in the ball grid array;

[0016] The portion of the first chip detection sub-loop located in the die includes a first chip crack detection line, and the first chip crack detection line extends along at least one edge region of the die.

[0017] In one possible implementation, one end of the first interposer detection sub-loop is coupled to a third solder ball in the ball grid array, and extends from the third solder ball through the substrate layer into the interposer, and then extends from the interposer back to the substrate layer. The other end of the first interposer detection sub-loop is coupled to a fourth solder ball in the ball grid array.

[0018] The portion of the first interposer detection sub-loop located in the interposer includes a first interposer crack detection line, and the first interposer crack detection line extends along at least one edge region of the interposer.

[0019] In one possible implementation, the first substrate detection sub-circuit extends in the substrate layer, and one end of the first substrate detection sub-circuit is coupled to a fifth solder ball in the ball grid array, and the other end of the first substrate detection sub-circuit is coupled to a sixth solder ball in the ball grid array;

[0020] The first substrate detection sub-loop includes a first substrate crack detection line, and the first substrate crack detection line extends along at least one edge region of the substrate layer.

[0021] In one possible implementation, one end of the second chip detection sub-loop is coupled to a first GPIO sub-interface of the GPIO interface, and extends from the first GPIO sub-interface through the bare die to the interposer, and then extends from the interposer back to the bare die, and the other end of the second chip detection sub-loop is coupled to a second GPIO sub-interface of the GPIO interface.

[0022] The portion of the second chip detection sub-loop located in the die includes a second chip crack detection line, and the second chip crack detection line extends along at least one edge region of the die.

[0023] In one possible implementation, one end of the second interposer detection sub-loop is coupled to a third GPIO sub-interface of the GPIO interface, and extends from the third GPIO sub-interface through the bare die and the interposer to the substrate layer, and then extends from the substrate layer through the interposer to the bare die, and the other end of the second interposer detection sub-loop is coupled to a fourth GPIO sub-interface of the GPIO interface.

[0024] The portion of the second interlayer detection sub-loop located in the interlayer includes a second interlayer crack detection line, and the second interlayer crack detection line extends along at least one edge region of the interlayer.

[0025] In one possible implementation, one end of the second substrate detection sub-loop is coupled to a fifth GPIO sub-interface in the GPIO interface, and extends from the fifth GPIO sub-interface through the bare die, the interposer, and the substrate layer to a seventh solder ball disposed on the substrate layer, then extends from the seventh solder ball to an eighth solder ball disposed on the substrate layer via an inter-solder ball connection line, and then extends from the eighth solder ball again through the substrate layer and the interposer to the bare die. The other end of the second substrate detection sub-loop is coupled to a sixth GPIO sub-interface in the GPIO interface.

[0026] The portion of the second substrate detection sub-circuit located in the substrate layer includes a second substrate crack detection line, and the second substrate crack detection line extends along at least one edge region of the substrate layer.

[0027] According to another aspect of an embodiment of the present disclosure, a chip crack detection device is provided, comprising:

[0028] The chip crack detection circuit as described in any one of the above items;

[0029] A signal transceiver detection device is coupled to the detection interface group.

[0030] According to another aspect of an embodiment of the present disclosure, a chip is provided, including:

[0031] A bare die, an interposer, and a substrate layer stacked together, and a chip crack detection circuit as described in any one of the above items.

[0032] As can be seen from the above scheme, the chip crack detection circuit, chip crack detection device, and chip disclosed herein introduce multi-directional, multi-level crack detection paths, which can quickly and accurately locate the crack position in the chip being detected, helping to improve the chip crack detection speed and help reduce detection costs. At the same time, using the chip crack detection circuit, chip crack detection device, and chip disclosed herein, one or more detection circuits or one or more detection sub-circuits in the crack detection circuit network can be used as appropriate based on resource conditions such as the size of the chip being tested. For example, according to actual conditions, any combination of the first chip detection sub-circuit, the second chip detection sub-circuit, the first interposer detection sub-circuit, the second interposer detection sub-circuit, the first substrate detection sub-circuit, and the second substrate detection sub-circuit can be selected to implement chip crack detection. At the same time, the chip crack detection circuit, chip crack detection device and chip disclosed in the present invention can also be flexibly set according to different packaging structures. When used in chips with packaging structures such as 3D, it is only necessary to arrange the corresponding detection circuit in the structure where crack detection is required. In addition, the chip crack detection circuit, chip crack detection device and chip disclosed in the present invention can also be flexibly adjusted according to the structural changes of the chip to be detected. It is also applicable to chips without silicon interposers or silicon bridges. It is only necessary to remove the interposer detection circuit for the silicon interposer, thereby realizing crack detection of chips with various packaging structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the stacking structure of the 2.5D packaging structure;

[0034] Figure 2 is a schematic diagram showing a modular structure of a chip crack detection circuit according to an exemplary embodiment;

[0035] Figure 3A is a schematic diagram showing a routing path of a first chip detection sub-loop from a chip cross-sectional perspective according to an exemplary embodiment;

[0036] Figure 3B is a schematic diagram showing the arrangement position of a first chip crack detection line from a top view of the chip according to an exemplary embodiment;

[0037] Figure 4Ais a schematic diagram showing a routing path of a first interposer detection sub-loop from a chip cross-sectional perspective according to an exemplary embodiment;

[0038] Figure 4B is a schematic diagram showing the arrangement position of a crack detection line of a first interposer from a top view of a chip according to an exemplary embodiment;

[0039] Figure 5A is a schematic diagram showing a routing path of a first substrate detection sub-circuit from a chip cross-sectional perspective according to an exemplary embodiment;

[0040] Figure 5B is a schematic diagram showing the arrangement position of the first substrate crack detection line from a top view of the chip according to an exemplary embodiment;

[0041] Figure 6A is a schematic diagram showing a routing path of a second chip detection sub-loop from a chip cross-sectional perspective according to an exemplary embodiment;

[0042] Figure 6B 1 is a schematic diagram showing the arrangement position of a second chip crack detection line from a top view of the chip according to an exemplary embodiment;

[0043] Figure 7A is a schematic diagram showing a routing path of a second interposer detection sub-loop from a chip cross-sectional perspective according to an exemplary embodiment;

[0044] Figure 7B 1 is a schematic diagram showing the arrangement position of the second interposer crack detection line from a top view of the chip according to an exemplary embodiment;

[0045] Figure 8A is a schematic diagram showing a routing path of a second substrate detection sub-circuit from a chip cross-sectional perspective according to an exemplary embodiment;

[0046] Figure 8B is a schematic diagram showing the arrangement position of the second substrate crack detection line from a top view of the chip according to an exemplary embodiment;

[0047] Figure 9 is a schematic diagram of a chip crack detection device according to an exemplary embodiment;

[0048] Figure 10 The figure is a flow chart of a chip crack detection method according to an exemplary embodiment. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0051] Chip stacking technology is an integrated circuit manufacturing technology that achieves higher performance, smaller size and lower power consumption by vertically stacking multiple chiplets or chips with different functions.

[0052] 2.5D packaging is a packaging technology that performs high-density I / O interconnection on an interposer. The interposer is usually made of silicon material. Therefore, the interposer made of silicon material can also be called a silicon interposer. Figure 1 This is a schematic diagram of the stacking structure of the 2.5D packaging structure, such as Figure 1 As shown, the structure of the 2.5D package is to stack an interposer 102 and a die 103 in sequence on a substrate layer 101, with different dies 103 arranged in different areas of the interposer 102. The die 103 and the interposer 102 are electrically connected by micro bumps (also called ubumps) 113, and the interposer 102 and the substrate layer 101 are electrically connected by C4 bumps (c4 bumps) 112. An interconnection network for electrical connection between different dies 103 and between the dies 103 and the C4 bumps 112 is also arranged in the interposer 102. A ball grid array (BGA) 111 is provided on the substrate layer 101, and an interconnection network for electrical connection between the C4 bumps 112 and the ball grid array 111 is provided in the substrate layer 101. The C4 bump 112 is a component used for chip-to-chip connection in flip-chip interconnection technology. The chip after 2.5D packaging is electrically connected to the outside world through the ball grid array 111, wherein the bare chip 103 is electrically connected to the outside world of the chip through the micro bumps 113, the electrical interconnection network in the interposer 102, the C4 bumps 112, the electrical interconnection network in the substrate layer 101 and the ball grid array 111.

[0053] from Figure 1It can be seen that in the 2.5D packaging structure, the chip contains a three-layer structure: substrate layer 101, interposer 102, and bare die 103. The number of bare die 103 is set according to the chip design requirements and is at least one. When the number of bare die 103 is two or more, each bare die 103 is arranged in a different area of ​​the interposer 102. In this complex hierarchical structure, cracks may occur in unknown locations of any layer or any unknown location of any bare die 103 during the packaging process or after aging due to long-term use of the chip. Once the crack crosses the wiring in the electrical interconnection network of each layer or crosses the devices in the bare die 103, it may cause chip performance degradation, loss of chip function, or even damage the chip.

[0054] Furthermore, with the advancement of semiconductor technology and artificial intelligence (AI), various HPC (High-Performance Computing) chips, such as high-performance CPUs (Central Processing Units), GPUs (Graphics Processing Units), and GPGPUs (General-Purpose Computing on Graphics Processing Units), are integrating an increasing number of integrated circuits on-chip. This increases the area required, placing stricter manufacturing requirements and driving up chip costs. The larger the chip area, the greater the risk of die cracking. Therefore, rapidly and effectively detecting die cracks is a key technical challenge facing large-scale, complex, and high-performance chips.

[0055] In light of this, the present disclosure provides a chip crack detection circuit, chip crack detection device, and chip, specifically for 2.5D packaged chips. These circuits can quickly and accurately determine whether a chip has cracks and quickly locate the crack site. This helps improve chip crack detection speed and address the problem of rapidly locating cracks in ultra-large, complex chips. Based on the rapid location of the crack site, other chip crack detection methods in related technologies can be used to further analyze the impact of cracks on chip performance.

[0056] Figure 2 FIG. 1 is a schematic diagram showing a modular structure of a chip crack detection circuit according to an exemplary embodiment. Figure 2As shown, the chip crack detection circuit includes a crack detection circuit network 200 and a detection interface group 300. The crack detection circuit network 200 is disposed in the chip under inspection 100. The chip under inspection 100 includes a stacked die 103, an interposer 102, and a substrate layer 101. The crack detection circuit network 200 is disposed in at least one of the die 103, the interposer 102, and the substrate layer 101. The detection interface group 300 is coupled to the crack detection circuit network 200.

[0057] The 2.5D package structure comprises a multi-layer structure consisting of a die 103, an interposer 102, and a substrate layer 101, and there may be multiple die 103s. Therefore, cracks may occur in any of these structures. Furthermore, due to the complex structure, large number of components, high integration, and dense electrical interconnection network of the 2.5D package, and considering chip performance and value, the crack detection circuit network 200 can be deployed in layers or die 103 that are expected to be prone to cracks. Therefore, in the exemplary embodiment, the crack detection circuit network 200 includes at least one of a chip detection circuit, an interposer detection circuit, and a substrate detection circuit. For example, if the wiring space on the die 103 allows, a chip detection circuit can be deployed as needed; if the wiring space on the interposer 102 allows, an interposer detection circuit can be deployed as needed; and if the wiring space on the substrate layer 101 allows, a substrate detection circuit can be deployed as needed.

[0058] In an exemplary embodiment, the detection interface group 300 can be configured based on the actual design of the chip. For example, if the chip size is large enough and the number of solder balls in the ball grid array 111 is sufficient, the solder balls in the ball grid array 111 can be used as the detection interface group 300. If the number of solder balls in the ball grid array 111 is limited, the GPIO (General Purpose Input / Output) interface of the detected chip 100 can be used as the detection interface group 300. Based on this, in an exemplary embodiment, the detection interface group 300 includes the solder balls in the ball grid array of the detected chip 100 and / or the GPIO interface of the detected chip 100, that is, the detection interface group 300 includes at least one of the solder balls in the ball grid array of the detected chip 100 and the GPIO interface of the detected chip 100. The ball grid array is provided on the substrate layer 101, and the GPIO interface is provided on the bare die 103. Among them, the GPIO interface is an interface set inside the chip for communication between the chip and external devices. The GPIO interface is a flexible and programmable interface that can be configured as input or output function according to needs.

[0059] To accommodate different locations of the detection interface group 300 , such as the ball grid array of the substrate layer 101 or the GPIO interface in the die 103 , the chip detection loop, the interposer detection loop, and the substrate detection loop can all adopt different loop routing forms.

[0060] In an illustrative embodiment, the chip detection circuit may include at least one of a first chip detection sub-circuit and a second chip detection sub-circuit, respectively, for the ball grid array of the substrate layer 101 and the GPIO interface within the bare chip 103, wherein the first chip detection sub-circuit is coupled to the ball grid array and the second chip detection sub-circuit is coupled to the GPIO interface.

[0061] In an illustrative embodiment, with respect to the ball grid array of the substrate layer 101 and the GPIO interface within the bare chip 103, respectively, the intermediary layer detection loop may include at least one of a first intermediary layer detection sub-loop and a second intermediary layer detection sub-loop, wherein the first intermediary layer detection sub-loop is coupled to the ball grid array and the second intermediary layer detection sub-loop is coupled to the GPIO interface.

[0062] In an illustrative embodiment, with respect to the ball grid array of the substrate layer 101 and the GPIO interface within the bare chip 103, respectively, the substrate detection circuit may include at least one of a first substrate detection sub-circuit and a second substrate detection sub-circuit, wherein the first substrate detection sub-circuit is coupled to the ball grid array and the second substrate detection sub-circuit is coupled to the GPIO interface.

[0063] Figure 3A is a schematic diagram showing a routing path of a first chip detection sub-loop from a chip cross-sectional perspective according to an exemplary embodiment. Figure 3B FIG. 1 is a schematic diagram showing the location of the first chip crack detection line when viewed from above the chip according to an exemplary embodiment. Figure 3A As shown in the exemplary embodiment, one end of the first chip detection sub-loop 210 is coupled to a first solder ball 311 in the ball grid array, and extends from the first solder ball 311 through the substrate layer 101 and the interposer 102 to the bare die 103, and then extends from the bare die 103 through the interposer 102 to the substrate layer 101. The other end of the first chip detection sub-loop 210 is coupled to a second solder ball 312 in the ball grid array. Figure 3B As shown, the portion of the first chip detection sub-loop 210 located in the die 103 includes a first chip crack detection line 211. The first chip crack detection line 211 extends along at least one edge region of the die 103, for example Figure 3B The upper edge area extends.

[0064] Specifically, regarding the path of the first chip detection sub-loop 210, as shown in FIG. Figure 3AAs shown, the first chip detection sub-loop 210 extends from the substrate layer 101 to the interposer 102 via a C4 bump 112 between the substrate layer 101 and the interposer 102, the first chip detection sub-loop 210 extends from the interposer 102 to the bare die 103 via a micro bump 113 between the interposer 102 and the bare die 103, the first chip detection sub-loop 210 extends from the bare die 103 to the interposer 102 via another micro bump 113 between the interposer 102 and the bare die 103, and the first chip detection sub-loop 210 extends from the interposer 102 to the substrate layer 101 via another C4 bump 112 between the substrate layer 101 and the interposer 102.

[0065] The first solder ball 311 and the second solder ball 312 serve as interfaces for external electrical connection of the first chip detection sub-circuit 210 and are coupled to a related signal transceiver detection device for detecting chip cracks. The signal transceiver detection device sends a signal to the first chip detection sub-circuit 210 via one of the first solder ball 311 and the second solder ball 312 and receives the signal via the other of the first solder ball 311 and the second solder ball 312. By comparing the transmitted and received signals, it can be determined whether there is a crack in the edge region of the bare die 103 where the first chip crack detection line 211 is located. For example, if the signal transceiver detection device sends a signal to the first chip detection sub-circuit 210 via one of the first solder ball 311 and the second solder ball 312 and does not receive a signal from the other of the first solder ball 311 and the second solder ball 312, or if the received signal is abnormal, it can be determined that there is a crack in the edge region of the bare die 103 where the first chip crack detection line 211 is located.

[0066] Need to explain, Figure 3A It is only a schematic display of the routing path, which shows the part of the first chip detection sub-circuit 210 that passes through in the chip, and does not represent the wiring itself. In the actual chip structure, the routing portion of the first chip detection sub-circuit 210 in the bare die 103 extends to the micro bump 113 and is electrically connected to the micro bump 113. The routing portion of the first chip detection sub-circuit 210 in the interposer 102 extends to the micro bump 113 and the C4 bump 112 and is electrically connected to the micro bump 113 and the C4 bump 112. The routing portion of the first chip detection sub-circuit 210 in the substrate layer 101 extends to the C4 bump 112 and the solder balls (the first solder ball 311 and the second solder ball 312) and is electrically connected to the C4 bump 112 and the solder balls (the first solder ball 311 and the second solder ball 312).

[0067] During the chip production process or long-term use and aging process, the edge area of ​​the die 103 is subjected to greater tensile or compressive stress than the center area of ​​the die 103, so cracks are likely to be generated first at the edge of the die 103. Therefore, the first chip crack detection line 211 is set to extend along the edge area of ​​the die 103 to effectively detect whether there is a crack in the die 103. As an example, Figure 3B It is shown that the first chip crack detection line 211 is disposed at one edge region of the die 103, but the first chip crack detection line 211 may also be disposed at other regions. Figure 3B Furthermore, if conditions permit, the first chip crack detection line 211 can also be set in two adjacent edge areas, three edge areas, or even four edge areas on the die 103.

[0068] Figure 4A 1 is a schematic diagram showing a routing path of a first interposer detection sub-loop from a chip cross-sectional view according to an exemplary embodiment. Figure 4B FIG. 1 is a schematic diagram showing the location of the first interposer crack detection line when viewed from above the chip according to an exemplary embodiment. Figure 4A As shown in the exemplary embodiment, one end of the first interposer detection sub-loop 230 is coupled to a third solder ball 313 in the ball grid array, and extends from the third solder ball 313 through the substrate layer 101 to the interposer 102, and then extends from the interposer 102 to the substrate layer 101 again, and the other end of the first interposer detection sub-loop 230 is coupled to a fourth solder ball 314 in the ball grid array. Figure 4B As shown, the portion of the first interposer detection sub-loop 230 located in the interposer 102 includes a first interposer crack detection line 231 , which extends along at least one edge region of the interposer 102 , for example Figure 4B The upper edge area extends.

[0069] Specifically, regarding the path of the first intermediary layer detection sub-loop 230, as shown in FIG. Figure 4A As shown, the first interposer detection sub-loop 230 extends from the substrate layer 101 to the interposer 102 via a C4 bump 112 between the substrate layer 101 and the interposer 102 , and the first interposer detection sub-loop 230 extends from the interposer 102 to the substrate layer 101 via another C4 bump 112 between the substrate layer 101 and the interposer 102 .

[0070] Similar to the first solder balls 311 and the second solder balls 312, the third solder balls 313 and the fourth solder balls 314 serve as interfaces for external electrical connections of the first interposer detection sub-circuit 230 and are coupled to a signal transceiver detection device for detecting chip cracks. The signal transceiver detection device transmits a signal to the first interposer detection sub-circuit 230 via one of the third solder balls 313 and the fourth solder balls 314 and receives the signal via the other of the third solder balls 313 and the fourth solder balls 314. By comparing the transmitted and received signals, it is possible to determine whether a crack exists in the edge region of the interposer 102 where the first interposer detection sub-circuit 230 is located. For example, if the signal transceiver detection device transmits a signal to the first interposer detection sub-circuit 230 via one of the third solder balls 313 and the fourth solder balls 314 and does not receive a signal from the other of the third solder balls 313 and the fourth solder balls 314, or if the received signal is abnormal, it can be determined that a crack exists in the edge region of the interposer 102 where the first interposer detection sub-circuit 230 is located.

[0071] and Figure 3A The schematic representation of the same, Figure 4A The portion of the first interposer detection sub-loop 230 that passes through in the chip does not represent the wiring itself. In the actual chip structure, the routing portion of the first interposer detection sub-loop 230 in the interposer 102 extends to the C4 bump 112 and is electrically connected to the C4 bump 112. The routing portion of the first interposer detection sub-loop 230 in the substrate layer 101 extends to the C4 bump 112 and the solder balls (the third solder ball 313 and the fourth solder ball 314) and is electrically connected to the C4 bump 112 and the solder balls (the third solder ball 313 and the fourth solder ball 314).

[0072] Similar to the bare chip 103, during the chip production process or long-term use and aging process, the edge area of ​​the interposer 102 is subjected to greater tensile or compressive stress than the center area of ​​the interposer 102. Therefore, cracks in the interposer 102 are likely to occur first at the edge of the interposer 102. Therefore, the first interposer crack detection line 231 is set to extend along the edge area of ​​the interposer 102 to effectively detect whether there is a crack in the interposer 102. As an example, Figure 4B It is shown that the first interposer crack detection line 231 is disposed at one edge region of the interposer 102, but the first interposer crack detection line 231 may also be disposed at other regions. Figure 4B Furthermore, if conditions permit, the first interposer crack detection line 231 can also be arranged in two adjacent edge areas, three edge areas, or even four edge areas on the interposer 102 .

[0073] Figure 5AFIG1 is a schematic diagram showing a wiring path of a first substrate detection sub-circuit from a chip cross-sectional view according to an exemplary embodiment. Figure 5B FIG. 1 is a schematic diagram showing the arrangement position of the first substrate crack detection line in a top view of the chip according to an exemplary embodiment. Figure 5A In the exemplary embodiment, the first substrate detection sub-circuit 250 extends in the substrate layer 101, and one end of the first substrate detection sub-circuit 250 is coupled to a fifth solder ball 315 in the ball grid array, and the other end of the first substrate detection sub-circuit 250 is coupled to a sixth solder ball 316 in the ball grid array. Figure 5B As shown, the first substrate detection sub-circuit 250 includes a first substrate crack detection line 251, and the first substrate crack detection line 251 extends along at least one edge region of the substrate layer 101, for example Figure 5B The upper edge area extends.

[0074] Similar to the first solder balls 311 and 312, and the third solder balls 313 and 314, the fifth solder balls 315 and the sixth solder balls 316 serve as external electrical connection interfaces for the first substrate detection sub-circuit 250 and are coupled to a signal transceiver detection device for detecting chip cracks. The signal transceiver detection device transmits a signal to the first substrate detection sub-circuit 250 via one of the fifth solder balls 315 and 316, and receives the signal via the other of the fifth solder balls 315 and 316. By comparing the transmitted and received signals, it is possible to determine whether a crack exists in the edge region of the substrate layer 101 where the first substrate detection sub-circuit 250 is located. For example, if the signal transceiver detection device 400 transmits a signal to the first substrate detection sub-circuit 250 via one of the fifth solder balls 315 and 316, and does not receive a signal from the other of the fifth solder balls 315 and 316, or if the received signal is abnormal, it can be determined that a crack exists in the edge region of the substrate layer 101 where the first substrate detection sub-circuit 250 is located.

[0075] and Figure 3A 、 Figure 4A The schematic representation of the same, Figure 5A The portion of the first substrate detection sub-circuit 250 that passes through in the chip does not represent the wiring itself. In the actual chip structure, the routing portion of the first substrate detection sub-circuit 250 in the substrate layer 101 extends to the solder balls (fifth solder ball 315 and sixth solder ball 316) and is electrically connected to the C4 bump 112 and the solder balls (fifth solder ball 315 and sixth solder ball 316).

[0076] Similar to the bare chip 103 and the interposer 102, during the chip production process or the aging process due to long-term use, the edge area of ​​the substrate layer 101 is subjected to greater tensile or compressive stress than the central area of ​​the substrate layer 101. Therefore, cracks in the substrate layer 101 are likely to be generated first at the edge of the substrate layer 101. Therefore, the first substrate crack detection line 251 is set to extend along the edge area of ​​the substrate layer 101 to effectively detect whether there is a crack in the substrate layer 101. As an example, Figure 5B It is shown that the first substrate crack detection line 251 is disposed in an edge region of the substrate layer 101, but the first substrate crack detection line 251 may also be disposed in other regions. Figure 5B Moreover, if conditions permit, the first substrate crack detection line 251 can also be set in two adjacent edge areas, three edge areas or even four edge areas on the substrate layer 101.

[0077] above Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The illustrated embodiments all implement chip crack detection by coupling solder balls in a ball grid array (BGA) to a signal transceiver detection device for detecting chip cracks. The solder balls involved are all dedicated to chip crack detection. If the chip area is large and the number of solder balls available allows, the above approach can be employed to implement chip crack detection by providing a chip crack detection circuit containing a solder ball structure for chip crack detection. However, if the chip area is small and the number of solder balls available does not allow for the provision of solder balls dedicated to chip crack detection, it is not appropriate to use solder balls as the interface for external connections of the chip crack detection circuit. Therefore, the GPIO interface of the chip 100 being detected can be used as the interface for external connections of the chip crack detection circuit. Accordingly, the routing of the chip crack detection circuit is adjusted accordingly, as described below.

[0078] Figure 6A FIG1 is a schematic diagram showing a routing path of a second chip detection sub-loop from a chip cross-sectional view according to an exemplary embodiment. Figure 6B FIG. 1 is a schematic diagram showing the location of the second chip crack detection line when viewed from above the chip according to an exemplary embodiment. Figure 6AAs shown, in the exemplary embodiment, one end of the second chip detection sub-loop 220 is coupled to a first GPIO sub-interface 321 in the GPIO interface, and extends from the first GPIO sub-interface 321 through the bare die 103 to the interposer 102, and then extends from the interposer 102 back to the bare die 103. The other end of the second chip detection sub-loop 220 is coupled to a second GPIO sub-interface 322 in the GPIO interface. Figure 6B As shown, the portion of the second chip detection sub-circuit 220 located in the die 103 includes a second chip crack detection line 221. The second chip crack detection line 221 extends along at least one edge region of the die 103, for example Figure 6B The lower edge area extends.

[0079] Specifically, regarding the path of the second chip detection sub-loop 220, as Figure 6A As shown, the second chip detection sub-loop 220 extends from the die 103 to the interposer 102 via a micro-bump 113 between the interposer 102 and the die 103 , and the second chip detection sub-loop 220 extends from the interposer 102 back to the die 103 via another micro-bump 113 between the interposer 102 and the die 103 .

[0080] Among them, the first GPIO sub-interface 321 and the second GPIO sub-interface 322 serve as interfaces for external electrical connection of the second chip detection sub-circuit 220. Because GPIO is a programmable pin, the first GPIO sub-interface 321 and the second GPIO sub-interface 322 can be set in the detected chip 100 according to functional design requirements, so that the detected chip 100 can send a signal to the second chip detection sub-circuit 220 through one of the first GPIO sub-interface 321 and the second GPIO sub-interface 322 and receive the signal through the other of the first GPIO sub-interface 321 and the second GPIO sub-interface 322. By comparing the sent signal and the received signal, it can be determined whether there is a crack in the edge area of ​​the bare die 103 where the second chip crack detection line 221 is located. For example, when the detected chip 100 passes through the first GPIO sub-interface 321 and the second GPIO sub-interface 322, it can be determined whether there is a crack in the edge area of ​​the bare die 103 where the second chip crack detection line 221 is located. When one of the O sub-interfaces 322 sends a signal to the second chip detection sub-loop 220 and does not receive a signal from the other of the first GPIO sub-interface 321 and the second GPIO sub-interface 322 or the received signal is abnormal, it can be determined that there is a crack in the edge area of ​​the bare die 103 where the second chip crack detection line 221 is located. On this basis, the detected chip 100 can upload the detection result of whether there is a crack in the edge area of ​​the bare die 103 through the data channel in the detected chip 100 to the relevant crack detection device. For example, the detected chip 100 can store the detection result of whether there is a crack in the edge area of ​​the bare die 103 in the relevant register in the detected chip 100 for retrieval by the crack detection device.

[0081] The second chip detection sub-loop 220 extends from the die 103 to the interposer 102 and then back to the die 103 because this method facilitates the wiring of the die 103 and the interposer 102 .

[0082] and Figure 3A The schematic representation of the same, Figure 6A It is only a schematic display of the routing path, indicating the part through which the second chip detection sub-loop 220 passes in the chip, and does not represent the wiring itself. In the actual chip structure, the routing portion of the second chip detection sub-loop 220 in the bare die 103 extends to the micro-bump 113 and is electrically connected to the micro-bump 113, and the routing portion of the second chip detection sub-loop 220 in the interposer 102 extends to the micro-bump 113 and is electrically connected to the micro-bump 113.

[0083] In this exemplary embodiment, the chip under inspection 100 can employ both the first chip inspection sub-circuit 210 and the second chip inspection sub-circuit 220, or can employ either the first chip inspection sub-circuit 210 or the second chip inspection sub-circuit 220 as needed. When the chip under inspection 100 employs both the first chip inspection sub-circuit 210 and the second chip inspection sub-circuit 220, the first chip crack detection line 211 and the second chip crack detection line 221 can be respectively positioned at different edge regions of the die 103, thereby enabling more comprehensive detection of crack locations within the die 103.

[0084] Figure 7A FIG1 is a schematic diagram showing a routing path of a second interposer detection sub-loop from a chip cross-sectional view according to an exemplary embodiment. Figure 7B FIG. 1 is a schematic diagram showing the location of the second interposer crack detection line when viewed from above the chip according to an exemplary embodiment. Figure 7A As shown, one end of the second interposer detection sub-loop 240 is coupled to a third GPIO sub-interface 323 in the GPIO interface, and extends from the third GPIO sub-interface 323 through the die 103 and the interposer 102 to the substrate layer 101, and then extends from the substrate layer 101 through the interposer 102 to the die 103. The other end of the second interposer detection sub-loop 240 is coupled to a fourth GPIO sub-interface 324 in the GPIO interface. Figure 7B As shown, the portion of the second interposer detection sub-loop 240 located in the interposer 102 includes a second interposer crack detection line 241 , which extends along at least one edge region of the interposer 102 , for example Figure 7B The lower edge area extends.

[0085] Specifically, regarding the path of the second intermediary layer detection sub-loop 240, as Figure 7A As shown, the second interposer detection sub-loop 240 extends from the bare die 103 to the interposer 102 via a micro-bump 113 between the interposer 102 and the bare die 103, the second interposer detection sub-loop 240 extends from the interposer 102 to the substrate layer 101 via a C4 bump 112 between the substrate layer 101 and the interposer 102, the second interposer detection sub-loop 240 extends from the substrate layer 101 to the interposer 102 via another C4 bump 112 between the substrate layer 101 and the interposer 102, and the second interposer detection sub-loop 240 extends from the interposer 102 to the bare die 103 via another micro-bump 113 between the interposer 102 and the bare die 103.

[0086] Among them, the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324 serve as interfaces for external electrical connection of the second intermediary layer detection sub-loop 240, so that the detected chip 100 can send a signal to the second intermediary layer detection sub-loop 240 through one of the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324 and receive the signal through the other of the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324. By comparing the sent signal and the received signal, it can be determined whether there is a crack in the edge area of ​​the intermediary layer 102 where the second intermediary layer crack detection line 241 is located. For example, when the detected chip 100 passes through the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324, When one of the interposer detection sub-loops 240 sends a signal and does not receive a signal from the other of the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324, or the received signal is abnormal, it can be determined that there is a crack in the edge area of ​​the interposer 102 where the second interposer crack detection line 241 is located. On this basis, the chip under test 100 can upload the detection result of whether there is a crack in the edge area of ​​the interposer 102 through the data channel in the chip under test 100 to the relevant crack detection device. For example, the chip under test 100 can store the detection result of whether there is a crack in the edge area of ​​the interposer 102 in the relevant register in the chip under test 100 for retrieval by the crack detection device.

[0087] The second interposer detection sub-loop 240 extends from the interposer 102 to the substrate 101 and then back to the interposer 102 because this method facilitates the wiring of the interposer 102 and the substrate 101 .

[0088] and Figure 6A The schematic representation of the same, Figure 7A It represents the part through which the second interposer detection sub-loop 240 passes in the chip, and does not represent the wiring itself. In the actual chip structure, the routing portion of the second interposer detection sub-loop 240 in the bare die 103 extends to the micro-bump 113 and is electrically connected to the micro-bump 113, the routing portion of the second interposer detection sub-loop 240 in the interposer 102 extends to the micro-bump 113 and the C4 bump 112 and is electrically connected to the micro-bump 113 and the C4 bump 112, and the routing portion of the second interposer detection sub-loop 240 in the substrate layer 101 extends to the C4 bump 112 and is electrically connected to the C4 bump 112.

[0089] In this exemplary embodiment, the chip under inspection 100 may employ both the first interposer detection sub-circuit 230 and the second interposer detection sub-circuit 240, or may employ either the first interposer detection sub-circuit 230 or the second interposer detection sub-circuit 240 as needed. When the chip under inspection 100 employs both the first interposer detection sub-circuit 230 and the second interposer detection sub-circuit 240, the first interposer crack detection line 231 and the second interposer crack detection line 241 may be disposed at different edge regions of the interposer 102, thereby enabling more comprehensive detection of crack locations in the interposer 102.

[0090] Figure 8A FIG1 is a schematic diagram showing a wiring path of a second substrate detection sub-circuit from a chip cross-sectional view according to an exemplary embodiment. Figure 8B FIG. 1 is a schematic diagram showing the arrangement position of the second substrate crack detection line in a top view of the chip according to an exemplary embodiment. Figure 8A As shown, in the exemplary embodiment, one end of the second substrate detection sub-loop 260 is coupled to a fifth GPIO sub-interface 325 in the GPIO interface, and extends from the fifth GPIO sub-interface 325 through the bare die 103, the interposer 102, and the substrate layer 101 to a seventh solder ball 317 disposed on the substrate layer 101, and then extends from the seventh solder ball 317 to an eighth solder ball 318 disposed on the substrate layer 101 through an inter-solder ball connection line, and then extends from the eighth solder ball 318 again through the substrate layer 101 and the interposer 102 to the bare die 103. The other end of the second substrate detection sub-loop 260 is coupled to a sixth GPIO sub-interface 326 in the GPIO interface. Figure 8B As shown, the portion of the second substrate detection sub-circuit 260 located in the substrate layer 101 includes a second substrate crack detection line 261, which extends along at least one edge region of the substrate layer 101, for example Figure 8B The lower edge area extends.

[0091] Specifically, regarding the path of the second substrate detection sub-circuit 260, as Figure 8A As shown, the second substrate detection sub-loop 260 extends from the bare die 103 to the interposer 102 via a micro-bump 113 between the interposer 102 and the bare die 103, the second substrate detection sub-loop 260 extends from the interposer 102 to the substrate layer 101 via a C4 bump 112 between the substrate layer 101 and the interposer 102, the second substrate detection sub-loop 260 extends from the substrate layer 101 to the interposer 102 via another C4 bump 112 between the substrate layer 101 and the interposer 102, and the second substrate detection sub-loop 260 extends from the interposer 102 to the bare die 103 via another micro-bump 113 between the interposer 102 and the bare die 103.

[0092] In an exemplary embodiment, the connection lines between the solder balls can be connected in the form of traces or interconnect lines. If the seventh solder ball 317 and the eighth solder ball 318 are adjacent solder balls, solder ball bridging can be used to connect the seventh solder ball 317 and the eighth solder ball 318. The seventh solder ball 317 and the eighth solder ball 318 are specifically used for substrate crack detection.

[0093] Among them, the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326 serve as interfaces for external electrical connection of the second substrate detection sub-circuit 260, so that the detected chip 100 can send a signal to the second substrate detection sub-circuit 260 through one of the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326 and receive the signal through the other of the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326. By comparing the sent signal and the received signal, it can be determined whether there is a crack in the edge area of ​​the substrate layer 101 where the second substrate crack detection line 261 is located. For example, when the detected chip 100 passes through the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326, When one of the detected chips 100 sends a signal to the second substrate detection sub-circuit 260 and does not receive a signal from the other of the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326, or the received signal is abnormal, it can be determined that there is a crack in the edge area of ​​the substrate layer 101 where the second substrate crack detection line 261 is located. On this basis, the detected chip 100 can upload the detection result of whether there is a crack in the edge area of ​​the substrate layer 101 through the data channel in the detected chip 100 to the relevant crack detection device. For example, the detected chip 100 can store the detection result of whether there is a crack in the edge area of ​​the substrate layer 101 in the relevant register in the detected chip 100 for retrieval by the crack detection device.

[0094] The second substrate detection sub-loop 260 extends from the substrate layer 101 through the seventh solder ball 317 and the eighth solder ball 318 back to the substrate layer 101 because this method facilitates wiring of the substrate layer 101 .

[0095] and Figure 6A The schematic representation of the same, Figure 8AThe portion through which the second substrate detection sub-circuit 260 passes in the chip does not represent the wiring itself. In the actual chip structure, the routing portion of the second substrate detection sub-circuit 260 in the bare die 103 extends to the micro-bump 113 and is electrically connected to the micro-bump 113. The routing portion of the second substrate detection sub-circuit 260 in the interposer 102 extends to the micro-bump 113 and the C4 bump 112 and is electrically connected to the micro-bump 113 and the C4 bump 112. The routing portion of the second substrate detection sub-circuit 260 in the substrate layer 101 extends to the C4 bump 112 and the solder balls (the seventh solder ball 317 and the eighth solder ball 318) and is electrically connected to the C4 bump 112 and the solder balls (the seventh solder ball 317 and the eighth solder ball 318).

[0096] In this exemplary embodiment, the chip under inspection 100 can employ both the first substrate detection sub-circuit 250 and the second substrate detection sub-circuit 260, or can employ only one of the first and second substrate detection sub-circuit 250 and 260 as needed. When the chip under inspection 100 employs both the first and second substrate detection sub-circuit 250 and 260, the first and second substrate crack detection lines 251 and 261 can be positioned at different edge regions of the substrate layer 101, thereby enabling more comprehensive detection of crack locations within the substrate layer 101.

[0097] In an illustrative embodiment, the chip 100 under test can be any one of a CPU, a GPU, a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), a GPGPU and other HPC chips.

[0098] The chip crack detection circuit of the disclosed embodiment introduces multi-directional, multi-level crack detection paths that can quickly and accurately locate cracks, helping to improve chip crack detection speed and reduce detection costs. Furthermore, the chip crack detection circuit of the disclosed embodiment can utilize one or more detection circuits or one or more detection sub-circuits within the crack detection circuit network, depending on resource availability, such as the size of the chip being tested. For example, any combination of the first chip detection sub-circuit, the second chip detection sub-circuit, the first interposer detection sub-circuit, the second interposer detection sub-circuit, the first substrate detection sub-circuit, and the second substrate detection sub-circuit can be selected to achieve chip crack detection. Furthermore, the chip crack detection circuit of the disclosed embodiment can be flexibly configured to accommodate different packaging structures. For chips with 3D packaging structures, the corresponding detection circuits can be deployed in the structure requiring crack detection. Furthermore, the chip crack detection circuit of the disclosed embodiment can be flexibly adjusted based on the structural variations of the chip being tested. It is also applicable to chips without silicon interposers or silicon bridges by simply removing the interposer detection circuit for the silicon interposer, thereby enabling crack detection for chips with various packaging structures.

[0099] The present disclosure also provides a chip crack detection device. Figure 9 FIG. 1 is a schematic diagram of an embodiment of the chip crack detection device. Figure 9As shown, in an exemplary embodiment, the chip crack detection device includes a chip crack detection circuit as described in any of the above embodiments and a signal transceiver detection device 400. The signal transceiver detection device 400 is coupled to the detection interface group 300, and is used to send a reference detection signal to the crack detection loop network 200 through the detection interface group 300 and receive a feedback detection signal. In an exemplary embodiment, the chip crack detection device is also used to determine whether a crack occurs in the chip based on the difference between the feedback detection signal and the reference detection signal, and further obtain the location of the crack based on the specific solder ball or GPIO interface in the detection interface group 300 corresponding to the feedback detection signal and the reference detection signal. Each solder ball and / or GPIO interface in the detection interface group 300 is respectively associated with the edge area where the crack detection line electrically connected to it is located. For example, the first solder ball 311 and the second solder ball 312 are associated with the edge area where the first chip crack detection line 211 in the bare die 103 is located, the third solder ball 313 and the fourth solder ball 314 are associated with the edge area where the first interposer crack detection line 231 in the interposer 102 is located, the fifth solder ball 315 and the sixth solder ball 316 are associated with the edge area where the first substrate crack detection line 251 in the substrate layer 101 is located, the first GPIO sub-interface 321 and the second GPIO sub-interface 322 are associated with the edge area where the second chip crack detection line 221 in the bare die 103 is located, the third GPIO sub-interface 323 and the fourth GPIO sub-interface 324 are associated with the edge area where the second interposer crack detection line 241 in the interposer 102 is located, and the fifth GPIO sub-interface 325 and the sixth GPIO sub-interface 326 are associated with the edge area where the second substrate crack detection line 261 in the substrate layer 101 is located.

[0100] Based on the above chip crack detection and chip crack detection device, the embodiment of the present disclosure further provides a chip crack detection method. Figure 10 FIG. 1 is a flow chart of an embodiment of the chip crack detection method, as shown in FIG. Figure 10 The method shown mainly includes the following steps 1001 to 1003.

[0101] Step 1001: Send a reference detection signal to the crack detection loop network through the detection interface group;

[0102] Step 1002: Receive a feedback detection signal from the detection interface group;

[0103] Step 1003 : Obtain a chip crack detection result based on the difference between the feedback detection signal and the reference detection signal.

[0104] In an exemplary embodiment, the crack detection result of the chip includes whether a crack occurs in the chip and the location of the crack.

[0105] In the embodiment where the crack detection circuit network 200 includes a chip detection circuit, an interposer detection circuit, and a substrate detection circuit, and the chip detection circuit includes a first chip detection sub-circuit 210 and a second chip detection sub-circuit 220, the interposer detection circuit includes a first interposer detection sub-circuit 230 and a second interposer detection sub-circuit 240, and the substrate detection circuit includes a first substrate detection sub-circuit 250 and a second substrate detection sub-circuit 260, step 1001 may specifically include:

[0106] Sending a first chip reference detection sub-signal to the first chip detection sub-loop 210 via the first solder ball 311;

[0107] Sending a second chip reference detection sub-signal to the second chip detection sub-circuit 220 via the first GPIO sub-interface 321;

[0108] Sending the first interposer reference detection sub-signal to the first interposer detection sub-loop 230 via the third solder ball 313 ;

[0109] Sending the second interposer reference detection sub-signal to the second interposer detection sub-loop 240 via the third GPIO sub-interface 323 ;

[0110] Sending a first substrate reference detection sub-signal to the first substrate detection sub-circuit 250 via the fifth solder ball 315 ;

[0111] The second substrate reference detection sub-signal is sent to the second substrate detection sub-circuit 260 through the fifth GPIO sub-interface 325 .

[0112] In the embodiment where the crack detection circuit network 200 includes a chip detection circuit, an interposer detection circuit, and a substrate detection circuit, and the chip detection circuit includes a first chip detection sub-circuit 210 and a second chip detection sub-circuit 220, the interposer detection circuit includes a first interposer detection sub-circuit 230 and a second interposer detection sub-circuit 240, and the substrate detection circuit includes a first substrate detection sub-circuit 250 and a second substrate detection sub-circuit 260, step 1002 may specifically include:

[0113] receiving the first chip feedback detection sub-signal from the second solder ball 312;

[0114] receiving a second chip feedback detection sub-signal from the second GPIO sub-interface 322;

[0115] receiving the first interposer feedback detection sub-signal from the fourth solder ball 314;

[0116] receiving a second interposer feedback detection sub-signal from the fourth GPIO sub-interface 324;

[0117] receiving a first substrate feedback detection sub-signal from the sixth solder ball 316;

[0118] The second substrate feedback detection sub-signal is received from the sixth GPIO sub-interface 326 .

[0119] In the embodiment where the crack detection circuit network 200 includes a chip detection circuit, an interposer detection circuit, and a substrate detection circuit, and the chip detection circuit includes a first chip detection sub-circuit 210 and a second chip detection sub-circuit 220, the interposer detection circuit includes a first interposer detection sub-circuit 230 and a second interposer detection sub-circuit 240, and the substrate detection circuit includes a first substrate detection sub-circuit 250 and a second substrate detection sub-circuit 260, step 1003 may specifically include:

[0120] Determine whether a crack occurs in the edge area of ​​the die 103 where the first chip crack detection line 211 is located according to the difference between the first chip reference detection sub-signal and the first chip feedback detection sub-signal;

[0121] Determine whether a crack occurs in the edge area of ​​the die 103 where the second chip crack detection line 221 is located according to the difference between the second chip reference detection sub-signal and the second chip feedback detection sub-signal;

[0122] determining whether a crack occurs in the edge region of the interposer 102 where the first interposer crack detection line 231 is located according to a difference between the first interposer reference detection sub-signal and the first interposer feedback detection sub-signal;

[0123] determining whether a crack occurs in the edge region of the interposer 102 where the second interposer crack detection line 241 is located according to a difference between the second interposer reference detection sub-signal and the second interposer feedback detection sub-signal;

[0124] Determining whether a crack occurs in the edge region of the substrate layer 101 where the first substrate crack detection line 251 is located according to a difference between the first substrate reference detection sub-signal and the first substrate feedback detection sub-signal;

[0125] Whether a crack occurs in the edge region of the substrate layer 101 where the second substrate crack detection line 261 is located is determined based on the difference between the second substrate reference detection sub-signal and the second substrate feedback detection sub-signal.

[0126] In an exemplary embodiment, in step 1003 , the severity of the crack may also be determined based on the difference between the feedback detection signal and the reference detection signal. Taking the difference between the first chip reference detection sub-signal and the first chip feedback detection sub-signal as an example: if there is no difference or the difference is very small between the first chip reference detection sub-signal and the first chip feedback detection sub-signal, it indicates that no crack has appeared in the edge region of the die 103 where the first chip crack detection line 211 is located; if there is a certain difference between the first chip reference detection sub-signal and the first chip feedback detection sub-signal but the difference is not serious, it indicates that a slight crack may have appeared in the edge region of the die 103 where the first chip crack detection line 211 is located; if there is a large difference between the first chip reference detection sub-signal and the first chip feedback detection sub-signal, it indicates that a large crack may have appeared in the edge region of the die 103 where the first chip crack detection line 211 is located; if the difference between the first chip reference detection sub-signal and the first chip feedback detection sub-signal is such that the change of the first chip feedback detection sub-signal does not respond to the change of the first chip reference detection sub-signal or the first chip feedback detection sub-signal is not received, it indicates that the crack at the edge region of the die 103 where the first chip crack detection line 211 is located is very large and may even cause the first chip crack detection line 211 to be disconnected.

[0127] In an exemplary embodiment, the severity of the crack may be scored accordingly based on the difference characteristics or degree of difference between the feedback detection signal and the reference detection signal to quantify the severity of the crack, thereby achieving auxiliary quantitative evaluation of chip quality.

[0128] An embodiment of the present disclosure further provides a chip, which includes a bare die, an interposer, and a substrate layer stacked together, and the chip crack detection circuit as described in any of the above embodiments.

[0129] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A chip crack detection circuit, characterized in that: include: a crack detection circuit network, the crack detection circuit network being arranged in a chip to be inspected, wherein the chip to be inspected includes a bare die, an interposer, and a substrate layer stacked together, and the crack detection circuit network is arranged in at least one of the bare die, the interposer, and the substrate layer; A detection interface group is coupled to the crack detection loop network.

2. The chip crack detection circuit according to claim 1, wherein: The crack detection circuit network includes at least one of a chip detection circuit, an interposer detection circuit, and a substrate detection circuit.

3. The chip crack detection circuit according to claim 2, wherein: The detection interface group includes solder balls in the ball grid array of the detected chip and / or the GPIO interface of the detected chip, the ball grid array is arranged on the substrate layer, and the GPIO interface is arranged in the bare chip; The chip detection circuit includes at least one of a first chip detection sub-circuit and a second chip detection sub-circuit, wherein the first chip detection sub-circuit is coupled to the ball grid array, and the second chip detection sub-circuit is coupled to the GPIO interface; The interposer detection loop includes at least one of a first interposer detection sub-loop and a second interposer detection sub-loop, wherein the first interposer detection sub-loop is coupled to the ball grid array, and the second interposer detection sub-loop is coupled to the GPIO interface; The substrate detection circuit includes at least one of a first substrate detection sub-circuit and a second substrate detection sub-circuit, wherein the first substrate detection sub-circuit is coupled to the ball grid array, and the second substrate detection sub-circuit is coupled to the GPIO interface.

4. The chip crack detection circuit according to claim 3, wherein: One end of the first chip detection sub-loop is coupled to a first solder ball in the ball grid array, and extends from the first solder ball through the substrate layer and the interposer to the bare die, and then extends from the bare die through the interposer to the substrate layer again, and the other end of the first chip detection sub-loop is coupled to a second solder ball in the ball grid array; The portion of the first chip detection sub-loop located in the die includes a first chip crack detection line, and the first chip crack detection line extends along at least one edge region of the die.

5. The chip crack detection circuit according to claim 3, wherein: One end of the first interposer detection sub-loop is coupled to a third solder ball in the ball grid array, and extends from the third solder ball through the substrate layer into the interposer, and then extends from the interposer to the substrate layer again, and the other end of the first interposer detection sub-loop is coupled to a fourth solder ball in the ball grid array; The portion of the first interposer detection sub-loop located in the interposer includes a first interposer crack detection line, and the first interposer crack detection line extends along at least one edge region of the interposer.

6. The chip crack detection circuit according to claim 3, wherein: The first substrate detection sub-loop extends in the substrate layer, and one end of the first substrate detection sub-loop is coupled to a fifth solder ball in the ball grid array, and the other end of the first substrate detection sub-loop is coupled to a sixth solder ball in the ball grid array; The first substrate detection sub-loop includes a first substrate crack detection line, and the first substrate crack detection line extends along at least one edge region of the substrate layer.

7. The chip crack detection circuit according to claim 3, wherein: One end of the second chip detection sub-loop is coupled to a first GPIO sub-interface of the GPIO interface, and extends from the first GPIO sub-interface through the bare die to the interposer, and then extends from the interposer back to the bare die, and the other end of the second chip detection sub-loop is coupled to a second GPIO sub-interface of the GPIO interface; The portion of the second chip detection sub-loop located in the die includes a second chip crack detection line, and the second chip crack detection line extends along at least one edge region of the die.

8. The chip crack detection circuit according to claim 3, wherein: One end of the second interposer detection sub-loop is coupled to a third GPIO sub-interface of the GPIO interfaces, and extends from the third GPIO sub-interface through the bare die and the interposer to the substrate layer, and then extends from the substrate layer through the interposer to the bare die, and the other end of the second interposer detection sub-loop is coupled to a fourth GPIO sub-interface of the GPIO interfaces; The portion of the second interlayer detection sub-loop located in the interlayer includes a second interlayer crack detection line, and the second interlayer crack detection line extends along at least one edge region of the interlayer.

9. The chip crack detection circuit according to claim 3, wherein: One end of the second substrate detection sub-loop is coupled to a fifth GPIO sub-interface of the GPIO interface, and extends from the fifth GPIO sub-interface through the bare die, the interposer, and the substrate layer to a seventh solder ball disposed on the substrate layer, then extends from the seventh solder ball to an eighth solder ball disposed on the substrate layer via an inter-solder ball connection line, and then extends from the eighth solder ball again through the substrate layer and the interposer to the bare die. The other end of the second substrate detection sub-loop is coupled to a sixth GPIO sub-interface of the GPIO interface; The portion of the second substrate detection sub-circuit located in the substrate layer includes a second substrate crack detection line, and the second substrate crack detection line extends along at least one edge region of the substrate layer.

10. A chip crack detection device, characterized in that: include: The chip crack detection circuit according to any one of claims 1 to 9; A signal transceiver detection device is coupled to the detection interface group.

11. A chip, characterized in that: include: A bare die, an interposer, and a substrate layer stacked together, and a chip crack detection circuit as claimed in any one of claims 1 to 9.

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