Flyback synchronous rectification control circuit
Through the flyback synchronous rectification control circuit, passive components and isolation devices are used to accurately control the dead zone and duty cycle of the drive signal, which solves the shortcomings of coil self-drive and chip drive methods, improves the reliability and efficiency of the power module, and is suitable for high-voltage and high-current scenarios.
Patent Information
- Application Number
- CN202422543232.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-10-21
AI Technical Summary
In the existing synchronous rectification method of the flyback converter, the coil self-drive has difficulty controlling the dead zone of the primary and secondary side drive signals. The chip drive cost is high and it is not suitable for high voltage and high current scenarios, resulting in low power supply reliability and efficiency.
A flyback synchronous rectification control circuit is adopted, and passive components are matched with an isolator and a driver to realize the reverse direction of the driving signal and the adjustable dead zone, and limit the maximum duty cycle. The threshold voltage and integrated comparator of the chips U1 and U3 are used to control the time delay of the driving signal. Combined with the adjustment of the resistance and capacitance of the capacitor and resistor, the dead zone and maximum duty cycle of the driving signal can be accurately adjusted.
The reliability of the power module is improved, and current backflow damage caused by the secondary-side switch being on for a long time during switching on and off and adjusting the output voltage is avoided. It is suitable for high-voltage and high-current environments and reduces the cost and complexity of the driver chip.
Smart Images
Figure CN223364038U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of switching power supplies, in particular to a flyback synchronous rectification control circuit. Background Art
[0002] With the development of the intelligent era, power electronic equipment continues to upgrade, power demand continues to increase, switching power supplies are becoming more and more extensive, covering a wider power range, and various power supply topologies are constantly being optimized and improved. Flyback switching power supplies are widely used in the range of tens to hundreds of watts, especially in multi-output applications. Under these conditions, the optimization of flyback switching power supplies is extremely important, especially in high-voltage flyback applications, where reliability and practicality must be taken into account simultaneously.
[0003] Currently, flyback converter synchronous rectification methods are mainly divided into two categories: coil self-drive and chip drive. The coil self-drive method is difficult to control and the primary and secondary drive dead zones cannot be controlled. The chip drive method is expensive and cannot be used in high-voltage and high-current scenarios, severely limiting its application scenarios.
[0004] Specifically, for coil-driven synchronous rectification, the drive signal is generated by the coil's induced voltage, which is proportional to the number of coil turns, which is always an integer multiple. The induced voltage per turn is fixed, so the amplitude of the drive signal cannot be precisely adjusted for this type of synchronous rectification. This limits its ability to meet the voltage amplitude requirements of the switching transistor drive signal. Furthermore, because the drive signal is induced by the coil, the dead zone of the primary and secondary drive signals cannot be controlled, significantly reducing the reliability of the power supply and increasing the risk of damage.
[0005] For chip-driven synchronous rectification, the chip's power comes from the power supply's output. When the power supply outputs high voltage, the chip's power comes from the power supply output. This requires very high voltage resistance for the chip. Currently, no driver chip on the market can withstand voltages of several hundred volts. Furthermore, when the module operates in intermittent mode, the output current capability is very low, potentially causing the chip to malfunction and switch to diode mode. Existing driver chips on the market are generally unstable. Under high-voltage, high-current output conditions, the chip is easily interfered with, resulting in abnormal drive signals and, in turn, the failure of the power supply to operate in synchronous rectification mode, significantly reducing power supply efficiency. Utility Model Content
[0006] The purpose of the present utility model is to provide a flyback synchronous rectification control circuit to solve the problem that the synchronous rectification methods of the flyback converter in the background technology are mainly divided into two categories: coil self-drive and chip drive. Among them, the coil self-drive method cannot realize the control of the original secondary side drive dead zone, and the chip drive cost is high and cannot be used in high voltage and high current scenarios.
[0007] To achieve the above-mentioned purpose, the technical solution of the present utility model provides a flyback synchronous rectification control circuit, which includes a drive control circuit, wherein the primary drive signal is connected to the second pin of the chip U1 through a resistor R1, the resistor R1 is connected in parallel with the diode D1, one end of the diode D1 is connected to the primary drive signal input end, and the other end is connected to the second pin of the chip U1; one end of the capacitor C1 is connected to the second pin of the chip U1, and the other end is connected to the fourth pin of the chip U1 and the primary ground; the seventh pin of the chip U1 is connected to the input end of the capacitor C2, the output end of the capacitor C2 is connected to the fourth pin of the chip U2, the third pin of the chip U2 is connected to the power supply through the resistor R4, and the fifth pin of the chip U1 and the second pin of the chip U2 are connected to the secondary ground.
[0008] Furthermore, it also includes a power conversion circuit, which includes a chip U3, the primary drive signal is connected to the input end of the resistor R6, the output end of the resistor R6 is connected to the third pin of the chip U3, the resistor R6 is connected in parallel with the diode D4, one end of the capacitor C4 is connected to the third pin of the chip U3 and the output end of the resistor R6, and the other end is connected to the primary ground; the fourth pin and the second pin of the chip U3 are both connected to the primary ground, and the first pin of the chip U3 is connected to the power supply; the fifth pin of the chip U3 is connected to the gate of the MOS tube Q1, the source of the MOS tube Q1 is connected to the primary ground, the drain of the MOS tube Q1 is connected to the non-identical terminal of the primary side of the driving transformer, and the identical terminal of the secondary side of the driving transformer is connected to the MOS tube Q2.
[0009] Furthermore, the fifth pin of the chip U2 is connected to the secondary side driving signal.
[0010] Furthermore, the drain of the MOS transistor Q2 is connected to the secondary-side same-name terminal of the driving transformer, the source is connected to the secondary-side ground, and the gate is connected to the secondary-side driving signal.
[0011] Furthermore, it also includes a resistor R3 and a diode D3, the input end of the resistor R3 is connected to the power supply, and the output end is connected to the output end of the capacitor C2 and the fourth pin of the chip U2; the diode D3 is connected in parallel with the resistor R3, its input end is connected to the power supply, and the output end is connected to the output end of the capacitor C2 and the fourth pin of the chip U2.
[0012] Furthermore, a diode D2 is included, one end of the diode D2 is connected to the power supply and the first pin of the chip U1, and the other end is connected to the output end of the resistor R1 and the second pin of the chip U1.
[0013] Furthermore, the chip U1 and the chip U3 have threshold voltages and integrated comparators inside.
[0014] The beneficial effects of the utility model include:
[0015] 1. Compared with coil self-drive, it is more controlled and can achieve precise adjustment of the dead zone of the primary and secondary side drive signals, greatly improving the reliability of the power module;
[0016] 2. The maximum duty cycle of the secondary-side drive signal is limited without the need for an external chip, effectively solving the problem of current backflow and power supply damage caused by the secondary-side switch being on for a long time during module power on / off and output voltage adjustment.
[0017] 3. The secondary-side drive signal control of the utility model is different from the driver chip. The secondary-side drive signal and the switch tube are not integrated. In the high-voltage and high-current output environment, only the appropriate switch tube needs to be selected, which makes up for the problem that the driver chip is limited in the high-voltage and high-current scenario. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 A schematic diagram of a drive control circuit provided by an embodiment of the present utility model;
[0020] Figure 2 A schematic diagram of a power conversion circuit provided by an embodiment of the present utility model; DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.
[0022] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the figures, or the orientation or position relationship in which the utility model product is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0023] The utility model can realize the reverse of the driving signal, the adjustable dead zone, and the limitation of the maximum positive duty cycle of the reverse driving signal by using passive components in combination with an isolator and a driver.
[0024] See Figure 1 As shown, at least one embodiment of the present disclosure provides a flyback synchronous rectification control circuit, which includes a drive control circuit, wherein the primary drive signal is connected to the second pin of the chip U1 through a resistor R1, the resistor R1 is connected in parallel with a diode D1, one end of the diode D1 is connected to the primary drive input end, and the other end is connected to the second pin of the chip U1; one end of the capacitor C1 is connected to the second pin of the chip U1, and the other end is connected to the fourth pin of the chip U1 and the primary ground; the seventh pin of the chip U1 is connected to the input end of the capacitor C2, the output end of the capacitor C2 is connected to the fourth pin of the chip U2, the fifth pin of the chip U2 is connected to the secondary drive signal, the third pin of the chip U2 is connected to the power supply through a resistor R4, the fifth pin of the chip U1 and the second pin of the chip U2 are connected to the secondary ground, the input end of the resistor R3 is connected to the power supply, and the output end is connected to the output end of the capacitor C2 and the fourth pin of the chip U2, and the diode D3 is connected in parallel with the resistor R3; one end of the diode D2 is connected to the power supply and the first pin of the chip U1, and the other end is connected to the output end of the resistor R1 and the second pin of the chip U1.
[0025] Specifically, in this embodiment, the diode D2 and the diode D3 play a clamping role, the purpose of which is to clamp the anode voltage of the diode to protect the chip pins.
[0026] Specifically, in this embodiment, the chip U1 acts as an isolator to isolate the input side and output side signals from each other.
[0027] like Figure 2 As shown, it also includes a power conversion circuit, which includes a chip U3, the primary side drive signal is connected to the input end of the resistor R6, the output end of the resistor R6 is connected to the third pin of the chip U3, the resistor R6 is connected in parallel with the diode D4, one end of the capacitor C4 is connected to the third pin of the chip U3 and the output end of the resistor R6, and the other end is connected to the primary side ground; the fourth pin and the second pin of the chip U3 are both connected to the primary side ground, and the first pin of the chip U3 is connected to the power supply; the fifth pin of the chip U3 is connected to the gate of the MOS tube Q1, the source of the MOS tube Q1 is connected to the primary side ground, the drain of the MOS tube Q1 is connected to the non-identical terminal of the primary side of the driving transformer, the identical terminal of the secondary side of the driving transformer is connected to the MOS tube Q2, the drain of the MOS tube Q2 is connected to the identical terminal of the secondary side of the driving transformer, the source is connected to the secondary side ground, and the gate is connected to the secondary side drive signal.
[0028] In this embodiment, the primary side drive signal is input to pin 2 of chip U1 and pin 3 of U3 through resistor R1, capacitor C1, diode D1 and resistor R6, capacitor C4, diode D4 respectively; since there is a threshold voltage inside chip U1 and chip U3 and an integrated comparator, the dead time control of the primary and secondary sides is achieved by changing the charging and discharging time for the capacitor voltage value to reach the threshold voltage.
[0029] When the primary drive signal is high, increasing the resistance and capacitance of resistor R1 and capacitor C1 will lengthen the time it takes for capacitor C1 to charge to the threshold voltage, and the falling edge of the secondary drive will be delayed. Otherwise, the falling edge will arrive earlier.
[0030] When the primary drive signal is high, increasing the resistance and capacitance of resistor R6 and capacitor C4 will prolong the time it takes for capacitor C4 to charge to the threshold voltage, and the rising edge of the primary drive signal will be delayed. Otherwise, the rising edge will arrive earlier.
[0031] By combining the above two situations, accurate adjustment of the dead time can be achieved.
[0032] In this embodiment, the drive signal is reversed using driver chip U2. The non-inverting input of driver chip U2 is connected to a 5V power supply via pull-up resistor R4, while the inverting input is connected to the 5V power supply and the right side of capacitor C2 via diode D3 and resistor R3. The left side of capacitor C2 is connected to the output terminal O1 of the isolator. When the primary drive signal transitions from a low level to a high level, the driver output terminal O1 also transitions from a low level to a high level, outputting 5V. Because the voltage across the capacitor cannot change suddenly, the potential at pin 4 of chip U2 is instantly raised. Diode D3 then clamps the voltage to approximately 5.5V, ultimately maintaining the voltage at 5V and protecting the driver pins. At this point, because the voltage at the inverting input of driver chip U2 is higher than or equal to the non-inverting input, output terminal 5 will output a low level. When the primary drive signal changes from high to low, the driver output terminal O1 will also change from 5V high to low. At this time, since the voltage across the capacitor cannot change suddenly, the potential of U2's pin 4 will be instantly pulled down. At this time, the 5V power supply charges the capacitor C2 through the resistor R3. Before reaching the comparator threshold voltage of the driver chip U2, since the voltage of the driver U2's non-inverting input terminal is higher than the inverting input terminal, the output terminal pin 5 will output a high level. This realizes the function of reverse driving signal.
[0033] In this embodiment, when the primary drive signal transitions from a high level to a low level, the driver output terminal O1 also transitions from a 5V high level to a low level. At this point, because the voltage across the capacitor cannot change suddenly, the potential at pin 4 of U2 is instantly pulled down, the voltage at the non-inverting input of driver U2 becomes higher than the voltage at the inverting input, and output pin 5 outputs a high level. At this point, the 5V power supply charges capacitor C2 via R3. When the voltage at pin 4 of isolator U2 reaches the threshold voltage, the output of the isolator will transition from a high level to a low level. The 5V power supply charges capacitor C2 via R3 until it reaches the threshold voltage of isolator U2. By varying the resistance and capacitance values of C2 and R3, the time it takes for the voltage at pin 4 of U2 to reach the threshold voltage of isolator U2 is controlled to limit the maximum duty cycle. Increasing the values of C2 and R3 increases the maximum duty cycle, while decreasing them decreases it.
[0034] In this embodiment, the maximum positive duty cycle of the secondary side can also be limited. Specifically, when the primary side drive signal changes from a high level to a low level, the driver output terminal O1 also changes from a 5V high level to a low level. At this time, because the voltage across the capacitor cannot change suddenly, the potential of pin 4 of chip U2 will be instantly pulled down, the voltage at the non-inverting input terminal of driver chip U2 will be higher than the voltage at the reverse input terminal, and the output terminal 5 will output a high level. At this time, the 5V power supply charges capacitor C2 through resistor R3. When the voltage at pin 4 of isolation chip U2 reaches the threshold voltage, the output of the isolation chip will change from high to low. The 5V power supply charges capacitor C2 through resistor R3 to the isolation chip U2 threshold voltage before the isolation chip U2 threshold voltage is reached. The maximum duty cycle is limited by changing the resistance and capacitance values of capacitor C2 and resistor R3 to control the time when the voltage at pin 4 of isolation chip U2 reaches the isolation chip U2 threshold voltage. Increasing the values of capacitor C2 and resistor R3 will increase the maximum duty cycle, while decreasing the values of capacitor C2 and resistor R3 will reduce the maximum duty cycle.
[0035] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A flyback synchronous rectification control circuit, characterized in that: It includes a drive control circuit, in which the primary drive signal is connected to the second pin of the chip U1 through a resistor R1, the resistor R1 is connected in parallel with a diode D1, one end of the diode D1 is connected to the primary drive signal input end, and the other end is connected to the second pin of the chip U1; one end of the capacitor C1 is connected to the second pin of the chip U1, and the other end is connected to the fourth pin of the chip U1 and the primary ground; the seventh pin of the chip U1 is connected to the input end of the capacitor C2, the output end of the capacitor C2 is connected to the fourth pin of the chip U2, the third pin of the chip U2 is connected to the power supply through a resistor R4, and the fifth pin of the chip U1 and the second pin of the chip U2 are connected to the secondary ground.
2. A flyback synchronous rectification control circuit according to claim 1, characterized in that: It also includes a power conversion circuit, which includes a chip U3, the primary drive signal is connected to the input end of the resistor R6, the output end of the resistor R6 is connected to the third pin of the chip U3, the resistor R6 is connected in parallel with the diode D4, one end of the capacitor C4 is connected to the third pin of the chip U3 and the output end of the resistor R6, and the other end is connected to the primary ground; the fourth pin and the second pin of the chip U3 are both connected to the primary ground, and the first pin of the chip U3 is connected to the power supply; the fifth pin of the chip U3 is connected to the gate of the MOS tube Q1, the source of the MOS tube Q1 is connected to the primary ground, the drain of the MOS tube Q1 is connected to the non-identical terminal of the primary side of the driving transformer, and the identical terminal of the secondary side of the driving transformer is connected to the MOS tube Q2.
3. The flyback synchronous rectification control circuit according to claim 1, characterized in that: The fifth pin of the chip U2 is connected to the secondary side drive signal.
4. The flyback synchronous rectification control circuit according to claim 2, characterized in that: The drain of the MOS transistor Q2 is connected to the secondary-side same-name terminal of the driving transformer, the source is connected to the secondary-side ground, and the gate is connected to the secondary-side driving signal.
5. The flyback synchronous rectification control circuit according to claim 1, characterized in that: It also includes a resistor R3 and a diode D3, the input end of the resistor R3 is connected to the power supply, and the output end is connected to the output end of the capacitor C2 and the fourth pin of the chip U2; the diode D3 is connected in parallel with the resistor R3, its input end is connected to the power supply, and its output end is connected to the output end of the capacitor C2 and the fourth pin of the chip U2.
6. The flyback synchronous rectification control circuit according to claim 1, characterized in that: It also includes a diode D2, one end of which is connected to the power supply and the first pin of the chip U1, and the other end is connected to the output end of the resistor R1 and the second pin of the chip U1.
7. The flyback synchronous rectification control circuit according to claim 2, characterized in that: The chip U1 and the chip U3 have a threshold voltage and an integrated comparator inside.