Wireless communication system

Abstract

The utility model discloses a wireless communication system which comprises an audio input device, a plurality of transmitters and a signal receiving host. The audio input device is used for collecting a sound signal, converting the sound signal into a first analog audio signal, and sending the first analog audio signal to each transmitter. The transmitter is used for receiving the first analog audio signal, performing signal enhancement processing on the first analog audio signal to obtain a transmitting signal, and transmitting the transmitting signal; and the signal receiving host is used for receiving the transmitting signal, demodulating the transmitting signal, performing clock synchronization processing at the same time, obtaining a target audio signal, and outputting the target audio signal. The signal transmission distance can be effectively increased, the coverage range is wider, the method can be effectively applied to various scenes, clock synchronization between the transmitted signal and the finally output target audio signal can be kept, the stability is improved, and the quality is ensured.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a wireless communication system. Background Art

[0002] With the rapid development of science and technology, human demand for communication is growing. Wireless communication systems have emerged and undergone profound reforms. Today, wireless communication technology has been widely used in various scenarios, such as broadcasting, conferences, offices, etc., and can realize the transmission and interaction of multimedia information such as data and voice.

[0003] In particular, audio signals are prone to signal distortion during transmission and processing, which affects the quality and stability of the audio signals. Utility Model Content

[0004] In view of this, the present application provides a wireless communication system for solving the problem that audio signals are easily distorted during transmission and processing, thereby affecting the quality and stability of the audio signals.

[0005] To achieve the above objectives, the following solutions are proposed:

[0006] A wireless communication system includes: an audio input device 1, a plurality of transmitters 2 and a signal receiving host 3;

[0007] The audio input device 1 is used to collect sound signals, convert the sound signals into first analog audio signals, and send the first analog audio signals to each of the transmitters 2;

[0008] The transmitter 2 is used to receive the first analog audio signal, perform signal enhancement processing on the first analog audio signal to obtain a transmission signal, and transmit the transmission signal;

[0009] The signal receiving host 3 is used to receive the transmission signal, demodulate the transmission signal, perform clock synchronization processing, obtain the target audio signal, and output the target audio signal.

[0010] Preferably, the transmitter 2 includes an analog-to-digital encoding chip 21, a first microcontroller unit 22, a transmitting chip 23, a power amplifier 24 and a built-in antenna 25;

[0011] The analog-to-digital encoding chip 21 is used to receive the first analog audio signal, perform analog-to-digital conversion on the first analog audio signal to obtain a digital signal, and send the digital signal to the first microcontroller unit 22;

[0012] The first microcontroller unit 22 is used to receive the digital signal, perform communication protocol conversion on the digital signal, obtain a first signal, and send the first signal to the transmitting chip 23;

[0013] The transmitting chip 23 is used to receive the first signal, perform signal modulation on the first signal to obtain a second signal, and send the second signal to the power amplifier 24;

[0014] The power amplifier 24 is used to receive the second signal, perform power amplification processing on the second signal to obtain a transmission signal, and send the transmission signal to the built-in antenna 25;

[0015] The built-in antenna 25 is used to receive the transmission signal and transmit it.

[0016] Preferably, the signal receiving host 3 includes a directional receiving antenna 31, a signal distribution unit 32, a clock synchronization unit 33, a digital-analog decoding unit 34 and an output unit 35;

[0017] The directional receiving antenna 31 is used to receive the transmission signal and send the transmission signal to the signal distribution unit 32;

[0018] The signal distribution unit 32 is used to receive the transmission signal, distribute the transmission signal to obtain individual distribution signals, and send the individual distribution signals to the clock synchronization unit 33;

[0019] The clock synchronization unit 33 is used to receive each of the distribution signals, demodulate each of the distribution signals, and perform clock synchronization processing to obtain a third signal, and send it to the digital-analog decoding unit 34;

[0020] The digital-to-analog decoding unit 34 is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a target audio signal, and send the target audio signal to the output unit 35;

[0021] The output unit 35 is configured to receive and output the target audio signal.

[0022] Preferably, the signal distribution unit 32 includes a low noise amplifier 321 and a signal distribution circuit 322;

[0023] The low noise amplifier 321 is used to receive the transmission signal, enhance the signal strength of the transmission signal, obtain an amplified signal, and send the amplified signal to the signal distribution circuit 322;

[0024] The signal distribution circuit 322 is configured to receive the amplified signal, distribute the amplified signal to obtain distributed signals, and send the distributed signals to the clock synchronization unit 33 .

[0025] Preferably, the clock synchronization unit 33 includes a clock chip 331, several receiving chips 332 and a second microcontroller unit 333;

[0026] The clock chip 331 is used to send clock signals to each of the receiving chips 332;

[0027] The receiving chip 332 is used to receive the distribution signal and the clock signal, demodulate the distribution signal, and use the clock signal to perform clock synchronization to obtain a demodulated signal, and send the demodulated signal to the second microcontroller unit 333;

[0028] The second microcontroller unit 333 is used to receive the demodulated signal, perform communication protocol conversion on the demodulated signal, obtain a third signal, and send it to the digital-to-analog decoding unit 34 .

[0029] Preferably, the digital-analog decoding unit 34 includes a digital-analog decoding chip 341 and an audio amplifying circuit 342;

[0030] The digital-to-analog decoding chip 341 is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a second analog audio signal, and send the second analog audio signal to the audio amplification circuit 342;

[0031] The audio amplifying circuit 342 is configured to receive the second analog audio signal, amplify the second analog audio signal to obtain a target audio signal, and send the target audio signal to the output unit 35 .

[0032] Preferably, the signal receiving host 3 further includes a display screen 36;

[0033] The display screen 36 is connected to the clock synchronization unit 33 and is used to display the third signal sent by the clock synchronization unit 33 .

[0034] Preferably, the transmitter 2 is a 2.4G transmitter, and the signal receiving host 3 is a 2.4G signal receiving host.

[0035] Preferably, the first microcontroller unit 22 is an STM32 single chip microcomputer.

[0036] Preferably, the second microcontroller unit 333 is an STM32 single chip microcomputer.

[0037] It can be seen from the above technical solution that the present application provides a wireless communication system, including an audio input device 1, several transmitters 2 and a signal receiving host 3; the audio input device 1 is used to collect sound signals, and convert the sound signals into a first analog audio signal, and send the first analog audio signal to each of the transmitters 2; the transmitter 2 is used to receive the first analog audio signal, and perform signal enhancement processing on the first analog audio signal to obtain a transmission signal, and transmit the transmission signal; the signal receiving host 3 is used to receive the transmission signal, demodulate the transmission signal, and perform clock synchronization processing at the same time to obtain a target audio signal, and output the target audio signal. The wireless communication system in the present application includes an audio input device 1, several transmitters 2 and a signal receiving host 3, and is connected through a first analog audio signal and a transmission signal. First, the sound signal emitted by the user is converted into a first analog audio signal so that it can be processed by the transmitter 2, and the transmitter 2 performs signal enhancement processing on the first analog audio signal. This can effectively improve the transmission distance of the first analog audio signal and have a wider coverage range. It can be effectively used in various scenarios without being blocked or interfered with by other devices or physical obstacles in the scene, thereby obtaining a transmission signal, and then transmitting the transmission signal, which is received by the signal receiving host 3, demodulated and clock synchronized at the same time. In this way, the clock synchronization between the transmission signal and the target audio signal finally output can be maintained to improve stability and ensure quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the structure of a wireless communication system provided in an embodiment of the present application;

[0039] Figure 2 A schematic diagram of the structure of a transmitter provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of a signal receiving host provided in an embodiment of the present application;

[0041] Figure 4 A schematic structural diagram of a signal distribution unit provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of the structure of a clock synchronization unit provided in an embodiment of the present application;

[0043] Figure 6 A schematic structural diagram of a digital-to-analog decoding unit provided in an embodiment of the present application;

[0044] Figure 7 A schematic structural diagram of another signal receiving host provided in an embodiment of the present application.

[0045] In the figure: 1. Audio input device; 2. Transmitter; 3. Signal receiving host; 21. Analog-to-digital encoding chip; 22. First microcontroller unit; 23. Transmitter chip; 24. Power amplifier; 31. Directional receiving antenna; 32. Signal distribution unit; 33. Clock synchronization unit; 34. Digital-to-analog decoding unit; 35. Output unit; 36. Display screen; 321. Low noise amplifier; 322. Signal distribution circuit; 331. Clock chip; 332. Receiving chip; 333. Second microcontroller unit; 341. Digital-to-analog decoding chip; 342. Audio amplification circuit. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] With the rapid development of science and technology, humanity's demand for communications has grown. Wireless communication systems have emerged and undergone profound reforms. Today, wireless communication technology is widely used in various scenarios, such as broadcasting, conferences, and offices, enabling the transmission and interaction of multimedia information such as data and voice. In particular, audio signals are prone to signal distortion during transmission and processing, affecting their quality and stability.

[0048] See also Figure 1 , Figure 1 A schematic diagram of the structure of a wireless communication system provided in an embodiment of the present application is shown in FIG. Figure 1 As shown:

[0049] The system includes an audio input device 1, several transmitters 2 and a signal receiving host 3;

[0050] The audio input device 1 is used to collect sound signals, convert the sound signals into first analog audio signals, and send the first analog audio signals to each of the transmitters 2; a microphone, sound receiver, etc. can be selected as the audio input device, and this embodiment does not limit this.

[0051] The transmitter 2 is used to receive the first analog audio signal, perform signal enhancement processing on the first analog audio signal to obtain a transmission signal, and transmit the transmission signal;

[0052] The signal receiving host 3 is used to receive the transmission signal, perform clock synchronization processing on the transmission signal, perform digital-to-analog conversion, obtain the target audio signal, and output the target audio signal.

[0053] Specifically, the sound signal can be emitted by a user or any device that can emit an audio signal. The audio input device 1 can collect and convert the sound signal into a first analog audio signal, which also needs to be emitted to each transmitter 2.

[0054] The present application sets up multiple transmitters 2, and these multiple transmitters 2 all correspond to the same signal receiving host 3. There is no need for point-to-point transmission, and there is no need to set up multiple receiving devices in the signal receiving host 3, which improves convenience and simplicity. Among them, each transmitter 2 can receive the first analog audio signal and perform signal enhancement processing on the first analog audio signal, such as signal power enhancement. Therefore, the transmitter 2 can be a power amplifier or the transmitter 2 contains a multi-stage amplification circuit, both of which can achieve the purpose of signal enhancement, so that the coverage range of the first analog audio signal is wider, and the transmission distance of the first analog audio signal can be effectively improved. For example, in some scenarios, the signal is easily affected by interference from wireless devices, obstruction by physical obstacles, etc., or when there are many people, the location of the people or the movement of the people will cause the signal to be intermittent or lost, thereby affecting the transmission or transmission of the signal. Then, enhancing the first analog audio signal can overcome this problem, and the transmission signal is obtained after the enhancement processing and transmitted.

[0055] The signal receiving host 3 can receive the transmission signals sent by multiple transmitters 2, and demodulate each transmission signal separately, and perform clock synchronization processing at the same time. Since the signal is prone to signal distortion or packet loss during the demodulation process, and is also susceptible to external or internal interference, performing clock synchronization processing while demodulating can ensure that the demodulated signal maintains the same clock as the signal before demodulation, enhance anti-interference ability, improve stability, and ensure quality.

[0056] Optionally, the structural diagram of the transmitter 2 may be as follows: Figure 2 shown, including:

[0057] Analog-to-digital encoding chip 21, first microcontroller unit 22, transmitting chip 23, power amplifier 24 and built-in antenna 25;

[0058] The analog-to-digital encoding chip 21 is used to receive the first analog audio signal, perform analog-to-digital conversion on the first analog audio signal to obtain a digital signal, and send the digital signal to the first microcontroller unit 22;

[0059] The first microcontroller unit 22 is used to receive the digital signal, perform communication protocol conversion on the digital signal, obtain a first signal, and send the first signal to the transmitting chip 23;

[0060] The transmitting chip 23 is used to receive the first signal, perform signal modulation on the first signal to obtain a second signal, and send the second signal to the power amplifier 24;

[0061] The power amplifier 24 is used to receive the second signal, perform power amplification processing on the second signal to obtain a transmission signal, and send the transmission signal to the built-in antenna 25;

[0062] The built-in antenna 25 is used to receive the transmission signal and transmit it.

[0063] Specifically, the first analog audio signal is an analog signal. The analog-to-digital encoding chip 21 can perform analog-to-digital conversion on the first analog audio signal, i.e., ADC (Analog-to-Digital Conversion), to obtain a digital signal. The analog-to-digital encoding chip 21 can select any existing chip capable of analog-to-digital conversion, such as the CS53 series chip. After the conversion, the digital signal needs to be sent to the first microcontroller unit 22.

[0064] The first microcontroller unit 22 and the analog-to-digital encoding chip 21 can be connected via an I2S bus. The analog-to-digital encoding chip 21 transmits the digital signal to the first microcontroller unit 22 via the I2S bus. The I2S bus is a serial bus standard for audio data transmission between digital audio devices. It enables audio data to be transmitted between different audio components or structures in a simple and efficient manner.

[0065] The first microcontroller unit 22 is actually an MCU (Microcontroller Unit), also known as a single-chip microcomputer or single-chip microcomputer. It is a microcomputer that integrates key functional components such as a central processing unit (CPU), memory, timers / counters, and input / output (I / O) interfaces on a single integrated circuit chip. After receiving the digital signal, the first microcontroller unit 22 needs to convert the communication protocol. This is because the analog-to-digital encoding chip 21 and the transmitter chip 23 may follow different communication protocols. For example, the analog-to-digital encoding chip 21 communicates using the I2C protocol, while the transmitter chip 23 communicates using the SPI protocol. In this case, the first microcontroller unit 22 needs to perform protocol conversion, communicating with the analog-to-digital encoding chip 21 as an I2C master device on one side and communicating with the transmitter chip 23 as an SPI slave device on the other side. This allows the two chips using different protocols to exchange or transmit data. In addition, the first microcontroller unit 22 can also perform data format conversion. For example, if the analog-to-digital encoding chip 21 and the transmitting chip 23 use different data formats, the first microcontroller unit 22 needs to perform format conversion; if the analog-to-digital encoding chip 21 and the transmitting chip 23 use different encoding methods, the first microcontroller unit 22 can also encode and re-decode so that the data between the two chips can be correctly understood and processed.

[0066] After the conversion is completed, the first microcontroller unit 22 obtains the first signal and sends it to the transmitting chip 23. The transmitting chip 23 needs to modulate the first signal. The SI24 series chip can be selected as the transmitting chip 23 of this application. It is a wireless radio frequency chip that can modulate the first signal, enhance the transmission and receiving capabilities of the first signal, extend the communication distance of the first signal, and improve the communication quality, thereby obtaining the second signal and sending the second signal to the power amplifier 24.

[0067] In order to further make the signal stronger, the present application also sets a power amplifier 24 in the transmitter 2 to perform power amplification processing on the second signal to obtain a transmission signal, and the RFX24 series chip can be used.

[0068] After the transmitter 2 completes the processing, it needs to be transmitted. The built-in antenna can be used to send the transmission signal to the built-in antenna 25, which is then transmitted by the built-in antenna 25. The use of a built-in antenna can save external space and can be better integrated into the transmitter 2 without increasing the volume of the transmitter 2. It can also prevent external physical damage, making the overall appearance of the wireless communication system more concise and smooth.

[0069] Optionally, the structural diagram of the signal receiving host 3 can be as follows: Figure 3 shown, including:

[0070] Directional receiving antenna 31, signal distribution unit 32, clock synchronization unit 33, digital-analog decoding unit 34 and output unit 35;

[0071] The directional receiving antenna 31 is used to receive the transmission signal and send the transmission signal to the signal distribution unit 32;

[0072] The signal distribution unit 32 is used to receive the transmission signal, distribute the transmission signal to obtain individual distribution signals, and send the individual distribution signals to the clock synchronization unit 33;

[0073] The clock synchronization unit 33 is used to receive each of the distribution signals, demodulate each of the distribution signals, and perform clock synchronization processing to obtain a third signal, and send it to the digital-analog decoding unit 34;

[0074] The digital-to-analog decoding unit 34 is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a target audio signal, and send the target audio signal to the output unit 35;

[0075] The output unit 35 is configured to receive and output the target audio signal.

[0076] Specifically, the directional receiving antenna 31 is specifically for the transmitter 2, and can directionally receive the signal transmitted by the transmitter 2 and send it to the signal distribution unit 32. In order to better process the transmitted signal, the present application sets a signal distribution unit in the signal receiving host 3, which can distribute the transmitted signal to obtain multiple signals, thereby improving the overall reliability of the wireless communication system and enhancing the functionality, and then send them to the clock synchronization unit 33 simultaneously.

[0077] The clock synchronization unit 33 can ensure that the signal receiving host 3 performs clock synchronization processing simultaneously during the demodulation process, keeps the clock consistent, enhances the signal's anti-interference ability, and improves stability and quality; in addition, since the crystal oscillator and load capacitance on each chip used in the wireless communication system have certain errors, approximately 1%-5%, it will cause a certain deviation in the signal's clock frequency CLK, so it needs to be adjusted to maintain synchronization and maintain the quality of the signal itself. After completion, the third signal is obtained and sent to the digital-to-analog decoding unit 34.

[0078] This application performs analog-to-digital encoding in the transmitter 2, so digital-to-analog decoding, i.e., Digital-to-Analog Decoding, is also required in the signal receiving host 3. The digital signal is converted into an analog signal through the digital-to-analog decoding unit 34, i.e., the digital-to-analog decoding unit 34 performs digital-to-analog decoding on the third signal to obtain the target audio signal in analog form, and sends it to the output unit 35, which outputs it, thereby completing the entire wireless communication process.

[0079] In a specific implementation process, the signal distribution unit 32 may include a low noise amplifier 321 and a signal distribution circuit 322, such as Figure 4 As shown, the low-noise amplifier 321 (Low-Noise Amplifier, LNA) can amplify the signal while minimizing the introduced noise, providing a signal of sufficient strength for the subsequent signal transmission process. For example, the RF24 series chip is selected as the low-noise amplifier 321. After amplification, the amplified signal is obtained and sent to the signal distribution circuit 322 for signal distribution.

[0080] In the specific implementation process, the specific structure of the clock synchronization unit 33 can be as follows: Figure 5 As shown, it includes a clock chip 331, several receiving chips 332 and a second microcontroller unit 333;

[0081] The clock chip 331 is used to send clock signals to each of the receiving chips 332;

[0082] The receiving chip 332 is used to receive the distribution signal and the clock signal, demodulate the distribution signal, and use the clock signal to perform clock synchronization to obtain a demodulated signal, and send the demodulated signal to the second microcontroller unit 333;

[0083] The second microcontroller unit 333 is used to receive the demodulated signal, perform communication protocol conversion on the demodulated signal, obtain a third signal, and send it to the digital-to-analog decoding unit 34 .

[0084] Specifically, the present application sets up multiple receiving chips 332 in the clock synchronization unit 33. On the one hand, this can ensure the normal transmission of signals. For example, when a receiving chip 332 fails, other receiving chips 332 can still receive the distribution signal normally, ensuring that the function of the overall wireless communication system is not affected. In addition, it is convenient to compare whether the demodulated signals output by multiple receiving chips 332 are the same to determine whether there is a failure in the receiving chip 332; on the other hand, multiple receiving chips 332 can process the distribution signal at the same time, improve the processing speed and efficiency of the wireless communication system, and meet wireless communication scenarios with high real-time requirements, such as radar signal processing, high-speed audio and video signal acquisition, etc.; from another perspective, multiple receiving chips 332 can use different types of chips respectively, so that the distribution signal can be processed differently according to their own functions, thereby realizing the diversification of the functions of the wireless communication system.

[0085] The receiving chip 332 performs demodulation and clock synchronization simultaneously. The clock chip 331 sends a clock signal CLK to each receiving chip 332. In one example, there are four receiving chips 332, namely receiving chip 3321, receiving chip 3322, receiving chip 3323, and receiving chip 3324. The clock chip 331 sends CLK1, CLK2, CLK3, and CLK4 to these four receiving chips respectively. Then, these four receiving chips 332 respectively demodulate the allocated signal they receive and use the CLK they receive to perform clock synchronization while demodulating. The receiving chip 332 can keep the demodulated signal consistent with the signal before demodulation, reducing the impact of the demodulation process on the signal. After the receiving chip 332 is processed, it needs to be sent to the second microcontroller unit 333. The second microcontroller unit 333 has the same function as the first microcontroller unit 22, performing communication protocol conversion to obtain a third signal for transmission to the digital-to-analog decoding unit 34. Optionally, both the second microcontroller unit 333 and the first microcontroller unit 22 use STM32 single-chip microcomputers.

[0086] It should be noted that there is also a connection relationship between the clock chip 331 and the second microcontroller unit 333, such as communication through I2C, so that the second microcontroller unit 333 can read the status information of the clock chip 331 through I2C, such as whether the clock chip 331 is working normally, whether the current output frequency is accurate, whether there are errors or warning signals, etc., which can also ensure the stability and reliability of the entire wireless communication system.

[0087] The clock chip 331 in this application can be directly obtained or purchased.

[0088] In the specific implementation process, Figure 6As shown, the digital-analog decoding unit 34 includes a digital-analog decoding chip 341 and an audio amplifier circuit 342;

[0089] The digital-to-analog decoding chip 341 is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a second analog audio signal, and send the second analog audio signal to the audio amplification circuit 342;

[0090] The audio amplifying circuit 342 is configured to receive the second analog audio signal, amplify the second analog audio signal to obtain a target audio signal, and send the target audio signal to the output unit 35 .

[0091] Specifically, the digital-to-analog decoding chip 341 can be implemented by a digital-to-analog decoding circuit (DAC) provided therein. The digital-to-analog decoding chip 341 can select a chip of the CS43 series. After the digital-to-analog conversion and decoding are completed, the signal is sent to the audio amplification circuit 342 for further power amplification processing, thereby making the coverage range of the target audio signal wider and effectively improving its transmission distance.

[0092] Furthermore, the signal receiving host 3 may further include a display screen 36, which is connected to the clock synchronization unit 33 and is used to display the third signal sent by the clock synchronization unit 33, such as Figure 7 As shown, the display screen 36 allows the user to clearly understand the processing and transmission status of the third signal, so as to grasp the dynamics in real time and discover problems in real time to ensure the normal operation of the wireless communication system.

[0093] Furthermore, the transmitter 2, signal receiving host 3, transmitting chip 23, and receiving chip 332 in this application can all be 2.4G. For example, in a conference scenario, 2.4G wireless communication technology is used to enable participants to achieve audio transmission and interaction without connecting cables. Although 2.4G wireless communication technology has the advantages of low cost and high bandwidth, the signal propagation range of the 2.4GHZ frequency band is limited, and its transmission distance is short. It can usually only be effectively transmitted within a range of forty or fifty meters, which undoubtedly limits its application scenarios and scope. The present application realizes multiple signal power amplification processing through the power amplifier 24, the low noise amplifier 321 and the audio amplifier circuit 342, wherein the power amplifier 24 can The signal strength of the second signal is enhanced by 22DB. The connection between the low-noise amplifier 321 and the directional receiving antenna 31 can increase the signal receiving sensitivity by 28DB-33DB. The high-intensity signal ensures its own stability and anti-interference. The higher signal receiving sensitivity ensures the stability of signal reception, greatly improves the signal transmission distance, and makes its coverage wider. It can be applied in more scenarios, especially in 2.4G wireless communication scenarios. For example, the existing 2.4GHZ frequency band signal transmission distance of forty to fifty meters can be increased to more than 100 meters; in addition, the gain of an ordinary 2.4G rod antenna is 3~5DB, and the directional receiving antenna 31 selected in this application can increase the gain to 10~15DB.

[0094] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0095] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined with each other, and the same or similar parts between the various embodiments can be referenced to each other.

[0096] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wireless communication system, characterized in that: include: An audio input device (1), a plurality of transmitters (2) and a signal receiving host (3); The audio input device (1) is used to collect sound signals, convert the sound signals into first analog audio signals, and send the first analog audio signals to each of the transmitters (2); The transmitter (2) is used to receive the first analog audio signal, perform signal enhancement processing on the first analog audio signal, obtain a transmission signal, and transmit the transmission signal; The signal receiving host (3) is used to receive the transmission signal, demodulate the transmission signal, perform clock synchronization processing, obtain the target audio signal, and output the target audio signal.

2. The system according to claim 1, wherein: The transmitter (2) includes an analog-to-digital encoding chip (21), a first microcontroller unit (22), a transmitting chip (23), a power amplifier (24) and a built-in antenna (25); The analog-to-digital encoding chip (21) is used to receive the first analog audio signal, perform analog-to-digital conversion on the first analog audio signal to obtain a digital signal, and send the digital signal to the first microcontroller unit (22); The first microcontroller unit (22) is used to receive the digital signal, perform communication protocol conversion on the digital signal, obtain a first signal, and send the first signal to the transmitting chip (23); The transmitting chip (23) is used to receive the first signal, perform signal modulation on the first signal to obtain a second signal, and send the second signal to the power amplifier (24); The power amplifier (24) is used to receive the second signal, perform power amplification processing on the second signal, obtain a transmission signal, and send the transmission signal to the built-in antenna (25); The built-in antenna (25) is used to receive the transmission signal and transmit it.

3. The system according to claim 1, wherein: The signal receiving host (3) includes a directional receiving antenna (31), a signal distribution unit (32), a clock synchronization unit (33), a digital-analog decoding unit (34) and an output unit (35); The directional receiving antenna (31) is used to receive the transmission signal and send the transmission signal to the signal distribution unit (32); The signal distribution unit (32) is used to receive the transmission signal, distribute the transmission signal to obtain individual distribution signals, and send the individual distribution signals to the clock synchronization unit (33); The clock synchronization unit (33) is used to receive each of the distribution signals, demodulate each of the distribution signals, and perform clock synchronization processing to obtain a third signal, and send it to the digital-analog decoding unit (34); The digital-to-analog decoding unit (34) is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a target audio signal, and send the target audio signal to the output unit (35); The output unit (35) is used to receive and output the target audio signal.

4. The system according to claim 3, characterized in that The signal distribution unit (32) includes a low noise amplifier (321) and a signal distribution circuit (322); The low noise amplifier (321) is used to receive the transmission signal, enhance the signal strength of the transmission signal, obtain an amplified signal, and send the amplified signal to the signal distribution circuit (322); The signal distribution circuit (322) is used to receive the amplified signal, distribute the amplified signal to obtain individual distributed signals, and send the individual distributed signals to the clock synchronization unit (33).

5. The system according to any one of claims 3 or 4, characterized in that: The clock synchronization unit (33) includes a clock chip (331), a plurality of receiving chips (332) and a second microcontroller unit (333); The clock chip (331) is used to send a clock signal to each of the receiving chips (332); The receiving chip (332) is used to receive the distribution signal and the clock signal, demodulate the distribution signal, and simultaneously use the clock signal for clock synchronization to obtain a demodulated signal, and send the demodulated signal to the second microcontroller unit (333); The second microcontroller unit (333) is used to receive the demodulated signal, perform communication protocol conversion on the demodulated signal, obtain a third signal, and send it to the digital-to-analog decoding unit (34).

6. The system according to claim 3, wherein: The digital-analog decoding unit (34) includes a digital-analog decoding chip (341) and an audio amplification circuit (342); The digital-to-analog decoding chip (341) is used to receive the third signal, perform digital-to-analog conversion on the third signal, obtain a second analog audio signal, and send the second analog audio signal to the audio amplification circuit (342); The audio amplifying circuit (342) is used to receive the second analog audio signal, amplify the second analog audio signal, obtain a target audio signal, and send the target audio signal to the output unit (35).

7. The system according to claim 3, wherein: The signal receiving host (3) further includes a display screen (36); The display screen (36) is connected to the clock synchronization unit (33) and is used to display the third signal sent by the clock synchronization unit (33).

8. The system according to claim 1, wherein: The transmitter (2) is a 2.4G transmitter, and the signal receiving host (3) is a 2.4G signal receiving host.

9. The system according to claim 2, wherein: The first microcontroller unit (22) is an STM32 single-chip microcomputer.

10. The system according to claim 5, wherein: The second microcontroller unit (333) is an STM32 single-chip microcomputer.

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