Reference processing module
By designing a reference processing module for multi-frequency clock signal generation, the problem of repeated design in the existing technology is solved, flexible frequency and power range support is achieved, the design and debugging workload is reduced, and the requirements of different projects are adapted.
Patent Information
- Application Number
- CN202422081756.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-08-27
AI Technical Summary
In the prior art, the reference processing module is redesigned each time according to different project needs, resulting in a large design workload and increased debugging workload. In addition, the input signal frequency is fixed, the frequency and power range are limited, and clock signals of different frequencies cannot be output.
A reference processing module was designed, which includes a clock submodule, a power control module, and a control communication module. It can generate clock signals of various frequencies (10MHz, 100MHz, 2.4GHz) and automatically switch the internal and external reference states through FPGA. It supports inputs with a wide frequency and power range, including 10MHz~400MHz frequency and -40~+15dBm power.
It realizes multi-frequency clock signal output, reduces the need for repeated design, improves design and debugging efficiency, supports flexible internal and external reference switching and wide frequency and power range, and adapts to different project requirements.
Smart Images
Figure CN223364144U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of communication engineering, in particular to a reference processing module. Background Art
[0002] Frequency synthesis modules all have reference clock requirements, and the reference processing module provides the reference clock for the frequency synthesis module. However, different projects have different requirements for reference clocks.
[0003] In the prior art, a reference processing module design must be performed each time according to the project, which increases the design workload. In addition, there are differences in the design layout each time, which ultimately increases the debugging workload.
[0004] The external reference input frequency is fixed, typically 100 MHz, and has a low input power range, typically -5 to +5 dBm. It can only output a fixed-frequency clock signal of 100 MHz. If a clock signal with a different frequency is required, a redesign is required. To address this issue, the present invention provides a reference processing module, comprising: a reference processing module for generating 10 MHz, 100 MHz, and 2.4 GHz clock signals; a power control module for generating voltages of +3.3 V, +5 V, and +5.5 V, and for controlling the module and reporting its status via an FPGA.
[0005] The structure of the prior art is as shown in the attached Figure 1 As shown in the figure, the 100MHz signal output by the external reference 100MHz clock source enters one input of the switch, and the 100MHz signal output by the internal 100MHz phase-locked crystal oscillator enters the other input of the switch. The output signal of the switch enters the input of the clock distribution component. The clock distribution component outputs multiple 100MHz clock signals, of which one 100MHz clock signal enters the dot-frequency clock source, and the remaining 100MHz clock signals are output externally. The dot-frequency clock source outputs a multiplied frequency signal. Utility Model Content
[0006] The utility model overcomes the defects in the prior art that clock sources need to be repeatedly designed according to different frequency synthesis modules, and the input signal frequency bandwidth is narrow and the power range is low, and provides a reference processing module.
[0007] The technical solution adopted in this utility model is:
[0008] A reference processing module, comprising:
[0009] A clock submodule, which is used to generate 10 MHz, 100 MHz, and 2.4 GHz clock signals;
[0010] A power control module having a control communication module, a power supply module, a connector, and an adapter; the power supply module is used to generate voltages of +3.3V, +5V, and +5.5V, and provide voltages to the clock submodule and the control communication module; the control communication module is connected to the clock submodule and is used to control the clock submodule and report its status.
[0011] Furthermore, the clock submodule includes:
[0012] Selector switch;
[0013] an internal reference module, the internal reference module being used to output a 10 MHz internal reference signal and transmit it to an input end of the selection switch;
[0014] an external reference module, the external reference module being used to output a 10 MHz external reference signal and transmit it to the other input end of the selection switch;
[0015] a 100 MHz signal generating module, wherein an input end of the 100 MHz signal generating module receives the signal output from the selection switch and outputs a 100 MHz signal;
[0016] A power divider A, wherein an input end of the power divider A receives the 100 MHz signal output by the 100 MHz signal generation module and divides the 100 MHz signal into two paths;
[0017] A power splitter B, wherein the input end of the power splitter B receives the 100 MHz signal output by the power splitter A and splits the 100 MHz signal into two paths;
[0018] A 100 MHz clock module, wherein the input end of the 100 MHz clock module receives a 100 MHz signal output by the power distributor A and outputs a 100 MHz clock signal externally;
[0019] A 10 MHz clock module, wherein the input end of the 10 MHz clock module receives a 100 MHz signal output by the power distributor B and outputs a 10 MHz clock signal externally;
[0020] A 2.4 GHz clock module, wherein the input end of the 2.4 GHz clock module receives a 100 MHz signal output by the power distributor B and outputs a 2.4 GHz clock signal to the outside.
[0021] Furthermore, the internal reference module includes:
[0022] An internal 10 MHz crystal oscillator is connected to an input end of the selection switch.
[0023] External reference modules include:
[0024] An AGC component, wherein the input end of the AGC component receives an external reference signal and outputs a constant power signal; a control pin of the AGC component is connected to the control communication module to report the locking status to the latter; and the AGC component is connected to the power supply module to provide voltage to the latter for the AGC component;
[0025] The frequency divider A, the input terminal A of the frequency divider receives the signal output by the AGC component; the frequency divider A is connected to the control communication module, and the latter controls the frequency division coefficient of the former;
[0026] The attenuator A, wherein the input end of the attenuator A receives the signal output by the frequency divider A;
[0027] The low-pass filter A, the input end of the low-pass filter A receives the signal output by the attenuator A.
[0028] Furthermore, the 100 MHz signal generation module includes:
[0029] a 100 MHz signal phase-locked loop, wherein an input end of the 100 MHz signal phase-locked loop receives the signal output by the selection switch, and the 100 MHz signal phase-locked loop outputs a 100 MHz signal; and a control pin of the 100 MHz signal phase-locked loop is connected to the control communication module, and the former feeds back the phase-locked state to the latter;
[0030] A low-pass filter B, wherein an input end of the low-pass filter B receives the signal output by the 100 MHz signal phase-locked loop.
[0031] an attenuator B, wherein an input end of the attenuator B receives a signal output by the low-pass filter B;
[0032] Amplifier A, wherein an input end of the amplifier A receives the signal output by the attenuator B.
[0033] Furthermore, the 100 MHz clock module includes:
[0034] an attenuator C, wherein an input end of the attenuator C receives the 100 MHz signal output by the power divider A;
[0035] A power divider C, wherein an input end of the power divider C receives the signal output by the attenuator C;
[0036] A power distributor D, wherein the input end of the attenuator D receives one channel of signal output by the attenuator C, and the attenuator D outputs two channels of 100 MHz clock signals;
[0037] A power distributor E, wherein the input end of the attenuator E receives the other signal output by the attenuator C, and the attenuator E outputs two 100 MHz clock signals to the outside.
[0038] Furthermore, the 10MHz clock module includes:
[0039] A frequency divider B, wherein the input end of the frequency divider B receives a 100 MHz signal output by the power divider B and outputs a 100 MHz signal; and a control pin of the frequency divider B is connected to the control communication module, and the control communication module controls the frequency division coefficient of the frequency divider B;
[0040] a low-pass filter C, wherein an input end of the low-pass filter C receives the signal output by the frequency divider B;
[0041] an attenuator D, wherein an input end of the attenuator D receives a signal output by the low-pass filter C;
[0042] an amplifier B, wherein an input end of the amplifier B receives the signal output by the attenuator D;
[0043] A power distributor F, wherein the input end of the power distributor F receives the signal output by the amplifier B, and the power distributor F outputs two 10 MHz clock signals to the outside.
[0044] Furthermore, the 2.4 GHz clock module includes:
[0045] an attenuator H, wherein an input end of the attenuator H receives a signal output by the power divider B;
[0046] A 2.4 GHz point frequency source component, wherein the input end of the 2.4 GHz point frequency source component receives the signal output by the attenuator H, and the 2.4 GHz point frequency source component outputs a 2.4 GHz signal; a control pin of the 2.4 GHz point frequency source component is connected to the control communication module to enter the phase-locked state of the latter;
[0047] an attenuator E, wherein an input end of the attenuator E receives a signal output by the 2.4 GHz point frequency source component;
[0048] an amplifier C, wherein an input end of the amplifier C receives the signal output by the attenuator E;
[0049] a low-pass filter D, wherein an input end of the low-pass filter D receives a signal output by the amplifier C;
[0050] A power divider G, wherein an input end of the power divider G receives the signal output by the low-pass filter D, and the power divider G outputs two 2.4 GHz signals;
[0051] an attenuator F, wherein an input end of the attenuator F receives a signal output by the power divider G;
[0052] A power divider H, wherein the input end of the power divider H receives the signal output by the attenuator F, and the power divider H outputs two 2.4 GHz clock signals externally;
[0053] Attenuator G, the input end of the attenuator G receives another signal output by the power divider G, and the attenuator G outputs a 2.4 GHz clock signal to the outside.
[0054] Furthermore, the power control module includes:
[0055] Connectors;
[0056] adapter; the signal output by the connector enters the adapter; the signal output by the adapter enters the connector;
[0057] A control communication module receives a signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; a signal output by the control communication module enters the adapter through a pair of transmitting differential lines TX_P and TX_N;
[0058] A power supply module, wherein the input end of the power supply module receives the +12V voltage output by the connector, and the output voltage of the power supply module enters the clock submodule and the control communication module, and is used to provide voltage to the clock submodule and the control communication module.
[0059] Furthermore, the control communication module includes:
[0060] 422 adapter, the adapter 422 receives the signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; the signal output by the adapter 422 enters the adapter through a pair of transmitting differential lines TX_P and TX_N;
[0061] FPGA, the FPGA receives the signal output by the 422 adapter through the receiving signal line RX; the signal output by the FPGA enters the 422 adapter through the transmitting signal line TX; the FPGA controls the frequency division coefficients of the frequency divider A and the frequency divider B, reads the locking status of the AGC component, the 100 MHz signal phase-locked loop, the locking status of the 2.4 GHz point frequency source component, and controls the switching of the selection switch; the IO pins of the FPGA are connected to the control pins of the controlled device, and the state of the corresponding device is controlled by controlling the high and low levels output by the FPGA to realize the control function.
[0062] Furthermore, the power supply module includes:
[0063] a DC power converter DCDC, wherein an input end of the DC power converter DCDC receives +12V input from the adapter, and the DC power converter DCDC outputs voltages of +3.3V, +5V, and +5.5V;
[0064] A low-dropout linear regulator LDO1, wherein the input end of the low-dropout linear regulator LDO1 receives the +12V voltage output by the DC power converter DCDC, and the low-dropout linear regulator LDO1 outputs a +3.3V voltage to provide voltage for the FPGA, all frequency dividers, and all attenuators;
[0065] A low-voltage-dropout linear regulator LDO2, wherein the input end of the low-voltage-dropout linear regulator LDO2 receives the +12V voltage output by the DC power converter DCDC, and the low-voltage-dropout linear regulator LDO2 outputs a +5V voltage to provide voltage for all amplifiers.
[0066] Furthermore, the models of the frequency divider A and the frequency divider B are AD9513; the model of the selection switch is SKY13286-359LF.
[0067] The beneficial effects of the utility model are:
[0068] It has multiple output reference clock paths and can simultaneously output multi-frequency clocks such as 100M, 10M, and 2.4G, with good phase noise indicators. There is no need to redesign the reference processing module for different projects. The application of the AD9513 divider makes the external reference input frequency range wider, and can achieve multi-point switching of the input frequency from 10M to 400M. The application of the AGC component widens the input power range to -40~+15dBm. The application of FPGA can automatically switch the internal and external reference states and report them. Both internal and external references can work, and the use is flexible and diverse without limitations. BRIEF DESCRIPTION OF THE DRAWINGS
[0069] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0070] Figure 1 It is a structural block diagram of the prior art reference processing module.
[0071] Figure 2 This is a structural block diagram of the detailed principle of the reference processing module.
[0072] Figure 3A structural block diagram of an embodiment of a reference processing module. DETAILED DESCRIPTION
[0073] The embodiments of the utility model are described in detail below with reference to the accompanying drawings.
[0074] In the prior art, a reference processing module design must be performed each time according to the project, which increases the design workload. In addition, there are differences in the design layout each time, which ultimately increases the debugging workload.
[0075] The external reference input frequency is fixed, usually 100 MHz, and the input power range is low, usually -5 to +5 dBm. It can only output a fixed-frequency clock signal of 100 MHz. If a clock signal with a different frequency is required, a redesign is required.
[0076] In order to unify design ideas, reduce the probability of errors, reduce unnecessary design and debugging work each time, and adapt to different project requirements, it was decided to develop and design a universal reference processing module.
[0077] In order to solve the above problems, this embodiment provides a reference processing module, the structure of which is as shown in the attached figure. Figure 2 shown.
[0078] Before introducing the embodiment, the composition and signal flow of each module of the reference processing module are first introduced.
[0079] The reference processing module in this embodiment includes:
[0080] Clock submodule, which is used to generate 10MHz, 100MHz, and 2.4GHz clock signals;
[0081] The power control module includes a control communication module, a power supply module, a connector, and an adapter. The power supply module is used to generate +3.3V, +5V, and +5.5V voltages and provide voltage to the clock submodule and the control communication module. The control communication module is connected to the clock submodule to control the clock submodule and report its status.
[0082] The clock submodule in this embodiment includes:
[0083] Selector switch;
[0084] An internal reference module, which is used to output a 10MHz internal reference signal and transmit it to one input end of the selection switch;
[0085] The external reference module is used to output a 10MHz external reference signal and transmit it to the other input end of the selection switch;
[0086] a 100 MHz signal generating module, wherein an input end of the 100 MHz signal generating module receives a signal output from the selection switch and outputs a 100 MHz signal;
[0087] Power divider A: The input end of power divider A receives the 100 MHz signal output by the 100 MHz signal generation module and divides the 100 MHz signal into two paths;
[0088] Power splitter B: The input end of power splitter B receives the 100MHz signal output by power splitter A and splits the 100MHz signal into two paths;
[0089] 100MHz clock module: The input end of the 100MHz clock module receives a 100MHz signal output from power distributor A and outputs a 100MHz clock signal to the outside.
[0090] 10MHz clock module: The input end of the 10MHz clock module receives a 100MHz signal output by power distributor B and outputs a 10MHz clock signal to the outside.
[0091] 2.4 GHz clock module: The input end of the 2.4 GHz clock module receives a 100 MHz signal output by power splitter B and outputs a 2.4 GHz clock signal.
[0092] The internal reference module in this embodiment includes:
[0093] Internal 10MHz crystal oscillator, the internal 10MHz crystal oscillator is connected to one input end of the selection switch.
[0094] External reference modules include:
[0095] AGC component: The input end of the AGC component receives an external reference signal and outputs a constant power signal; the control pin of the AGC component is connected to the control communication module to report the locking status to the latter; at the same time, the AGC component is connected to the power supply module to provide voltage to the AGC component;
[0096] Frequency divider A, the input terminal A of the frequency divider receives the signal output by the AGC component; the frequency divider A is connected to the control communication module, and the latter controls the frequency division coefficient of the former;
[0097] Attenuator A, where an input end of attenuator A receives a signal output by frequency divider A;
[0098] A low-pass filter A, wherein an input end of the low-pass filter A receives a signal output by the attenuator A;
[0099] The 100 MHz signal generation module in this embodiment includes:
[0100] 100MHz signal phase-locked loop, the input end of the 100MHz signal phase-locked loop receives the signal output by the selection switch, and the 100MHz signal phase-locked loop outputs a 100MHz signal; at the same time, the control pin of the 100MHz signal phase-locked loop is connected to the control communication module, and the former feeds back the phase-locked status to the latter;
[0101] Low-pass filter B, the input end of the low-pass filter B receives the signal output by the 100MHz signal phase-locked loop;
[0102] Attenuator B, where an input end of attenuator B receives a signal output by low-pass filter B;
[0103] Amplifier A, the input end of amplifier A receives the signal output by attenuator B;
[0104] The 100 MHz clock module in this embodiment includes:
[0105] Attenuator C, the input end of attenuator C receives the 100MHz signal output by power divider A;
[0106] A power divider C, wherein an input end of the power divider C receives a signal output by the attenuator C;
[0107] The power divider D and the input end of the attenuator D receive a signal output by the attenuator C, and the attenuator D outputs two 100MHz clock signals.
[0108] Power divider E, the input end of attenuator E receives the other signal output by attenuator C, and attenuator E outputs two 100MHz clock signals to the outside;
[0109] The 10 MHz clock module in this embodiment includes:
[0110] Frequency divider B: The input end of frequency divider B receives a 100MHz signal output by power divider B and outputs a 100MHz signal. At the same time, the control pin of frequency divider B is connected to the control communication module, which controls the frequency division coefficient of the former.
[0111] A low-pass filter C, wherein an input end of the low-pass filter C receives a signal output by the frequency divider B;
[0112] Attenuator D, where an input end of the attenuator D receives a signal output by the low-pass filter C;
[0113] Amplifier B, the input end of amplifier B receives the signal output by attenuator D;
[0114] Power divider F: The input end of the power divider F receives the signal output by the amplifier B, and the power divider F outputs two 10MHz clock signals to the outside;
[0115] The 2.4 GHz clock module in this embodiment includes:
[0116] Attenuator H, where an input end of the attenuator H receives a signal output by the power divider B;
[0117] 2.4GHz point frequency source component, the input end of the 2.4GHz point frequency source component receives the signal output by the attenuator H, and the 2.4GHz point frequency source component outputs a 2.4GHz signal; the control pin of the 2.4GHz point frequency source component is connected to the control communication module, and the phase-locked state enters the latter;
[0118] Attenuator E, the input end of attenuator E receives the signal output by the 2.4 GHz point frequency source component;
[0119] Amplifier C, where an input terminal of the amplifier C receives a signal output by the attenuator E;
[0120] A low-pass filter D, wherein an input end of the low-pass filter D receives a signal output by the amplifier C;
[0121] Power divider G, the input end of power divider G receives the signal output by low-pass filter D, and power divider G outputs two 2.4GHz signals;
[0122] Attenuator F, the input end of attenuator F receives a signal output by power divider G;
[0123] Power divider H: The input end of the power divider H receives the signal output by the attenuator F, and the power divider H outputs two 2.4 GHz clock signals.
[0124] Attenuator G: The input end of attenuator G receives another signal output by power divider G, and attenuator G outputs a 2.4 GHz clock signal.
[0125] The power control module in this embodiment includes:
[0126] Connectors;
[0127] Adapter; the signal output from the connector enters the adapter; the signal output from the adapter enters the connector;
[0128] Control the communication module, the control communication module receives the signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; the control communication module outputs the signal into the adapter through a pair of transmitting differential lines TX_P and TX_N;
[0129] The power supply module receives the +12V voltage output by the connector at its input end, and the output voltage of the power supply module enters the clock submodule and the control communication module to provide voltage to the clock submodule and the control communication module.
[0130] The control and communication module in this embodiment includes:
[0131] 422 adapter, the 422 adapter receives the signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; the signal output by the 422 adapter enters the adapter through a pair of transmitting differential lines TX_P and TX_N;
[0132] FPGA, FPGA receives the signal output by the 422 adapter through the receive signal line RX; the signal output by the FPGA enters the 422 adapter through the transmit signal line TX; the FPGA controls the frequency division coefficients of divider A and divider B, reads the lock status of the AGC component, the 100MHz signal phase-locked loop, the lock status of the 2.4GHz point frequency source component, and controls the switching of the selection switch; the FPGA's IO pins are connected to the control pins of the controlled device, and the state of the corresponding device is controlled by controlling the high and low levels of the FPGA output to achieve the control function;
[0133] The power supply module in this embodiment includes:
[0134] A DC power converter DCDC, wherein an input end of the DC power converter DCDC receives +12V input from the adapter, and the DC power converter DCDC outputs voltages of +3.3V, +5V, and +5.5V;
[0135] Low-voltage-dropout linear regulator LDO1: The input end of the low-voltage-dropout linear regulator LDO1 receives the +12V voltage output by the DC power converter DCDC, and the low-voltage-dropout linear regulator LDO1 outputs a +3.3V voltage to power the FPGA, all frequency dividers, and all attenuators;
[0136] The low voltage dropout linear regulator LDO2 receives a +12V voltage output by a DC power converter DCDC at its input end, and outputs a +5V voltage to power all amplifiers.
[0137] The models of the frequency divider A and the frequency divider B in this embodiment are AD9513; the model of the selection switch is SKY13286-359LF.
[0138] This embodiment adds external devices and modules based on the complete structure of the reference processing module: signal generator, power module, host computer and frequency synthesis module, as shown in the attached figure. Figure 3 shown.
[0139] The signal generator provides a 200MHz external reference signal, which enters the input of the AGC component. The power module provides +12V to the DC power converter (DCDC) via a connector and adapter. The host computer, acting as the master device, communicates with the control communication module of the power control module via a connector and adapter. The clock signal output by the reference processing module is transmitted to the frequency synthesis module, which then uses the clock signal.
[0140] After introducing the composition and signal flow of each module of the reference processing module, the principle and implementation method of each function of the reference embodiment are introduced below.
[0141] In this embodiment, when the user controls or checks the status of the reference processing module, the host computer and the FPGA need to communicate.
[0142] When the host computer sends a command to the FPGA, the command signal enters the FPGA through the connector J30J-9ZKP, the adapter, and the 422 adapter MAX3077E.
[0143] The communication protocol of the command includes frame header, address, data byte, check byte and frame trailer. The 422 adapter MAX3077E is a serial RS422 interface with a baud rate of 1Mbps.
[0144] When FPGA sends a command to the host computer, the command signal is sent to the host computer through the 422 adapter, adapter, and connector J30J-9ZKP.
[0145] In this embodiment, the user can switch between internal and external reference inputs and view the current status, i.e., internal reference or external reference. The specific method is as follows, as shown in the attached Figure 3 As shown:
[0146] The user sends a command through the host computer. The command reaches the FPGA, where an IO pin is connected to the control interface of the SKY13286-359LF selector switch. The SKY13286-359LF selector switch is a single-pole, double-throw (SPDT) switch. One input is connected to the internal reference module, the other to the external reference module, and the output is connected to a 100MHz phase-locked loop (PLL). The FPGA controls the switch position by changing the voltage level on the IO pin, thereby switching between internal and external reference inputs. The FPGA then sends internal and external reference status indication signals to the host computer, allowing real-time reporting of the internal and external reference status.
[0147] In this embodiment, the user can check the locking status of the 100MHz signal phase-locked loop. The specific method is as follows, as shown in the attached Figure 3 As shown:
[0148] The user sends instructions through the host computer, and the instructions reach the FPGA. One of the FPGA's IO pins is connected to the lock indication pin LD of the 100MHz signal phase-locked loop. When the lock is successful, the 100MHz signal phase-locked loop outputs a 100MHz signal, and the lock indication pin LD is high. When the lock fails, it is low. The level signal is transmitted to the FPGA through the IO pin, and the FPGA transmits the instruction to the host computer.
[0149] In this embodiment, the user can check the locking status of the 2.4GHz point frequency source component in the same way as checking the locking status of the 100MHz signal phase-locked loop, as shown in the attached figure. Figure 3 shown.
[0150] Principle of the external reference module: In this embodiment, the signal generator outputs a 200MHz, 10dBm signal to enter the AGC component. This AGC component does not change the signal frequency, but only changes the power. It outputs a 200MHz, 0dBm signal to enter the frequency divider AD9513. After frequency division, AD9513 outputs a 10MHz, 0dBm signal, which is attenuated and filtered and enters the selection switch SKY13286-359LF. AD9513 has 6 control pins connected to 6 FPGA IO pins. The user sends instructions to the FPGA through the host computer. The FPGA parses the instructions and changes the IO level to control the frequency division coefficient of the AD9513. When the AGC component changes the power, its STAT interface sends the locking status to the FPGA through the FPGA's IO pin. A high level of STAT indicates that the locking is successful, that is, a 0dBm power signal is output; a low level of STAT indicates that the locking fails, that is, no 0dBm power signal is output, as shown in the attached figure. Figure 3 shown.
[0151] The principle of the 100MHz signal generation module: The signal output by the selection switch SKY13286-359LF enters the 100MHz signal phase-locked loop, which outputs a 100MHz signal, which is then filtered, attenuated, amplified, and then output to the power divider A.
[0152] The principle of the 100MHz clock module is as follows: After entering power splitter A, the 100MHz signal is divided into two 100MHz signals. One signal passes through attenuator C and enters power splitter C to be divided into two 100MHz signals. The two 100MHz signals enter power splitter D and power splitter E respectively. Power splitter D and power splitter E each output two 100MHz signals. The 100MHz signal generation module outputs a total of four 100MHz clock signals that enter the frequency synthesizer module. Power splitter E is a reserved port for compatible design. It can be expanded to output two 100MHz clock signals according to project requirements in the future. Figure 3 shown.
[0153] The principle of the 10MHz clock module: the other signal output by power divider A enters power divider B, the 100MHz signal output by power divider B enters a frequency divider AD9513, the frequency divider AD9513 divides the frequency by 10 and outputs a 10MHz signal, which is filtered, attenuated, and amplified before entering power divider F. Power divider F outputs two 10MHz clock signals which enter the frequency synthesizer module, as shown in the attached figure. Figure 3 shown.
[0154] The principle of the 2.4GHz clock module: The other 100MHz signal output by power divider B enters the 2.4GHz point frequency source component after 7dB attenuation. The 2.4GHz point frequency source component outputs a 2.4GHz signal, which enters the power divider G after 0dB attenuation, amplification, and filtering. Power divider G outputs two 2.4GHz signals, one of which is output as a 2.4GHz clock signal after 3dB attenuation and enters the frequency synthesizer module. The other is attenuated by 0dB and enters the power divider H. The power divider H outputs three 2.4GHz clock signals and enters the frequency synthesizer module, as shown in the attached figure. Figure 3 shown.
Claims
1. A reference processing module, characterized in that: include: A clock submodule, which is used to generate 10 MHz, 100 MHz, and 2.4 GHz clock signals; A power control module having a control communication module, a power supply module, a connector, and an adapter; the power supply module is used to generate voltages of +3.3V, +5V, and +5.5V, and provide voltages to the clock submodule and the control communication module; the control communication module is connected to the clock submodule and is used to control the clock submodule and report its status.
2. The reference processing module according to claim 1, wherein: The clock submodule includes: Selector switch; an internal reference module, the internal reference module being used to output a 10 MHz internal reference signal and transmit it to an input end of the selection switch; an external reference module, the external reference module being used to output a 10 MHz external reference signal and transmit it to the other input end of the selection switch; a 100 MHz signal generating module, wherein an input end of the 100 MHz signal generating module receives the signal output from the selection switch and outputs a 100 MHz signal; A power divider A, wherein an input end of the power divider A receives the 100 MHz signal output by the 100 MHz signal generation module and divides the 100 MHz signal into two paths; A power splitter B, wherein the input end of the power splitter B receives the 100 MHz signal output by the power splitter A and splits the 100 MHz signal into two paths; A 100 MHz clock module, wherein the input end of the 100 MHz clock module receives a 100 MHz signal output by the power distributor A and outputs a 100 MHz clock signal externally; A 10 MHz clock module, wherein the input end of the 10 MHz clock module receives a 100 MHz signal output by the power distributor B and outputs a 10 MHz clock signal externally; A 2.4 GHz clock module, wherein the input end of the 2.4 GHz clock module receives a 100 MHz signal output by the power distributor B and outputs a 2.4 GHz clock signal to the outside.
3. The reference processing module according to claim 2, wherein: The internal reference module includes: an internal 10 MHz crystal oscillator connected to an input terminal of the selection switch; The external reference module includes: An AGC component, wherein the input end of the AGC component receives an external reference signal and outputs a constant power signal; a control pin of the AGC component is connected to the control communication module to report the locking status to the latter; and the AGC component is connected to the power supply module to provide voltage to the latter for the AGC component; A frequency divider A, wherein an input terminal A of the frequency divider receives a signal output by the AGC component; the frequency divider A is connected to the control communication module, and the latter controls the frequency division coefficient of the former; an attenuator A, wherein an input end of the attenuator A receives the signal output by the frequency divider A; A low-pass filter A, wherein an input end of the low-pass filter A receives the signal output by the attenuator A.
4. The reference processing module according to claim 3, wherein: The 100MHz signal generation module includes: a 100 MHz signal phase-locked loop, wherein an input end of the 100 MHz signal phase-locked loop receives the signal output by the selection switch, and the 100 MHz signal phase-locked loop outputs a 100 MHz signal; and a control pin of the 100 MHz signal phase-locked loop is connected to the control communication module, and the former feeds back the phase-locked state to the latter; A low-pass filter B, wherein an input end of the low-pass filter B receives a signal output by the 100 MHz signal phase-locked loop; an attenuator B, wherein an input end of the attenuator B receives a signal output by the low-pass filter B; Amplifier A, wherein an input end of the amplifier A receives the signal output by the attenuator B.
5. The reference processing module according to claim 4, characterized in that The 100MHz clock module includes: an attenuator C, wherein an input end of the attenuator C receives the 100 MHz signal output by the power divider A; A power divider C, wherein an input end of the power divider C receives the signal output by the attenuator C; A power distributor D, wherein the input end of the attenuator D receives a signal output by the attenuator C, and the attenuator D outputs two 100 MHz clock signals externally; A power distributor E, wherein the input end of the attenuator E receives the other signal output by the attenuator C, and the attenuator E outputs two 100 MHz clock signals to the outside; The 10MHz clock module includes: A frequency divider B, wherein the input end of the frequency divider B receives a 100 MHz signal output by the power divider B and outputs a 100 MHz signal; and a control pin of the frequency divider B is connected to the control communication module, and the latter controls the frequency division coefficient of the former; a low-pass filter C, wherein an input end of the low-pass filter C receives the signal output by the frequency divider B; an attenuator D, wherein an input end of the attenuator D receives a signal output by the low-pass filter C; an amplifier B, wherein an input end of the amplifier B receives the signal output by the attenuator D; A power distributor F, wherein the input end of the power distributor F receives the signal output by the amplifier B, and the power distributor F outputs two 10 MHz clock signals to the outside.
6. The reference processing module according to claim 5, characterized in that: The 2.4 GHz clock module includes: an attenuator H, wherein an input end of the attenuator H receives a signal output by the power divider B; A 2.4 GHz point frequency source component, wherein the input end of the 2.4 GHz point frequency source component receives the signal output by the attenuator H, and the 2.4 GHz point frequency source component outputs a 2.4 GHz signal; a control pin of the 2.4 GHz point frequency source component is connected to the control communication module to enter the phase-locked state of the latter; an attenuator E, wherein an input end of the attenuator E receives a signal output by the 2.4 GHz point frequency source component; an amplifier C, wherein an input end of the amplifier C receives the signal output by the attenuator E; a low-pass filter D, wherein an input end of the low-pass filter D receives a signal output by the amplifier C; A power divider G, wherein an input end of the power divider G receives the signal output by the low-pass filter D, and the power divider G outputs two 2.4 GHz signals; an attenuator F, wherein an input end of the attenuator F receives a signal output by the power divider G; A power divider H, wherein the input end of the power divider H receives the signal output by the attenuator F, and the power divider H outputs two 2.4 GHz clock signals externally; Attenuator G, the input end of the attenuator G receives another signal output by the power divider G, and the attenuator G outputs a 2.4 GHz clock signal to the outside.
7. The reference processing module according to claim 6, characterized in that: The power control module includes: Connectors; an adapter, wherein the signal output by the connector enters the adapter; and the signal output by the adapter enters the connector; A control communication module, wherein the control communication module receives a signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; the signal output by the control communication module enters the adapter through a pair of transmitting differential lines TX_P and TX_N; A power supply module, wherein the input end of the power supply module receives the +12V voltage output by the connector, and the output voltage of the power supply module enters the clock submodule and the control communication module, and is used to provide voltage to the clock submodule and the control communication module.
8. The reference processing module according to claim 7, wherein: The control communication module includes: 422 adapter, the adapter 422 receives the signal output by the adapter through a pair of receiving differential lines RX_P and RX_N; the signal output by the adapter 422 enters the adapter through a pair of transmitting differential lines TX_P and TX_N; FPGA, the FPGA receives the signal output by the 422 adapter through the receiving signal line RX; the signal output by the FPGA enters the 422 adapter through the transmitting signal line TX; the FPGA controls the frequency division coefficients of the frequency divider A and the frequency divider B, reads the locking status of the AGC component, the 100 MHz signal phase-locked loop, the locking status of the 2.4 GHz point frequency source component, and controls the switching of the selection switch; the IO pins of the FPGA are connected to the control pins of the controlled device, and the state of the corresponding device is controlled by controlling the high and low levels output by the FPGA to realize the control function.
9. The reference processing module according to claim 8, characterized in that: The power supply module includes: a DC power converter DCDC, wherein an input end of the DC power converter DCDC receives +12V input from the adapter, and the DC power converter DCDC outputs voltages of +3.3V, +5V, and +5.5V; A low-dropout linear regulator LDO1, wherein the input end of the low-dropout linear regulator LDO1 receives the +12V voltage output by the DC power converter DCDC, and the low-dropout linear regulator LDO1 outputs a +3.3V voltage to provide voltage for the FPGA, all frequency dividers, and all attenuators; A low-voltage-dropout linear regulator LDO2, wherein the input end of the low-voltage-dropout linear regulator LDO2 receives the +12V voltage output by the DC power converter DCDC, and the low-voltage-dropout linear regulator LDO2 outputs a +5V voltage to provide voltage for all amplifiers.
10. The reference processing module according to claim 8, wherein: The model of the frequency divider A and the frequency divider B is AD9513; The model of the selector switch is SKY13286-359LF.