Power MOS (Metal Oxide Semiconductor) capable of realizing open circuit

Abstract

The utility model provides a power MOS capable of realizing open circuit. The power MOS comprises a chip wafer; a grid electrode pin, a source electrode pin and a drain electrode pin; the drain electrode pin is connected with the chip wafer through a plurality of first bonding wires; and the source electrode pin is connected with the chip wafer through a plurality of second bonding wires. According to the power MOS capable of realizing the open circuit, the specific fusing current value of the MOS can be simply controlled, the fusing characteristic of the power MOS is increased, and the damage of a battery and a circuit board caused by continuous short circuit of a main loop can be effectively prevented; and meanwhile, the manufacturing process of the MOS can be simplified.

Description

Technical Field

[0001] The present invention relates to a power semiconductor product, in particular to a power MOS which can realize disconnection in a failure state. Background Art

[0002] MOS transistors (Metal Oxide Semiconductor Field Effect Transistor) are metal oxide semiconductor field effect transistors (MOSFETs), which are insulated gate type field effect transistors. MOSFETs that have undergone some performance enhancements and are used in power control circuits are called power MOSFETs.

[0003] In some high-power switching circuits, MOS transistors are required to control the on / off state of the circuit. However, in actual use, the MOS transistor may fail due to breakdown due to certain reasons. In this case, a short circuit usually occurs inside the MOS transistor, resulting in excessive internal short-circuit current, which causes continuous and intense heating inside the MOS transistor, causing the MOS transistor to burn out. In severe cases, it may even cause open flames, posing a safety hazard. Especially when the MOS transistor is installed on a corresponding printed circuit board and forms a complete circuit system with other components, the combustion of the MOS transistor is likely to cause the combustion of other components in the circuit system, paralyzing the entire circuit system. Utility Model Content

[0004] To enable a power MOS to be disconnected in a failure state and to prevent a short circuit due to excessive current flowing through it, thereby improving the safety of the power MOS when used in a printed circuit board, the present invention provides a power MOS capable of disconnecting, comprising: a chip wafer; a gate pin, a source pin, and a drain pin; the drain pin is connected to the chip wafer via a plurality of first bonding wires; and the source pin is connected to the chip wafer via a plurality of second bonding wires.

[0005] Furthermore, the number of the first bonding wires is less than the number of the second bonding wires.

[0006] Furthermore, the number of the second bonding wires is twice the number of the first bonding wires.

[0007] Furthermore, the diameter of the first bonding wire is 1.5 mil-2.5 mil.

[0008] Furthermore, the number of the first bonding wires is 16.

[0009] Furthermore, the first bonding wire and the second bonding wire have the same structure.

[0010] Furthermore, the gate pin is connected to the chip wafer via a bonding wire.

[0011] Furthermore, the device further comprises a ceramic package that encapsulates the first bonding wire, the second bonding wire, the chip wafer, the source pin, the gate pin, and the drain pin in a sealed space. Furthermore, the device further comprises a thermosetting plastic package that encapsulates the first bonding wire, the second bonding wire, the chip wafer, the source pin, the gate pin, and the drain pin in a sealed space.

[0012] The power MOS capable of achieving circuit breaking of the present invention can simply control the specific fusing current value of the MOS, increase the fusing characteristics of the power MOS, and effectively prevent damage to the battery and circuit board caused by a continuous short circuit of the main circuit; at the same time, the manufacturing process of the MOS can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of a power MOS capable of achieving circuit breaking in the present utility model. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0015] like Figure 1 As shown, the present invention provides a power MOS 10 capable of achieving a circuit breaker, comprising: a chip wafer 20; a gate pin 101, a source pin 102, and a drain pin 103; a plurality of first bonding wires 106 connecting the drain pin 103 to the chip wafer 20; a plurality of second bonding wires 105 connecting the source pin 102 to the chip wafer 20; and a packaging structure 30 that seals the chip wafer 20, source pin 102, drain pin 103, and gate pin 101 in a sealed space.

[0016] Because the currents flowing through the drain, gate, and source pins of a power MOS transistor differ in magnitude when used in an actual circuit, the gate, drain, and source pins can actually withstand different overcurrent capacities. Therefore, in the design of the power MOS transistor, this embodiment aims to control the overcurrent capacities of the source and drain electrodes by controlling the number of bonding wires in the main circuit, thereby controlling the location of the fuse, ensuring that the drain electrode blows first. This allows the power MOS transistor 10 to withstand an appropriate current in the circuit, achieving a disconnection function at a predetermined current. The number of bonding wires can be adjusted based on the specific application of the power MOS transistor, allowing for the design of different power MOS transistors, increasing the degree of freedom in power MOS design, and simplifying the power MOS transistor manufacturing process.

[0017] In the power MOS design process of this embodiment, assuming that the current flowing through the bonding wire is I, the resistivity of the bonding wire material is ρ, the bonding wire length is L, the cross-sectional area of ​​a single bonding wire is S, and the bonding wire power-on time is t, the heat Q1 generated by the bonding wire is:

[0018]

[0019] Assume that the comprehensive heat dissipation coefficient of the bond wire surface is Kt, which is the combination of heat convection, heat conduction, and heat radiation; the heat dissipation area of ​​the bond wire is A, which is equal to the surface area of ​​the wire without considering the two end faces, that is, A = ML, where M is the cross-sectional perimeter of the bond wire, L is the wire length, t is the wire power-on time, and τ is the temperature rise. Therefore, the heat Q2 dissipated by the bond wire to the environment is:

[0020] Q2=P2t=K t A τ t=K t ML τ t

[0021] Where P = K t A τ It is Newton's heat dissipation formula, or Newton's law of cooling formula.

[0022] When the surface temperature of the energized bonding wire stabilizes, Q1 = Q2, that is:

[0023]

[0024] From the above formula we can get:

[0025]

[0026] Therefore, in this implementation, the cross-sectional area of ​​the power MOS bonding wire is proportional to the square of the current flowing through the bonding wire. When the number of bonding wires increases to n, the cross-sectional area of ​​the bonding wire passing through the same electrode becomes ns, and the total current flowing through n bonding wires becomes Right now

[0027]

[0028] Therefore, when the number of bonding wires between the same electrode and the chip increases, the total cross-sectional area of ​​the bonding wires becomes larger, and the current allowed to flow through the bonding wires becomes higher. When the current flowing through the bonding wires exceeds the current that the bonding wires can withstand, the heat generated by the bonding wires is greater than the heat dissipated by the bonding wires to the environment. Within a certain period of time, when the heat accumulated on the bonding wires makes the temperature greater than the melting point of the bonding wires, the bonding wires will melt.

[0029] like Figure 1 As shown, in the actual design of the power MOS in this embodiment, considering that under normal circumstances, the power MOS needs to refer to the voltage between the gate and the source to control the on and off of the MOS, when the MOS fails, the drain end bonding wire needs to be fused first, so the number of drain bonding wires is smaller than the number of source bonding wires. In this embodiment, the specific fuse threshold of the drain end bonding first is mainly calculated and designed according to the following steps:

[0030] A. Assuming that the bonding wire in this embodiment is copper wire, with a length of L = 1 mm, a diameter of D = 0.0254 mm (1 mil), and a copper density of ρ = 8.92 mg / mm, the mass G of the copper wire is:

[0031] G=L×π(D / 2)^2×ρ≈0.001438mg

[0032] The mass of 3 copper wires is 0.0045mg. The temperature is raised from t1 = 25℃ to t2 = 1084℃ (melting point). The specific heat C of copper is known to be 390mJ / mg.℃. The required heat Q is: Q = G × C × (t2-t1) = 659.76mJ

[0033] It takes 659.76 mJ of heat to melt a bonding wire with a diameter of 1 mil.

[0034] B. At 20°C, the copper wire is 1 mm long and 0.0254 mm in diameter. The copper resistivity is ρ. The copper wire resistance value R = resistivity (length / cross-sectional area) = 0.01724 (0.001 / π(0.0254 / 2)^2) ≈ 0.035Ω

[0035] Assume that when I = 1A, the heat loss power P at 20°C is p = i^2R = 0.035W = 35mJ / s;

[0036] At 200°C, P≈50mJ / s; if it increases by 100mJ / s, the time required for the bond wire to reach the melting heat is T=659.76mJ / P≈3 to 8 seconds (taking into account heat dissipation and resistivity increase).

[0037] Therefore, for a copper wire with a length of 1mm and a diameter of 0.0254mm, when the overcurrent reaches 1A, the overcurrent heat loss within 3 to 8 seconds will cause it to melt. Therefore, in order to improve the overcurrent capability of the power MOS and protect the power MOS from switching on and off in a timely manner under overcurrent conditions, according to the previous calculations and derivations.

[0038] In this embodiment, the power carrying current is increased by changing the number and diameter of the bonding wires. To this end, we conducted a series of experiments, calculated and measured the corresponding power MOS fuse current according to the number of power MOS bonding wires. The following are the specific test values ​​we conducted:

[0039]

[0040] Through the above experiments, it can be seen that the theoretical fusing current of the power MOS composed of multiple bonding wires is basically consistent with the actual fusing current, and the actual fusing current is slightly larger than the theoretical fusing current. The power MOS composed of multiple bonding wires in this embodiment can be applied to high-current power circuits, which can more conveniently control the on-off of the circuit and have the function of presenting circuit-breaking protection in the event of failure. When it is necessary to use the power MOS in a high-power circuit, the carrying current of the power MOS can be increased by increasing the number of bonding wires between the drain pin and the chip wafer; when the power MOS is needed in a circuit with lower power, the number of bonding wires between the drain pin and the chip wafer can be reduced to reduce the carrying current of the power MOS. Therefore, by adopting the power of the present invention, the specific fusing current value can be simply controlled by changing the number of drain bonding wires, thereby increasing the fusing characteristics of the power MOS, and effectively preventing damage to the battery and circuit board caused by continuous short circuit of the main circuit.

[0041] In this embodiment, the number of source bonding wires is greater than the number of drain bonding wires, preferably twice the number of source bonding wires. This configuration ensures that the MOS transistor disconnects at the drain first when carrying excessive current. Furthermore, the bonding wire diameter is preferably 1.5 mil to 2.5 mil, allowing the power MOS transistor to carry higher currents in the circuit and ensuring stable performance.

[0042] When it is necessary to use a power MOS in a circuit greater than 10A, the number of bonding wires between the wafer and the gate pin of the power MOS is preferably set to 16. At the same time, in order to simplify the production process of the power MOS and improve the efficiency of the power MOS during the manufacturing process, the source bonding wire and the gate bonding wire are preferably set to the same structure. At the same time, the overcurrent between the gate and the chip wafer is generally very small, so the gate pin and the chip wafer can be connected by a single bonding wire, and there is no need to set up multiple bonding wires. At the same time, in order to further improve the safety performance of the power MOS, this embodiment preferably uses ceramic packaging for the power MOS, and encapsulates the chip wafer 20 and each pin outside the ceramic substrate. The primary reason for using ceramic in this embodiment is its high thermal conductivity. Heat generated by the various devices within the MOS transistor can be quickly dissipated through the ceramic packaging material. As a highly conductive material, ceramic protects the chip wafer from thermal damage. Secondly, the thermal expansion coefficients of the ceramic material and the chip material match. Since the chip is typically mounted directly on the packaging substrate, this matching thermal expansion coefficient reduces thermal stress on the chip and improves the reliability of the devices within the MOS transistor. Furthermore, ceramic materials offer excellent heat resistance, meeting the high-temperature operating requirements of power devices and exhibiting excellent thermal stability. Finally, ceramic materials also offer excellent insulation properties and high mechanical strength, meeting the strength requirements of device processing, packaging, and application. They are also reasonably priced and suitable for large-scale production and application. The ceramic packaging in this embodiment is hermetic, primarily made from materials such as Al2O3, AlN, BeO, and mullite. It exhibits advantages such as good moisture resistance, high mechanical strength, a low thermal expansion coefficient, and high thermal conductivity. While ceramic packaging is preferred in this embodiment, plastic packaging can alternatively be used, such as thermosetting plastics including phenolic, polyester, epoxy, and silicone. Plastic packaging also has the advantages of low price, light weight and good insulation performance.

[0043] In summary, the power MOS of the present invention can adjust the appropriate MOS overcurrent capacity based on the number of bonding wires, effectively preventing the MOS from melting due to heat accumulation caused by overcurrent. In a failed state, the MOS short-circuit, thus preventing long-term short circuits and spontaneous combustion. This automatically disconnects the MOS circuit when overcurrent occurs, improving the safety performance of the power MOS. Furthermore, the present invention can change the actual current capacity of the MOS by simply changing the number of bonding wires, simplifying the manufacturing process of the power MOS.

[0044] The above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention and are not intended to limit the implementation methods of the present invention. A person skilled in the art will be able to make other variations or modifications based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A power MOS capable of realizing circuit breaking, comprising: chip wafers; Gate pin, source pin, drain pin; It is characterized in that the drain pin is connected to the chip wafer through multiple first bonding wires; the source pin is connected to the chip wafer through multiple second bonding wires; the number of the first bonding wires is less than the number of the second bonding wires.

2. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The number of the second bonding wires is twice the number of the first bonding wires.

3. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The diameter of the first bonding wire is 1.5 mil-2.5 mil.

4. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The number of the first bonding wires is 16.

5. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The first bonding wire and the second bonding wire have the same structure.

6. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The gate pin is connected to the chip wafer via a bonding wire.

7. The power MOS capable of realizing circuit breaking according to claim 1, wherein: It also includes a ceramic package, which packages the first bonding wire, the second bonding wire, the chip wafer, the source pin, the gate pin and the drain pin in a closed space.

8. The power MOS capable of realizing circuit breaking according to claim 1, wherein: The invention also includes a thermosetting plastic package which can encapsulate the first bonding wire, the second bonding wire, the chip wafer, the source pin, the gate pin and the drain pin in a closed space.

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