SiC power MOSFET device

Abstract

The utility model relates to the technical field of power semiconductor devices, in particular to a SiC power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, the cellular structure of which sequentially comprises a substrate, an N-epitaxial layer, a polysilicon gate layer, an isolating layer and a metal layer from bottom to top, two bilaterally symmetrical Pwell layers are arranged in the surface of the N-epitaxial layer; the N + layer is arranged on the Pwell layer; the P + layer is arranged on the N + layer; the surface of the N-epitaxial layer is internally provided with an alternating structure of a cross section A and a cross section B; the structure of the section A is as follows: the boundaries of the opposite sides of the two pwell layers are in the shapes of arcs bent inwards and straight bottom edge boundaries connected with the arcs; the structure of the section B is as follows: the boundaries of the two pwell layers are arc-shaped which are bent inwards; groove structures are arranged on the two sides of the cellular structure. The device has a double-section alternating structure, so that the path of hole current passing through the lower part of the source region can be shortened, and the dynamic latch-up resistance of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductor devices, in particular to a SiC power MOSFET device. Background Art

[0002] To further enhance device performance at high voltages and high powers and overcome the theoretical limitations of silicon, third-generation semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), have attracted widespread attention. They can achieve excellent device performance over a wide temperature range and are considered an ideal alternative to existing silicon materials in power devices. SiC, a Group IV-IV compound semiconductor material, has a breakdown electric field ten times that of silicon and a thermal conductivity almost three times that of silicon. The wider band gap, higher thermal conductivity, and larger critical breakdown electric field enable SiC power devices to operate at higher temperatures and achieve higher current densities and blocking voltages. High saturation drift velocity and mobility can increase the switching frequency of the device.

[0003] Silicon carbide (SiC) power devices include diodes, junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs). SiC power MOSFETs have attracted widespread attention due to their high voltage blocking capability, high-temperature operation, and low on-resistance. Potential technical challenges for these devices include improving reliability and stability, reducing manufacturing costs, and optimizing performance.

[0004] Currently, dynamic latch-up is a failure mode in SiC MOSFET power semiconductor devices that usually occurs during the device's shutdown process. When the device attempts to shut down, if the parasitic NPN transistor (formed by the source, drain, and substrate of the MOSFET) accidentally turns on, current will continue to flow, making the device unable to successfully shut down. In order to increase the device (the cell structure of the SiC MOSFET power semiconductor device in the prior art is as follows Figure 1As shown in the figure (200 - epitaxial layer, 300 - Pwell layer, 400 - N+ layer, 600 - polysilicon gate layer, 700 - isolation layer; the dotted arrows indicate the path of hole current flow), dynamic latch-up resistance is typically achieved by implanting concentrated boron under the source region to reduce the lateral resistance during the turn-off process. (Lateral resistance refers to the resistance encountered by current flowing laterally between the source and drain regions of a device. By implanting concentrated boron under the source region, the resistance of this region can be reduced, thereby reducing the resistance encountered by hole current supplied by the p-type region flowing through this region during the turn-off process.) This prevents hole current from flowing through the lateral resistance and generating a voltage drop (or potential difference) higher than the turn-on voltage of the NPN parasitic transistor. When the device is turned off, if the lateral resistance is high, the hole current flowing through this resistance will generate a large voltage drop. In other words, if this voltage drop is large enough, it may exceed the turn-on voltage of the parasitic NPN transistor, causing the transistor to turn on and triggering dynamic latch-up. Therefore, by reducing the lateral resistance, this voltage drop can be reduced, preventing the parasitic transistor from turning on, and thus improving the device's resistance to dynamic latch-up. However, when activated, the injected concentrated boron diffuses into the channel region of the power semiconductor device, causing the device's voltage to increase. In addition, because the hole current has a long path under the N+ layer, the existing structure has limited ability to improve dynamic latch-up resistance. Utility Model Content

[0005] To further improve the dynamic latch-up resistance of SiC MOSFET power semiconductor devices, a SiC power MOSFET device is provided. The device structure of this utility model has a dual-cross-section alternating structure. This structure can shorten the path of hole current passing under the source region, thereby improving the device's dynamic latch-up resistance.

[0006] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] A SiC power MOSFET device, wherein the cell structure of the device comprises, from bottom to top, an N++-type SiC substrate, an N-epitaxial layer, a polysilicon gate layer, an isolation layer, and a metal layer;

[0008] Two bilaterally symmetrical Pwell layers are provided on the surface of the N- epitaxial layer, with a JFET region formed between the two Pwell layers; an N+ layer is provided on the Pwell layer, and a P+ layer is provided on the N+ layer;

[0009] The surface of the N-epitaxial layer has an alternating structure of cross sections A and B;

[0010] The structure of the cross section A: the cross section of the JFET region is a trapezoidal shape that is narrow at the top and wide at the bottom, and the two opposite side boundaries of the pwell layers are both in the shape of an arc that bends inward, and have a straight bottom edge connected to the arc;

[0011] The structure of the cross section B: the boundaries of the two pwell layers are both in an inwardly curved arc;

[0012] Both sides of the cellular structure have groove structures.

[0013] Furthermore, in the structure of the cross section A: the Pwell layer wraps the N+ layer and the P+ layer, and the boundary between the P+ layer and the N+ layer forms two stacked squares;

[0014] In the structure of the cross section B, the Pwell layer wraps the N+ layer and the P+ layer, the boundary between the P+ layer and the N+ layer is arc-shaped, and the arc-shaped boundary of the N+ layer wraps the arc-shaped boundary of the P+ layer.

[0015] Furthermore, in the cross section A and the cross section B, the depth of the Pwell layer is greater than the depth of the N+ layer and greater than the depth of the P+ layer.

[0016] Furthermore, the depth of the Pwell layer in the cross section A is the same as that in the cross section B, and the depth of the Pwell layer is 0.5 μm-1.5 μm;

[0017] The depth of the N+ layer in the cross section A is the same as that in the cross section B, and the depth of the N+ layer is 0.3 μm-0.8 μm;

[0018] The depth of the P+ layer in the cross section A is the same as that in the cross section B, and the depth of the P+ layer is 0.1 μm-0.3 μm.

[0019] Furthermore, the concentration of aluminum ions injected into the Pwell layer is 1×10 17 -1×10 19 cm -3 The nitrogen ion concentration of the N+ layer is 1×10 18 -1×10 20 cm -3 The aluminum ion concentration injected into the P+ layer is 1×10 18 -1×10 20 cm -3 .

[0020] Furthermore, the depth of the trench structure exceeds the depth of the P+ layer and reaches or exceeds the depth of the N+ layer, but does not exceed the depth of the Pwell layer.

[0021] Furthermore, the depth of the groove structure is 0.1 μm-0.5 μm, and a metal layer is provided in the groove structure.

[0022] Furthermore, the thickness of the N-epitaxial layer is 5 μm-20 μm, and the ion concentration is 10 13 -10 17 cm -3 ;

[0023] The thickness of the polysilicon gate layer on the surface of the N-epitaxial layer is in the range of

[0024] The isolation layer completely covers the polysilicon gate layer;

[0025] The metal layer covers the cellular structure;

[0026] A drain electrode is also included below the N++ type SiC substrate (1).

[0027] The above method for preparing a SiC power MOSFET device comprises the following steps:

[0028] S1. growing an N-epitaxial layer of a desired thickness on an N++ type SiC substrate;

[0029] S2. Photolithographically defining a barrier layer region on the N-epitaxial layer to form a first mask, and removing the undefined barrier layer region by etching to obtain a barrier layer region having a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, without removing the first mask;

[0030] S3. Photolithography is performed to define through-regions on both sides of the barrier layer region with a trapezoidal cross-sectional configuration, forming a second mask. The defined through-regions are removed by etching. Partial slopes of the same width and length are vertically etched at the same intervals on both sides of the trapezoidal cross-sectional configuration. The partial slopes are the defined through-regions. The second mask is removed. The etching of the partial slopes on both sides of the waist forms a substrate with alternating cross-sections A and B.

[0031] S4. Since the first mask is not removed in S2, it can be used as a mask for ion implantation. Aluminum ions are implanted to a desired depth to form a Pwell layer. Nitrogen ions are then implanted into the Pwell region to a desired depth to form an N+ layer. Finally, aluminum ions are implanted into the N+ layer to a desired depth to form a P+ layer. Due to the presence of a punch-through region in the barrier layer region, the boundary cross-section structures formed by each ion layer during ion implantation are different. After removing the first mask, the barrier layer region is etched away to the N-epitaxial layer, thereby obtaining an alternating structure having cross-sections A and B in the N-epitaxial layer.

[0032] S5. Forming a polysilicon gate layer and an isolation layer wrapping the polysilicon gate layer in sequence on the surface of the N-epitaxial layer in the JFET region;

[0033] S6, etching the active area trench structure;

[0034] S7. Deposit the entire metal layer, and photolithographically define the active metal region and the gate metal region. After etching, the active region electrode and the gate electrode are formed respectively to obtain a SiC power MOSFET device.

[0035] Furthermore, the height of the barrier layer region is The mesa width of the barrier layer region is The angle formed by the lower base and waist of the trapezoid ranges from 15° to 60°; the spacing between two adjacent barrier layer areas is

[0036] Furthermore, when etching the through region, the width of the waists on both sides etched away is 0.1-0.5 μm (i.e., the same width), and the same spacing between the waists on both sides is retained at 0.5-1.5 μm;

[0037] The angle during ion implantation is 0°, meaning the ions are implanted vertically into the material surface.

[0038] Furthermore, wet etching is used in S2 to remove the undefined barrier layer area. The corrosive solution used in the wet etching is a mixture of an NH4F solution with a mass fraction of 30% to 40% and an HF solution with a mass fraction of 40% to 50%, which are mixed in a volume ratio of 0-8:1. This makes the ratio of the vertical etching rate to the horizontal etching rate within the range of 1:0.55-3.8, thereby achieving a barrier layer area with a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, with an inner angle of the bottom surface ranging from 15° to 60°. By optimizing and adjusting the above parameters, the lateral etching rate and the longitudinal etching rate are different during wet etching, forming a slope with a certain inclination angle.

[0039] Furthermore, plasma dry etching is used in S3 to generate interval etching on the slope of the waists on both sides of the barrier layer area to remove the defined penetration area; the gas for generating plasma is one or more of CF4, CHF3, C2F4, SF4, NF3, SF6, chlorine, and hydrogen bromide. By optimizing and adjusting the gas flow rate, etching parameters such as gas pressure, RF power and other conditions, these gases attack the side wall surface to form a passivation layer to protect the side from further etching, thereby forming anisotropically etched side wall shapes. The side wall protection mechanism ensures that the etching rate in the vertical direction is higher than the etching rate in the horizontal direction, thereby forming a base structure with alternating sections A and B; the base structure of section A is a cross-sectional structure with a side wall slope of 80°-90°, and the base structure of section B is the same as the cross-sectional structure of the barrier layer area.

[0040] Beneficial technical effects:

[0041] The present invention designs a barrier layer with spaced transverse strip slopes on the epitaxial layer, and has two different cross-sections. Due to the simultaneous existence of the two different cross-sections, different energies are injected to form two structures of Pwell layer, N+ layer, and P+ layer on the two cross-sections. The simultaneous existence of these two different cross-sectional structures can reduce the path of hole current under the N+ layer, so that most of the hole current flows through the path above the N+ layer, thereby greatly improving the device's anti-latch capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The hole current flow path in the cross-sectional view of a planar SiC MOSFET in the prior art;

[0043] Figure 2 Schematic diagrams of the top view and cross-sectional structure of the barrier layer region defined by photolithography on the surface of the N-epitaxial layer after step S2; Ⅰ is the top view structure, and Ⅱ is the cross-sectional structure;

[0044] Figure 3 Schematic diagram of a top view of a substrate having alternating cross sections A and B formed after step S3;

[0045] Figure 4 Schematic diagram of the cross-sectional structure of the substrate at section A and the schematic diagram of the cross-sectional structure of the substrate at section B formed after step S3;

[0046] Figure 5 Schematic diagram of the substrate structure of cross section A formed after step S4;

[0047] Figure 6 Schematic diagram of the substrate structure of cross section B formed after step S4;

[0048] Figure 7 Schematic diagram of the cross section A of the cell structure of the SiC power MOSFET device of the present invention;

[0049] Figure 8 Schematic diagram of the cross section B of the cell structure of the SiC power MOSFET device of the present invention;

[0050] 1-N++ type SiC substrate, 2-N-epitaxial layer, 3-Pwell layer, 4-N+ ​​layer, 5-P+ layer, 6-polysilicon gate layer, 7-isolation layer, 8-metal layer, 9-trench structure; 21-barrier layer region, 22-through region. DETAILED DESCRIPTION

[0051] The following will be combined with the embodiments and drawings of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0052] Unless otherwise specifically stated, the numerical value set forth in these embodiments does not limit the scope of the present invention. The technology and methods known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology and methods should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values.

[0053] In addition, it should be noted that the use of words such as "first" and "second" to limit masks, etc. is only to facilitate the distinction between the substances used in each step. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this utility model.

[0054] In the following examples, the experimental methods without specific conditions are generally measured according to national standards; if there is no corresponding national standard, the general standard requirements or general methods are used.

[0055] Example 1

[0056] A SiC power MOSFET device, the cell structure of the device is as follows Figure 7 and Figure 8 As shown, the following are arranged from bottom to top: a drain electrode (not shown in the figure), an N++ type SiC substrate 1, an N- epitaxial layer 2, a polysilicon gate layer 6, an isolation layer 7, and a metal layer 8;

[0057] Two bilaterally symmetrical Pwell layers 3 are provided on the surface of the N- epitaxial layer 2, with a JFET region formed between the two Pwell layers 3; an N+ layer 4 is provided on the Pwell layer 3, and a P+ layer 5 is provided on the N+ layer 4;

[0058] The surface of the N-epitaxial layer 2 has an alternating structure of cross sections A and B;

[0059] The structure of the cross section A is as follows Figure 7As shown: the cross-section of the JFET region is a trapezoid that is narrow at the top and wide at the bottom, and the boundaries of the two opposite sides of the pwell layers 3 are both arc-shaped and curved inward, and have straight bottom edges connected to the arcs; the pwell layer 3 wraps the N+ layer 4 and the P+ layer 5, and the boundary between the P+ layer 5 and the N+ layer 4 forms two stacked squares;

[0060] The structure of the cross section B is as follows Figure 8 As shown: the boundaries of the two pwell layers 3 are both arc-shaped and curved inward; the Pwell layer 3 wraps the N+ layer 4 and the P+ layer 5 inside, the boundary between the P+ layer 5 and the boundary between the N+ layer 4 are arc-shaped, and the arc-shaped boundary of the N+ layer 4 wraps the arc-shaped boundary of the P+ layer 5 inside;

[0061] The two sides of the cell structure have groove structures 9, in which a metal layer 8 is deposited;

[0062] The depth of the Pwell layer 3 is greater than the depth of the N+ layer 4 and greater than the depth of the P+ layer 5.

[0063] The depth of the Pwell layer 3 is 0.8 μm-1.5 μm, and the concentration of aluminum ions injected into the Pwell layer 3 is 1×10 17 -1×10 19 cm -3 ;

[0064] The depth of the N+ layer 4 is 0.4 μm-0.7 μm, and the concentration of nitrogen ions injected into the N+ layer 4 is 1×10 18 -1×10 20 cm -3 ;

[0065] The depth of the P+ layer 5 is 0.1 μm-0.3 μm, and the concentration of aluminum ions injected into the P+ layer 5 is 1×10 18 -1×10 20 cm -3 ;

[0066] The depth of the trench structure 9 exceeds the depth of the P+ layer 5 and reaches the depth of the N+ layer 4. The depth of the trench structure 9 is 0.1-0.5 μm.

[0067] The thickness of the N-epitaxial layer 2 is 5 μm-20 μm, and the ion concentration range is 10 13 -10 17 The thickness of the polysilicon gate layer 6 on the surface of the N- epitaxial layer 2 is The isolation layer 7 completely covers the polysilicon gate layer 6 ; the metal layer 8 covers the cellular structure.

[0068] Example 2

[0069] The method for preparing the SiC power MOSFET device having an alternating structure of cross sections A and B in the above embodiment 1 comprises the following steps:

[0070] S1. Growing an N-epitaxial layer 2 on an N++-type SiC substrate 1. The N-epitaxial layer 2 is typically prepared using a CVD method. The thickness of the N-epitaxial layer 2 is controlled by controlling CVD parameters such as temperature, pressure, and time. The thickness is typically between 5 and 20 microns. The thickness range is designed to meet the requirements of different semiconductor devices and ensure that the epitaxial layer can provide sufficient physical and electrical performance support.

[0071] S2, as follows Figure 2 The top view structure shown ( Figure 2 Figure Ⅰ) and cross-sectional structure ( Figure 2 Ⅱ), a barrier layer region 21 is photolithographically defined on the N-epitaxial layer 2, a first mask (usually a photoresist) is formed by conventional methods, and the undefined barrier layer region 21 is removed by wet etching, thereby obtaining a barrier layer region having a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, without removing the first mask;

[0072] By controlling the drying temperature (20° C.-100° C.) and drying time (10 seconds-10 minutes) for forming the first mask, and controlling the etching time (10 seconds-5 minutes), using an etching solution of 30%-40% by mass NH4F solution and 40%-50% by mass HF solution, and controlling the volume ratio of the two to be 6:1, the ratio of the vertical etching rate to the horizontal etching rate is within the range of 1:0.55-3.8, thereby achieving a barrier layer region 21 with a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, and a bottom inner angle range of 15°-60°;

[0073] The obtained height of the barrier layer region 21 is The mesa width of the barrier layer region 21 is The angle formed by the lower base and waist of the trapezoid is in the range of 30°-60°; the spacing between two adjacent barrier layer regions 21 is

[0074] S3. According to Figure 3-Figure 4 The top view and cross-sectional structure of the barrier layer region 21 having a trapezoidal cross-sectional configuration are photolithographically defined as through-regions 22. A second mask is formed by conventional methods, and dry etching is performed to remove the defined through-regions 22. Partial slopes of the same width and length are vertically etched from the waists of the trapezoidal cross-sectional configuration on both sides at the same interval. The partial slopes are the defined through-regions 22.

[0075] When etching the through region 22, the waists on both sides are etched with the same width of 0.2 μm-0.5 μm, and the waists on both sides retain the same spacing of 0.8 μm-1.2 μm; the second mask is removed by conventional methods;

[0076] Due to the etching of the partial slope of the waist on both sides, a base with alternating sections A and B is formed;

[0077] Plasma dry etching is used to generate interval etching on the slopes of the waists on both sides of the barrier layer region 21, thereby removing the defined through-region 22. The gas used to generate the plasma is one or more of CF4, CHF3, C2F4, SF4, NF3, SF6, chlorine, and hydrogen bromide. By optimizing and adjusting the gas flow rate and etching parameters such as gas pressure and radio frequency power, these gases attack the sidewall surface to form a passivation layer that protects the side from further etching, thereby forming anisotropically etched sidewall shapes. The sidewall protection mechanism ensures that the etching rate in the vertical direction is higher than the etching rate in the horizontal direction, thereby forming a substrate structure with alternating cross-sections A and B.

[0078] The base structure of section A is a cross-sectional structure with a sidewall slope of 80°-90°, and the base structure of section B is the same as the cross-sectional structure of the barrier layer region, specifically as follows: Figure 3 and Figure 4 As shown;

[0079] S4, since the first mask is not removed in S2, it can be used as a mask for ion implantation, and aluminum ions are implanted to form the Pwell layer 3 (the angle of ion implantation is 0°, and after multiple implantations with different energies and different doses, a depth of 0.8μm-1.5μm and a concentration of 1×10 17 -1×10 19 cm -3 Pwell layer 3);

[0080] Then, nitrogen ions are injected into the Pwell region 3 to form an N+ layer 4 (the angle of ion injection is 0°, and after multiple injections with different energies and doses, a depth of 0.4μm-0.7μm and a concentration of 1×10 18 -1×10 20 cm -3 N+ layer 4);

[0081] Finally, aluminum ions are injected into the N+ layer 4 to form the P+ layer 5 (the angle of ion injection is 0°, and after multiple injections with different energies and different doses, a depth of 0.1μm-0.3μm and a concentration of 1×10 18 -1×10 20 cm-3 P+ layer 5);

[0082] Since the barrier layer region 21 has a through region 22, the boundary cross-section structure formed by each ion layer is different due to different depths and concentrations during ion implantation. After removing the first mask, the barrier layer region is etched away to the N-epitaxial layer, thereby obtaining an alternating structure having cross sections A and B on the surface of the N-epitaxial layer 2. The result is shown in FIG. Figure 5 The cross-section A structure and Figure 6 The cross-sectional structure B is shown;

[0083] S5, grow a layer of N-epitaxial layer 2 on the JFET region by thermal oxidation. A silicon dioxide layer is formed to form a gate oxide, and then polysilicon is deposited on the gate oxide by PECVD to form a polysilicon gate layer 6;

[0084] Photolithography defines different areas of the polysilicon gate layer and etches away unnecessary polysilicon;

[0085] Deposit an insulating dielectric layer on the surface to electrically isolate the polysilicon from the metal. This insulating dielectric layer is the isolation layer 7.

[0086] S6. Photolithography is used to define the active area hole layer and the hole layers on different polysilicon gate layers, and a trench structure 9 with a depth of 0.1-0.5 μm is etched. The depth of the trench structure exceeds the P+ layer 5 and reaches the N+ layer 4.

[0087] S7, depositing a layer of metal on the overall cellular structure to obtain a metal layer 8 (cross-sectional structure as shown in FIG. Figure 7 and Figure 8 As shown), the active metal region and the gate metal region are defined by photolithography, and the active region electrode and the gate electrode (not shown) are formed respectively after etching to obtain a SiC power MOSFET device.

[0088] The design of the alternate transverse strip-shaped slope barrier layer forms an alternating structure of the alternate section A and section B by different injection energies. The hole current of the section A structure ( Figure 7 The middle dotted line shows the hole current) flows laterally to the P+ layer 5 on the N+ layer 4 in the cross-section B structure, reducing the hole current path under the N+ layer 4. Most of the hole current flows through the path above the N+ layer 4, thereby greatly increasing the device's anti-latch capability.

[0089] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field within the technical scope disclosed by the present invention can make equivalent replacements or changes based on the technical solution and concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A SiC power MOSFET device, characterized in that: The cell structure of the device comprises, from bottom to top, an N++ type SiC substrate (1), an N-epitaxial layer (2), a polysilicon gate layer (6), an isolation layer (7), and a metal layer (8); Two bilaterally symmetrical Pwell layers (3) are provided on the surface of the N- epitaxial layer (2), with a JFET region formed between the two Pwell layers (3); an N+ layer (4) is provided on the Pwell layer (3), and a P+ layer (5) is provided on the N+ layer (4); The surface of the N-epitaxial layer (2) has an alternating structure of cross sections A and B; The structure of the cross section A: the cross section of the JFET region is a trapezoidal shape that is narrow at the top and wide at the bottom, and the two opposite side boundaries of the Pwell layers (3) are both in the shape of an arc that bends inward, and have a straight bottom edge connected to the arc; The structure of the cross section B: the boundaries of the two Pwell layers (3) are both in the shape of an arc that bends inward; Both sides of the cellular structure are provided with groove structures (9).

2. A SiC power MOSFET device according to claim 1, characterized in that: In the structure of the cross section A, the Pwell layer (3) encloses the N+ layer (4) and the P+ layer (5), and the boundary between the P+ layer (5) and the N+ layer (4) forms two stacked squares; In the structure of the cross section B, the Pwell layer (3) wraps the N+ layer (4) and the P+ layer (5), the boundary of the P+ layer (5) and the boundary of the N+ layer (4) are arc-shaped, and the arc-shaped boundary of the N+ layer (4) wraps the arc-shaped boundary of the P+ layer (5).

3. A SiC power MOSFET device according to claim 2, characterized in that: In the cross section A and the cross section B, the depth of the Pwell layer (3) is greater than the depth of the N+ layer (4) and is greater than the depth of the P+ layer (5).

4. A SiC power MOSFET device according to claim 3, characterized in that: The depth of the Pwell layer (3) in the section A and the section B is the same, and the depth of the Pwell layer (3) is 0.5 μm-1.5 μm; The depth of the N+ layer (4) in the cross section A is the same as that in the cross section B, and the depth of the N+ layer (4) is 0.3 μm-0.8 μm; The depth of the P+ layer (5) in the cross section A is the same as that in the cross section B, and the depth of the P+ layer (5) is 0.1 μm-0.3 μm.

5. A SiC power MOSFET device according to any one of claims 1 to 4, characterized in that: The depth of the groove structure (9) exceeds the depth of the P+ layer (5) and reaches or exceeds the depth of the N+ layer (4), but does not exceed the depth of the Pwell layer (3).

6. A SiC power MOSFET device according to claim 5, characterized in that: The depth of the groove is 0.1 μm-0.5 μm, and a metal layer (8) is provided in the groove structure (9).

7. The SiC power MOSFET device according to claim 5, characterized in that: The thickness of the N-epitaxial layer (2) is 5 μm-20 μm; The thickness range of the polysilicon gate layer (6) on the surface of the N-epitaxial layer (2) is 8. The SiC power MOSFET device according to claim 5, characterized in that: The isolation layer (7) completely covers the polysilicon gate layer (6); The metal layer (8) covers the cellular structure; A drain electrode is also included below the N++ type SiC substrate (1).

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