Semiconductor device and semiconductor package

Abstract

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked on each other and disposed over the semiconductor substrate. A dielectric layer covers a top surface and a side surface of each of the plurality of semiconductor dies. A connector is disposed over an uppermost one of the plurality of semiconductor dies. A passivation layer is disposed over the dielectric layer and laterally surrounds the connector, where an acute angle is sandwiched between an outermost surface of the passivation layer and a topmost surface of the dielectric layer as viewed from a cross-sectional view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor package, and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, the demand for smaller and more innovative semiconductor die packaging technologies has also emerged. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and taking up less space on the printed circuit board (PCB). Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked one on top of the other and disposed above the semiconductor substrate. The dielectric layer covers the top and side surfaces of each of the plurality of semiconductor dies. The connector is disposed above the topmost of the plurality of semiconductor dies. The passivation layer is disposed above the dielectric layer and laterally surrounds the connector, wherein, in a cross-sectional view, an outermost surface of the passivation layer forms an acute angle with the bottom surface of the passivation layer.

[0004] According to some embodiments of the present disclosure, a semiconductor package includes a redistribution structure, a semiconductor device, and an encapsulation material. The semiconductor device is disposed above the redistribution structure and includes a plurality of stacked semiconductor dies, a passivation layer covering the top and side surfaces of each of the plurality of semiconductor dies, and a passivation layer disposed above a dielectric layer, wherein the outermost surface of the passivation layer is an inclined surface that is inclined relative to the perpendicular side surfaces of the dielectric layer. The encapsulation material is disposed above the redistribution structure and laterally encapsulates the semiconductor device.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps. A plurality of first semiconductor dies are arranged on a semiconductor substrate, wherein the plurality of first semiconductor dies are separated from each other by a plurality of gaps. A plurality of second semiconductor dies are respectively arranged on the plurality of first semiconductor dies. A dielectric layer is arranged on the semiconductor substrate, wherein the dielectric layer covers the top surfaces of the plurality of first semiconductor dies and the plurality of second semiconductor dies, and fills the plurality of gaps. A passivation layer is located on the dielectric layer. The passivation layer is patterned to form a plurality of openings corresponding to the plurality of gaps, respectively, wherein the sidewall of each of the plurality of openings is an inclined surface inclined to the vertical direction. A cutting process is performed to cut off the dielectric layer and the semiconductor substrate to form a plurality of semiconductor devices separated from each other. In one embodiment, the plurality of openings penetrate the passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.

[0007] Figures 1 to 8 A cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device according to some exemplary embodiments of the present disclosure is shown.

[0008] Figures 9 to 17 A cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor package according to some exemplary embodiments of the present disclosure is shown.

[0009] Figure 18 A top view of a semiconductor package according to some exemplary embodiments of the present disclosure is shown.

[0010] Description of reference numerals:

[0011] 100: Semiconductor packaging

[0012] 101A: First packaging area

[0013] 101B: Second packaging area

[0014] 102: Carrier substrate

[0015] 104: Release layer

[0016] 110, 120: Semiconductor devices

[0017] 111: Semiconductor substrate

[0018] 112, 112a, 112b: first semiconductor die, semiconductor die

[0019] 1121, 1141, 122: Semiconductor substrate

[0020] 1123, 1123a, 1123b, 1143, 1143a: Interconnection structure

[0021] 1124: Connectors

[0022] 1124a: First connecting piece

[0023] 1125a, 1145a: dielectric layer

[0024] 1126: Die bonding material

[0025] 113: first dielectric layer, dielectric layer

[0026] 114, 114a, 114b: second semiconductor die, semiconductor die

[0027] 1142: Conductive vias

[0028] 1144a: Second connecting piece

[0029] 1142a: Through hole

[0030] 115: Second dielectric layer, dielectric layer

[0031] 116, 162: UBM layer

[0032] 117, 124: Connectors

[0033] 118: Passivation layer

[0034] 140: Encapsulation material

[0035] 150: Redistribution Structure

[0036] 153: Dielectric layer

[0037] 154: Metallized pattern

[0038] 164: Conductive bump

[0039] 170: tape

[0040] 180: Package substrate

[0041] 182: External connector

[0042] 184: Bonding pad

[0043] 190: Bottom fill layer

[0044] G1: Gap

[0045] OP1: Opening

[0046] OP2: Grooves

[0047] SL: Cutting Line

[0048] S1: Outermost surface, sidewall

[0049] S2: vertical side surface

[0050] W1: width

[0051] θ1: acute angle

[0052] θ2: Angle DETAILED DESCRIPTION

[0053] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may further include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0054] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0055] Figures 1 to 8 FIG2 shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 , a semiconductor substrate 111 is provided. The semiconductor substrate 111 may be in wafer form. For example, the wafer-form semiconductor substrate 111 may be processed to include multiple die regions. In some embodiments, the semiconductor substrate 111 is attached to a temporary carrier or a frame including an adhesive layer.

[0056] In some embodiments, the semiconductor substrate 111 can be considered as a carrier wafer for bonding multiple dies thereon. In other embodiments, the semiconductor substrate 111 may include multiple semiconductor devices formed therein and an interconnect structure formed on the semiconductor substrate. It should be noted that the various layers and features of the semiconductor substrate 111 are omitted in the figure. For example, the semiconductor substrate 111 includes a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, etc., which may be doped or undoped. In some embodiments, the semiconductor substrate 111 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure.

[0057] In some embodiments, a plurality of first semiconductor dies 112 are provided above a semiconductor substrate 111. The first semiconductor dies 112 may be first formed in a semiconductor wafer. For example, the semiconductor wafer is processed to include a plurality of die regions, and each die region may include an integrated circuit device (e.g., a logic die, a memory die, a radio frequency die, a power management die, a microelectromechanical system (MEMS) die, etc., or a combination thereof). In some embodiments, the semiconductor wafer is attached to a temporary carrier or a frame including tape, and then the semiconductor wafer is divided along cutting lines to form individual semiconductor dies 112. Thereafter, the separated semiconductor dies 112 may be picked up and placed on the semiconductor substrate 111, where the first semiconductor dies 112 are separated from each other by a plurality of gaps G1.

[0058] In some embodiments, the first semiconductor die 112 and the semiconductor substrate 111 can be fabricated separately, and the first semiconductor die 112 can be removed from the tape frame and mounted on the semiconductor substrate 111 using, for example, a pick-and-place process or other suitable attachment techniques. The first semiconductor die 112 can be tested before bonding so that only known good dies (KGDs) are used for bonding.

[0059] In some embodiments, the first semiconductor die 112 may include a semiconductor substrate 1121 having a semiconductor device (not shown) formed therein and an interconnect structure 1123 formed on the semiconductor substrate 1121. In some embodiments, the semiconductor substrate 1121 of the first semiconductor die 112 includes a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, and may be doped or undoped. In some embodiments, the semiconductor substrate 1121 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. In some embodiments, a silicon-germanium alloy is formed on a silicon substrate. In other embodiments, the silicon-germanium substrate is strained. The semiconductor substrate 1121 may include semiconductor devices (not shown) formed therein or thereon, and the semiconductor devices may be or may include active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical components. In some embodiments, the semiconductor devices are formed on a side of the semiconductor substrate 1121 proximal to the interconnect structure 1123.

[0060] In some embodiments, the semiconductor substrate 1121 may include circuitry (not shown) formed in a front-end-of-line (FEOL) process, and the interconnect structure 1123 may be formed in a back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 1123 includes an interlayer dielectric (ILD) layer formed above the semiconductor substrate 1121 and covering the semiconductor device, and an intermetallization dielectric (IMD) layer formed above the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of a low-K dielectric material or an extremely low-K (ELK) material, such as oxide, silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, or combinations thereof. The ILD layer and the IMD layer may include any suitable number of dielectric material layers, but are not limited thereto.

[0061] For example, an interconnect structure 1123 including one or more dielectric layers and a metallization pattern is formed on a semiconductor substrate 1121. The metallization pattern may be embedded in a dielectric layer (e.g., an IMD layer), and the metallization pattern (e.g., a metal line, a metal via, a metal pad, etc.) may be formed of a conductive material such as copper, gold, aluminum, or the like, or a combination thereof. In some embodiments, the interconnect structure 1123 is electrically coupled to a plurality of semiconductor devices formed in and / or on the semiconductor substrate 1121, electrically coupling them to each other and to external components (e.g., a test pad, a bonding conductor, etc.). For example, the metallization pattern in the dielectric layer routes electrical signals between the semiconductor device and the semiconductor substrate 1121. The semiconductor device and the metallization pattern are interconnected to perform one or more functions, including memory structures (e.g., memory cells), processing structures, input / output circuits, etc.

[0062] Next, refer to Figure 2 , a first dielectric layer 113 is provided over the semiconductor substrate 111. In some embodiments, the first dielectric layer 113 fills the gap G1 between adjacent first semiconductor dies 112 and covers the top surface and side surface of the first semiconductor die 112. For example, the first dielectric layer 113 can be a dielectric layer made of one or more suitable dielectric materials (e.g., silicon oxide, silicon nitride, low-k dielectric, polyimide, combinations of these, etc.). In one embodiment, the material of the dielectric layer 113 includes an oxide (e.g., silicon oxide, etc.). In some embodiments, the first semiconductor die 112 may include a conductive pad (not shown) disposed over and electrically coupled to the top metallization pattern of the interconnect structure 1123, and the first dielectric layer 113 may have an opening exposing at least a portion of the conductive pad for testing or further electrical connection. After providing the first dielectric layer 113, a planarization process such as a chemical mechanical polishing (CMP) operation may be performed to planarize the top surface of the first dielectric layer 113.

[0063] In some embodiments, a plurality of connectors 1124 may be formed in the dielectric layer 113 to connect to the interconnect structures 1123 of the first semiconductor die 112, respectively. The connectors 1124 may be conductive pillars or vias (e.g., including a metal such as copper, aluminum, tungsten, nickel, or alloys thereof), and are mechanically and electrically connected to the interconnect structures 1123. The connectors 1124 may be formed, for example, by electroplating. The connectors 1124 electrically connect the integrated circuits of the first semiconductor die 112. It should be noted that although one connector 1124 is shown connected to one first semiconductor die 112, multiple connectors 1124 may be configured on one first semiconductor die 112.

[0064] Then, see Figure 3, a plurality of second semiconductor dies 114 are respectively provided on the plurality of first semiconductor dies 112 to form a second layer of the die stack. A similar process for forming the first semiconductor die 112 can be applied to form the second semiconductor die 114. The second semiconductor die 114 can first be in the form of a wafer, as a semiconductor wafer, which includes a plurality of die regions, each of which can include an integrated circuit device (for example, a logic die, a memory die, a radio frequency die, a power management die, a micro-electromechanical system (MEMS) die, etc. or a combination of these). The configuration of the die region can be similar to the configuration of the first semiconductor die 112 region described above. For example, each die position can include a semiconductor substrate 1141 and an interconnect structure 1143.

[0065] In some embodiments, each second semiconductor die 114 may further include a plurality of conductive vias 1142 formed in the semiconductor substrate 1141 and connected to the interconnect structure 1143. In some embodiments, the conductive vias 1142 are formed by forming a recess in the semiconductor substrate 1141, depositing a dielectric liner, a barrier material, and a conductive material in the recess, and removing excess material from the semiconductor substrate 1141. For example, the recess in the semiconductor substrate 1141 is lined with a dielectric liner to laterally separate the conductive vias 1142 from the semiconductor substrate 1141. The conductive vias 1142 may be formed using a via-first method. For example, the conductive vias 1142 may be formed during the formation of the interconnect structure 1143. Alternatively, the conductive vias 1142 (i.e., through-silicon vias (TSVs)) may be formed using a via-last method and may be formed after the interconnect structure 1143 is formed.

[0066] In some embodiments, the first semiconductor die 112 and the second semiconductor die 114 can be manufactured separately, and then the second semiconductor die 114 can be removed from the tape frame using, for example, a pick-and-place process or other suitable attachment technology to be mounted on the first semiconductor die 112. The second semiconductor die 114 can be tested before bonding so that only known good dies (KGDs) are used for bonding. It should be understood that semiconductor dies cut from different semiconductor wafers can have different characteristics and functions. In some embodiments, the first semiconductor die 112 and the second semiconductor die 114 are cut from different semiconductor wafers and can differ in function and properties. For example, the first semiconductor die 112 and the second semiconductor die 114 can be bonded together in a face-to-face configuration. In some embodiments, the second semiconductor die 114 is picked up and placed separately on the first semiconductor die 112. The front side of the first semiconductor die 112 can be bonded to the back side of the second semiconductor die 114. The first semiconductor die 112 and the second semiconductor die 114 can be similar in construction, function, and characteristics.

[0067] exist Figure 3 In the embodiment of the present invention, the first semiconductor die 112 and the second semiconductor die 114 are stacked in a face-to-face manner. However, the present disclosure is not limited thereto, and other die stacking methods may also be applied. For example, Figure 3A and Figure 3B Shows that according to Figure 3 Cross-sectional views of intermediate stages in the fabrication of semiconductor devices according to various embodiments other than those of FIG. Figure 3A In this embodiment, the first semiconductor die 112a and the second semiconductor die 114a are stacked face to face. That is, the front sides of the first semiconductor die 112a and the second semiconductor die 114a face each other. In one embodiment, before the second semiconductor die 114a is mounted on the first semiconductor die 112a, a planarization process may be performed on the dielectric layer 113 until the first connector 1124a of the interconnect structure 1123a is exposed. The second semiconductor die 114a is then further flipped and mounted on the first semiconductor die 112a.

[0068] Specifically, first semiconductor die 112a and second semiconductor die 114a are bonded face-to-face via vias, first connectors 1124a, and second connectors 1144a. In some embodiments, before bonding second semiconductor die 114a to first semiconductor die 112a, interconnect structure 1123a and interconnect structure 1143a are aligned such that first connector 1124a of interconnect structure 1123a can bond to second connector 1144a of interconnect structure 1143a, and dielectric layer 1125a of interconnect structure 1143a can bond to dielectric layer 1125a of interconnect structure 1143a. Interconnect structure 1123a can bond to dielectric layer 1145a of interconnect structure 1143a. In some embodiments, alignment of first connector 1124a and second connector 1144a can be achieved using optical sensing methods. After alignment is achieved, the interconnect structure 1123 a and the interconnect structure 1143 a are bonded together through a hybrid bonding process.

[0069] In one embodiment, interconnect structure 1123a and interconnect structure 1143a are hybrid-bonded together by applying pressure and heat. Hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding, such as dielectric-to-dielectric bonding or fusion bonding. More specifically, first connector 1124a and second connector 1144a are bonded by metal-to-metal bonding, and dielectric layer 1125a and dielectric layer 1145a are bonded by non-metal-to-non-metal bonding.

[0070] In some embodiments, a plurality of through vias 1142a may be formed in the second semiconductor die 114a. The through vias 1142a pass through the semiconductor substrate 1141a and are electrically connected to the second connector 1144a of the first interconnect structure 1143a. In some embodiments, the through vias 1142a include conductive vias, which may be made of copper, copper alloy, aluminum, aluminum alloy, or a combination thereof. In some other embodiments, the through vias 1142a may further include a diffusion barrier layer (not shown) surrounding the conductive vias. The material of the diffusion barrier layer is Ta, TaN, Ti, TiN, CoW, or a combination thereof, and may be formed by a suitable process such as an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The through vias 1142a are used to provide electrical connections on the back side of the second semiconductor die 114a.

[0071] See also Figure 3BIn this embodiment, the first semiconductor die 112 b and the second semiconductor die 114 b are stacked back-to-back. That is, the front sides of the first semiconductor die 112 b and the second semiconductor die 114 b face opposite directions. More specifically, in the illustrated orientation, the front side of the first semiconductor die 112 b faces downward, while the front side of the second semiconductor die 114 b faces upward.

[0072] In this embodiment, a first semiconductor die 112b is placed on a semiconductor substrate 111 with its front side facing the semiconductor substrate 111. The front side of the first semiconductor die 112b includes an interconnect structure 1123b that can be electrically connected to the semiconductor substrate 111. A dielectric layer 113 is disposed over the semiconductor substrate 111 and laterally encapsulates the first semiconductor die 112b. Next, a second semiconductor die 114b is placed back-to-back with the first semiconductor die 112b. While the second semiconductor die 114b can be placed in close contact with the first semiconductor die 112b, it is generally preferred that at least one layer of die attach material 1126 be disposed between the second semiconductor die 114b and the underlying first semiconductor die 112b. In one embodiment, the die attach material 1126 can be dispensed onto the back side of the first semiconductor die 112b before the second semiconductor die 114b is placed thereon. The die attach material 1126 may be a conductive adhesive, an electrically insulating adhesive, or an electrically-anisotropic adhesive film.

[0073] In embodiments where die attach material 1126 is disposed between and bonds adjacent back surfaces of semiconductor dies 112 b and 114 b together, die attach material 1126 may be an electrically insulating or conductive adhesive. For example, in embodiments where the back surfaces of semiconductor dies 112 b and 114 b lack conductive features, a conductive adhesive (e.g., a silver- or copper-filled epoxy) may be used as die attach material 1126. Such a conductive adhesive may further have a relatively high thermal conductivity to allow for conductive heat transfer across the die-to-die interface, which may improve heat dissipation between semiconductor dies 112 b and 114 b. In other embodiments, it may be desirable to provide electrical interconnection between aligned conductive features located on the respective back surfaces of semiconductor dies 112 b and 114 b. In such instances, an anisotropic adhesive or film may be used as die attach material 1126. Such anisotropic adhesive or film allows for electrical conduction through the thickness of die attach material 1126 while providing electrical insulation along the plane of die attach material 1126.

[0074] For ease of explanation, the remaining figures use Figure 3The die stacking structure shown is that the semiconductor dies 112 and 114 are arranged face to face. However, it is worth noting that Figure 3 、 Figure 3A 、 Figure 3B The die stacking structure shown in and other suitable die stacking structures are also applicable to the semiconductor packaging and manufacturing processes disclosed herein.

[0075] Reference Figure 4 , a second dielectric layer 115 is disposed over the first semiconductor die 112. Specifically, the second dielectric layer 115 covers the first dielectric layer 113, fills the gaps between adjacent second semiconductor dies 114, and covers the top and side surfaces of the second semiconductor die 114. For example, the second dielectric layer 115 can be a dielectric layer made of one or more suitable dielectric materials (e.g., silicon oxide, silicon nitride, low-k dielectric, polyimide, combinations of these, etc.). In one embodiment, the material of the second dielectric layer 115 includes an oxide, such as silicon oxide, etc. In some embodiments, the second semiconductor die 114 may include a conductive pad (not shown) disposed over and electrically coupled to the top metallization pattern of the interconnect structure 1143, and the second dielectric layer 115 may have an opening exposing at least a portion of the conductive pad for testing or further electrical connection. After providing the second dielectric layer 115, a planarization process such as a chemical mechanical polishing (CMP) operation may be performed to planarize the top surface of the second dielectric layer 115.

[0076] In some embodiments, the above steps may be repeated to form a die stack. It should be understood that the die stack arranged on the semiconductor substrate 111 may include any number of layers. That is, the die stack includes a plurality of semiconductor dies stacked on each other (e.g., a first semiconductor die 112, a second semiconductor die 114, etc.) and is disposed above the semiconductor substrate 111. In this embodiment, a two-layer die stack (including a first semiconductor die 112 and a second semiconductor die 114) is used as an example for illustration, but the present disclosure is not limited thereto. In other embodiments, a die stack having fewer or more layers may be provided on the semiconductor substrate 111.

[0077] In some embodiments, the semiconductor die (e.g., semiconductor die 112, 114) at each layer can be tested before bonding so that only known good die (KGD) are used to form the device stack, thereby improving manufacturing yield. In some embodiments where the semiconductor die (e.g., semiconductor die 112, 114) are memory dies, because the semiconductor dies are vertically stacked and bonded, faster inter-memory communication can be achieved through the die stack during operation, which in turn can increase data bandwidth and enable faster data access and data storage.

[0078] After forming a die stack having a desired number of layers on semiconductor substrate 111, an underbump metallurgy (UBM) layer 116 is formed on the topmost semiconductor die 114 (e.g., on a portion of the metal pad region of interconnect structure 1143). UBM layer 116 is selectively formed on the exposed portions of the metal pad region by electroless deposition or immersion techniques. In one embodiment, UBM layer 116 comprises a diffusion barrier layer formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or the like. In one embodiment, UBM layer 116 comprises a copper layer having a thickness of approximately 3,000 to 5,000 angstroms, but the thickness may be greater or less. Because a planarization process, such as a CMP process, is performed to planarize the top surface of second dielectric layer 115, UBM layer 116 is formed on a relatively flat surface (i.e., the top surface of second dielectric layer 115), thereby enhancing the bonding strength of UBM layer 116.

[0079] Then, connectors 117 are disposed on the topmost semiconductor die (e.g., second semiconductor die 114). Specifically, connectors 117, such as conductive vias or pillars (e.g., formed of a metal such as copper), are physically and electrically coupled to corresponding UBM layers 116 and corresponding metal pad regions of interconnect structure 1143. Connectors 117 may be formed, for example, by electroplating, but the present disclosure is not limited thereto. Note that while one connector 117 is shown, more than one connector 117 may be disposed on a topmost semiconductor die.

[0080] Then, a passivation layer 118 may be disposed over the dielectric layer 115 of the topmost semiconductor die 114 in the die stack. In some embodiments, the passivation layer 118 covers the dielectric layer 115, the UBM layer 116, and at least laterally surrounds each connector 117. Because a planarization process, such as a CMP process, is performed to planarize the top surface of the second dielectric layer 115, the passivation layer 118 is formed on a relatively flat surface, thereby enhancing the bonding strength of the passivation layer 118. Initially, the passivation layer 118 may bury the die connectors 117, such that the topmost surface of the passivation layer 118 is located above the topmost surface of the connectors 117. In some embodiments where solder regions are disposed on the connectors 117, the passivation layer 118 may also bury the solder regions. In one embodiment, the passivation layer 118 is formed of a polymer layer, such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), combinations thereof, etc., but the present disclosure is not limited thereto. In addition, other relatively soft, typically organic, dielectric materials may also be used. Passivation layer 118 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, during the formation of semiconductor device 110, connector 117 is exposed through passivation layer 118 by, for example, a thinning process (e.g., CMP). In some embodiments, die connector 117 remains buried and is exposed during subsequent processes for packaging semiconductor device 110.

[0081] Then, refer to Figure 6 In some embodiments, a cutting process is performed on the scribe line region (within the gap G1) to separate the individual semiconductor devices 110, as shown in FIG. Figure 7 As shown. Generally speaking, for the singulation process, laser ablation is used to cut at least the top portion of the tube core (for example, the interconnect structure, the passivation layer, etc.) to avoid cracks, fragments, peeling and delamination of the material layer of the tube core caused by the blade saw process. However, during the laser ablation process, in addition to heating the material to melt or evaporate it, other effects such as plasma formation also occur. Sometimes complex processes can occur at the interface. Using a laser with a picosecond pulse length, the interface between the oxide (the material of the dielectric layers 113 and 115) and the silicon (the material of the semiconductor substrate 111) will be affected. Using a picosecond laser with a UV wavelength enhances the interface effect, causing the oxide film to separate and delaminate from the silicon surface.

[0082] Therefore, in this embodiment, a sheet cutting process and a laser ablation process are not used, but a patterning process is performed on the passivation layer 118 to form a plurality of openings OP1 corresponding to the gaps G1, so as to avoid cracks, fragments, peeling and delamination of the material layer of the tube core caused by the cutting process. Note that one opening OP1 is shown here, but a plurality of openings OP1 can be formed according to the number of gaps G1, which depends on the number of tube cores stacked on the semiconductor substrate 111. In some embodiments, the patterning process for forming the opening OP1 includes a photolithography and an etching process, and the opening OP1 passes through the passivation layer 118. Therefore, the photolithography process creates a sidewall of the opening OP1 with a relatively flat slope. In other words, as Figure 6 As shown, the sidewall of each opening OP1 is a slope inclined from the vertical direction. Figure 6 From the cross-sectional view shown, an acute angle θ1 is formed between the outermost surface S1 of the passivation layer 118 (i.e., the sidewall of the opening OP1) and the bottom surface of the passivation layer 118. That is, the outermost surface S1 of the passivation layer 118 forms an acute angle θ1 with a plane parallel to the top surface of the dielectric layer 115. In one embodiment, the acute angle θ1 is less than about 90° and is substantially equal to or greater than about 70° (i.e., 70°≤θ1<90°). If the acute angle θ1 is less than 70°, the encapsulation material 140 (e.g., the encapsulation material 140) subsequently used to fill the opening OP1 may not be formed. Figure 13 As shown in FIG. 1 , the amount of the passivation layer 118 (shown) may be excessive, which may cause severe warping of the package. Therefore, the width of the opening OP1 decreases as the opening OP1 extends from the top surface of the passivation layer 118 toward the dielectric layer 115.

[0083] Afterwards, refer to Figure 7 and Figure 8, a cutting process is performed to cut through the dielectric layers 113, 115 and the semiconductor substrate 111 to form a plurality of separated semiconductor devices 110. Instead of using a laser ablation process, the cutting process is used to cut through the dielectric layers 113, 115 to avoid delamination at the interface between the oxide (the material of the dielectric layers 113, 115) and silicon (the material of the semiconductor substrate 111). The cutting process generates a plurality of grooves OP2 having generally vertical sidewalls. That is, the outermost surfaces S2 of the dielectric layers 113, 115 are generally vertical surfaces. Thus, the included angle θ2 between the side surface and the bottom surface of the semiconductor substrate 111 is generally equal to or less than about 90° and generally equal to or greater than about 85° (i.e., 85 ≤ θ2 ≤ 90°). In this way, the sidewall S1 of each opening OP1 is inclined with respect to the vertical side surface S2 of each groove OP2 of the dielectric layer 115 cut by the cutting process. The cutting process forms a plurality of grooves OP2 along scribe lines, and the width of the grooves OP2 formed by the cutting process is smaller than the minimum width of the openings OP1 formed by the lithography process. Thus, the openings OP1 expose the edge portions of the dielectric layer 115. In other words, the dielectric layer 115 includes edge portions not covered by the passivation layer 118. In one embodiment, the width W1 of the edge portions is greater than 0 μm and generally equal to or less than 20 μm (i.e., 0 μm < W1 ≤ 20 μm).至此, Figure 8 The manufacturing process of the semiconductor device 110 shown is generally completed. If the width W1 is equal to 0, that is, the bottom of the opening OP1 of the passivation layer 118 is as narrow as the groove OP2 formed by the cutting process, the tool used for the cutting process may accidentally contact the passivation layer 118 when applied to the dielectric layer 115, which may cause cracks, fragments, peeling, and delamination in the passivation layer 118. [[ID=​​​​​​​​In some embodiments, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed simultaneously on the carrier substrate 102. In some embodiments, the release layer 104 may be formed of a polymer-based material, which may be removed together with the carrier substrate 102 from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 104 may be applied and cured as a liquid, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be flat and may have a high degree of flatness. In some embodiments, the release layer 104 may be omitted.

[0086] Reference Figure 10 , a plurality of semiconductor devices 110 and 120 are disposed on a carrier substrate 102. In the illustrated embodiment, the semiconductor devices 110 and 120 are attached to the carrier substrate 102 via a release layer 104. In other embodiments, the semiconductor devices 110 and 120 may be attached to the carrier substrate 102 via an adhesive applied to the backsides of the semiconductor devices 110 and 120. The adhesive may be any suitable adhesive, epoxy, die attach film (DAF), or the like. A desired type and number of semiconductor devices 110 and 120 are attached to each of the first packaging region 101A and the second packaging region 101B. In the illustrated embodiment, the plurality of semiconductor devices 110 and 120 are attached adjacent to each other in a side-by-side manner.

[0087] In some embodiments, each semiconductor device 110 is formed by the above-described manufacturing process and is a stacked device including multiple semiconductor dies 112 and 114. Therefore, semiconductor device 110 includes at least semiconductor dies 112 and 114 stacked on top of each other, dielectric layers 113 and 115 covering the top and side surfaces of each of semiconductor dies 112 and 114, and a passivation layer 118 disposed above dielectric layer 115. Due to the two steps of the singulation process (patterning and cutting), the outermost surface S1 of passivation layer 118 is inclined relative to the vertical side surface of dielectric layer 115. In some embodiments, semiconductor device 110 may be a memory die. The memory die may include a memory device such as a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, other suitable devices, or a combination thereof. The die stack of semiconductor device 110 may be used as a high-bandwidth memory (HBM). In some embodiments, the die stack is also a high-bandwidth memory including multiple stacked memory dies.

[0088] In some embodiments, semiconductor device 120 includes a semiconductor substrate 122 and an interconnect structure formed on semiconductor substrate 122. In some embodiments, various device components are formed in semiconductor substrate 122. Examples of various device components include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), diodes, or other suitable components. The device components are interconnected by the interconnect structure to form an integrated circuit device. Integrated circuit devices include logic devices, memory devices (e.g., static random access memory, SRAM), radio frequency (RF) devices, input / output (I / O) devices, system-on-chip (SoC) devices, other applicable types of devices, or combinations thereof. In some embodiments, semiconductor device 120 is a system-on-chip (SoC) that includes multiple functions.

[0089] Figure 18 FIG2 shows a top view of a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 10 and Figure 18 In some embodiments, each of the package regions 101A and 101B may include a semiconductor device 120 and a plurality of semiconductor devices 110 disposed around the semiconductor device 120. Figure 18 In the embodiment, the semiconductor device 110 is disposed on opposite sides of the semiconductor device 120 , but the configuration of the semiconductor devices 110 and 120 is not limited thereto.

[0090] Next, refer to Figure 11 In some embodiments, an encapsulation material 140 is formed on and around the semiconductor devices 110 and 120. After formation, the encapsulation material 140 encapsulates the semiconductor devices 110 and 120. The encapsulation material 140 may be a molding compound, an epoxy resin, or the like. The encapsulation material 140 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102 such that the semiconductor devices 110 and 120 are buried or covered. The encapsulation material 140 is further formed in the gap region between the semiconductor devices 110 and 120. In some embodiments, the encapsulation material 140 may be applied in a liquid or semi-liquid form and subsequently cured.

[0091] Afterwards, a planarization process is performed on encapsulation material 140 to expose connectors 117 of semiconductor device 110 and connectors 124 of semiconductor device 120. The planarization process may further remove the top portions of encapsulation material 140, passivation layer 118, and passivation layer 126 of semiconductor device 120 until connectors 117 and 124 are exposed. After the planarization process, the top surfaces of connectors 117 and 124, passivation layers 118 and 126, and encapsulation material 140 may be flush with each other (e.g., coplanar). The planarization process may be, for example, a chemical mechanical polishing (CMP) process, a grinding process, an etch-back process, or the like. In some embodiments, for example, if connectors 117 and 124 are already exposed, the planarization process may be omitted. Thus, encapsulation material 140 laterally encapsulates semiconductor devices 110 and 120.

[0092] According to some embodiments of the present disclosure, referring to Figure 13, the encapsulation material 140 contacts the inclined side surface S1 of the passivation layer 118, the vertical side surfaces S2 of the dielectric layers 113 and 115, and the top surface of the semiconductor substrate 111. In the illustrated embodiment, an acute angle θ1 is formed between the outermost side surface S1 of the passivation layer 118 and the bottom surface of the passivation layer 118. Thus, the inclined side surface S1 of the passivation layer 118 is inclined with respect to the vertical side surface S2 of the dielectric layer 115, and the encapsulation material 140 laterally encapsulates the inclined side surface S1 of the passivation layer 118 and the vertical side surfaces S2 of the dielectric layers 113 and 115. Additionally, the encapsulation material 140 covers (contacts) the edge portion of the dielectric layer 115 that is not covered by the passivation layer 118. In one embodiment, the width W1 of the edge portion is greater than 0 μm and is generally equal to or less than 20 μm (i.e., 0 μm < W1 ≤ 20 μm). If the width W1 is equal to 0, which means that the bottom of the opening of the passivation layer 118 is as narrow as the groove formed by the tool cutting process, then the tool cutting process applied to the dielectric layer 115 may still contact the passivation layer 118, which may cause fragmentation, peeling, and delamination of the material layer of the cracked passivation layer 118.

[0093] Now referring to Figure 14 , in some embodiments, a redistribution structure 150 is formed over the encapsulation material 140 and the semiconductor devices 110 and 120. The redistribution structure 150 includes a dielectric layer 153 and a metallization pattern 154. The metallization pattern may also be referred to as a redistribution layer or a redistribution line (RDL). Figure 14 The illustrated redistribution structure 150 includes three layers of metallization patterns and four layers of dielectric layers; however, the redistribution structure 150 may include more or fewer metallization patterns and dielectric layers. Thus, the top surface of the connector 117 is coplanar with the top surface of the passivation layer 118 and is bonded to the redistribution structure 150.

[0094] According to some embodiments of the present disclosure, the redistribution structure 150 can be used to fan out electrical contacts from the semiconductor devices 110 and 120. It should be understood that the depiction of the redistribution structure 150 in all figures is schematic. The redistribution structure 150 includes redistribution lines (RDLs) (e.g., metal traces (or metal lines)) and through-holes located below and connected to the metal traces. According to some embodiments of the present disclosure, the RDLs are formed by an electroplating process, wherein each RDL includes a seed layer (not shown) and an electroplated metal material above the seed layer. The seed layer can be formed using, for example, PVD. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the RDL. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The seed layer and the plated metal material can be formed of the same material or different materials. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer where the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer can be removed, such as by using an acceptable etching process (e.g., wet and / or dry etching). The remaining portion of the seed layer and the conductive material forms the RDL.

[0095] A dielectric layer or passivation layer may be formed over each layer of metal traces. In some embodiments, the dielectric layer or passivation layer is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., which may be patterned using a photolithographic mask. In other embodiments, the dielectric layer or passivation layer is formed of a nitride such as silicon nitride, an oxide (e.g., silicon oxide, PSG, BSG, BPSG), or the like. The dielectric layer or passivation layer may be formed by spin coating, lamination, CVD, etc., or a combination thereof. An opening may be formed in the topmost dielectric layer or passivation layer via a patterning process, which exposes part or all of the topmost metal layer of the redistribution structure 150. The patterning process may be an acceptable process, such as by exposing the dielectric layer or passivation layer to light when the dielectric layer is a photosensitive material or by etching using, for example, anisotropic etching.

[0096] Reference Figure 15Afterwards, a UBM layer 162 may be formed for external connection to the redistribution structure 150. The UBM layer 162 has a bump portion on and extending along the main surface of the topmost dielectric layer 153, and has a via portion extending through the topmost dielectric layer 153 to physically and electrically couple to the metallization pattern 154. As a result, the UBM layer 162 is electrically coupled to the semiconductor devices 110 and 120. The UBM layer 162 may be formed of the same material as the metallization pattern 154.

[0097] Afterwards, a plurality of conductive bumps 164 are formed on the UBM layer 162. The conductive bumps 164 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive bumps 164 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive bumps 164 are formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow soldering may be performed to shape the material into the desired bump shape. In another embodiment, the conductive bumps 164 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillars. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0098] Now refer to Figure 16 , Figure 15 The structure shown is flipped over, placed on tape 170, and the carrier substrate 102 is removed from the Figure 15 Debonding the backside of the structure (e.g., the backsides of encapsulation material 140 and semiconductor devices 110 and 120) is performed. According to some embodiments, debonding includes projecting light, such as laser light or UV light, onto release layer 104, causing release layer 104 to decompose under the heat of the light and allowing carrier substrate 102 to be removed. The structure is then flipped over and placed on tape 170.

[0099] In addition, Figure 16 In some embodiments, a sawing process is performed by sawing along a sawing line SL (e.g., between the first package region 101A and the second package region 101B) to form a plurality of semiconductor packages 100. The resulting semiconductor package 100 includes a redistribution structure 150, semiconductor devices 110 and 120 disposed over the redistribution structure 150, and an encapsulation material 140 disposed over the redistribution structure 150.

[0100] In some embodiments, the redistribution structure 150 may be pre-cut. A cutting device may partially cut into the redistribution structure 150 along a cutting line SL between the first packaging region 101A and the second packaging region 101B to form a groove (not separately shown) in the redistribution structure 150. In some embodiments, the cutting device used for the pre-cutting process is a laser. The pre-cutting process can prevent delamination of the redistribution structure 150 and its layers during a subsequent cutting process.

[0101] In summary, see Figure 7 The method for singulating the semiconductor device 110 adopts a two-stage singulation process, including first performing a patterning process (such as a photolithography process) on the passivation layer 118 to form an opening OP1 and then performing a cutting process to cut through the dielectric layers 113, 115 and the semiconductor substrate 111 to separate the semiconductor device 110. On the other hand, referring to Figure 16 The method for singulating the semiconductor package 100 may include performing a sawing process to cut through at least the encapsulation material 140 to separate the semiconductor packages 100. Alternatively, a pre-cutting process (e.g., a laser ablation process) may be performed on the redistribution structure 150 to pre-cut the redistribution structure 150, and then a sawing process may be performed to cut through the encapsulation material 140.

[0102] Afterwards, refer to Figure 17 In some embodiments, one of the individualized semiconductor packages 100 is attached to a package substrate 180 to form the final package structure 10. The package substrate 180 may be, for example, a printed circuit board (PCB) and may be connected to the semiconductor package 100 via conductive bumps 164. The package substrate 180 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or combinations thereof may be used. In addition, the package substrate 180 may also be an SOI substrate. Generally speaking, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the package substrate 180 is based on an insulating core (e.g., a glass fiber reinforced resin core). An exemplary core material is a glass fiber resin, such as FR4. Alternative core materials include bismaleimide triazine (BT) resin or other PCB materials or films. Build up films such as ABF or other laminate materials may be used for packaging substrate 180 .

[0103] According to some embodiments of the present disclosure, the package substrate 180 may include active and passive devices (not shown). Those skilled in the art will recognize that a variety of devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to generate the structural and functional requirements of the design of the final package structure. The devices may be formed using any suitable method. The package substrate 180 may further include metallization layers and vias (not shown) and bonding pads 184 above the metallization layers and vias. The metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric layers (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias used to interconnect the conductive material layers, and may be formed by any suitable process (e.g., deposition, single inlay, dual inlay, etc.). In some embodiments, the package substrate 180 is substantially free of active and passive devices.

[0104] In some embodiments, conductive bumps 164 are reflowed to bond to bond pads 184 of package substrate 180. Conductive bumps 164 are electrically and / or physically connected to package substrate 180, including metallization layers in package substrate 180, to semiconductor package 100. In some embodiments, an underfill layer 190 may be formed between the gap of semiconductor package 100 and package substrate 180 to at least laterally encapsulate conductive bumps 164. Alternatively, underfill layer 190 may be omitted.

[0105] In some embodiments, a plurality of external connectors 182 are formed to electrically contact the package substrate 180. In an embodiment, the external connectors 182 may be a ball grid array and may be placed on the bottom surface of the package substrate 180 and may include a eutectic material such as solder, but any suitable material may alternatively be used. In an embodiment where the external connectors 182 are solder balls, the external connectors 182 may be formed using a ball drop method to place the external connectors 182 onto an under bump metallization (UBM), such as a direct ball drop process. Alternatively, the solder balls may be formed by first forming a tin layer by any suitable method, such as evaporation, electroplating, printing, solder transfer, and then preferably performing reflow to shape the material into the desired bump shape. Once the external connectors 182 are formed, testing may be performed to ensure that the structure is suitable for further processing.

[0106] Based on the above discussion, it can be seen that the present disclosure provides various advantages. However, it should be understood that not all advantages are necessarily discussed herein, and other embodiments may provide different advantages, and it is not necessary for all embodiments to have a particular advantage.

[0107] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked one upon another and disposed above the semiconductor substrate. The dielectric layer covers the top and side surfaces of each of the plurality of semiconductor dies. The connector is disposed above the topmost of the plurality of semiconductor dies. The passivation layer is disposed above the dielectric layer and laterally surrounds the connector, wherein an acute angle is formed between the outermost surface of the passivation layer and the topmost surface of the dielectric layer. In one embodiment, the acute angle is less than 90° and substantially equal to or greater than 70°. In one embodiment, the dielectric layer includes an edge portion not covered by the passivation layer, and the width of the edge portion is greater than 0 μm and substantially equal to or less than 20 μm. In one embodiment, the angle formed between the side surface and the bottom surface of the semiconductor substrate is substantially equal to or less than 90° and substantially equal to or greater than 85°. In one embodiment, the dielectric layer is made of an oxide. In one embodiment, the passivation layer is made of a polymer. In one embodiment, the outermost surface of the dielectric layer is substantially vertical.

[0108] According to some embodiments of the present disclosure, a semiconductor package includes a redistribution structure, a semiconductor device, and an encapsulation material. The semiconductor device is disposed above the redistribution structure and includes a plurality of semiconductor dies stacked on each other, a top surface and side surfaces covering each of the plurality of semiconductor dies, and a passivation layer disposed above a dielectric layer, wherein the outermost surface of the passivation layer is an inclined surface inclined relative to the vertical side surface of the dielectric layer. The encapsulation material is disposed above the redistribution structure and laterally encapsulates the semiconductor device. In one embodiment, the semiconductor device further includes a connector disposed above the topmost one of the plurality of semiconductor dies, and the passivation layer laterally surrounds the connector. In one embodiment, the top surface of the connector is coplanar with the top surface of the passivation layer and is bonded to the redistribution structure. In one embodiment, an acute angle is formed between the outermost surface of the passivation layer and the topmost surface of the dielectric layer. In one embodiment, the acute angle is less than 90° and substantially equal to or greater than 70°. In one embodiment, the dielectric layer includes an edge portion not covered by the passivation layer, and the width of the edge portion is greater than 0 μm and substantially equal to or less than 20 μm. In one embodiment, the semiconductor package further includes a package substrate, and the package substrate is bonded to the redistribution structure through a plurality of conductive bumps.

[0109] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps. A plurality of first semiconductor dies are arranged on a semiconductor substrate, wherein the plurality of first semiconductor dies are separated from each other by a plurality of gaps. A plurality of second semiconductor dies are respectively arranged on the plurality of first semiconductor dies. A dielectric layer is arranged on the semiconductor substrate, wherein the dielectric layer covers the top surfaces of the plurality of first semiconductor dies and the plurality of second semiconductor dies and fills the plurality of gaps. A passivation layer is located on the dielectric layer. The passivation layer is patterned to form a plurality of openings corresponding to the plurality of gaps, wherein the sidewall of each of the plurality of openings is an inclined surface inclined to a vertical direction. A cutting process is performed to cut the dielectric layer and the semiconductor substrate to form a plurality of semiconductor devices separated from each other. In one embodiment, the plurality of openings penetrate the passivation layer. In one embodiment, the dielectric layer includes an edge portion not covered by the passivation layer, and the width of the edge portion is greater than 0 μm and substantially equal to or less than 20 μm. In one embodiment, the sidewall of each of the plurality of openings is inclined relative to the vertical side surface of the dielectric layer cut by the cutting process. In one embodiment, disposing a dielectric layer over a semiconductor substrate further includes: disposing a first dielectric layer over the semiconductor substrate, wherein the first dielectric layer fills a plurality of gaps and covers top surfaces of a plurality of first semiconductor dies; providing a second dielectric layer over the plurality of first semiconductor dies, wherein the second dielectric layer covers the first dielectric layer and top surfaces of the plurality of second semiconductor dies. In one embodiment, the method for fabricating a semiconductor device further includes: providing a connector over each of the plurality of second semiconductor dies, wherein the passivation layer at least laterally surrounds the connector.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; a plurality of semiconductor dies stacked on top of each other and disposed above the semiconductor substrate; a dielectric layer covering a top surface and side surfaces of each of the plurality of semiconductor dies; a connector disposed above an uppermost one of the plurality of semiconductor dies; as well as A passivation layer is disposed above the dielectric layer and laterally surrounds the connector, wherein, from a cross-sectional view, an outermost surface of the passivation layer forms an acute angle with the bottom surface of the passivation layer.

2. The semiconductor device according to claim 1, wherein The acute angle is less than 90° and equal to or greater than 70°.

3. The semiconductor device according to claim 1, wherein The dielectric layer includes an edge portion not covered by the passivation layer, and a width of the edge portion is greater than 0 μm and equal to or less than 20 μm.

4. The semiconductor device according to claim 1, wherein The outermost surface of the dielectric layer is a vertical surface.

5. A semiconductor package, characterized in that: include: Redistribution structure; a semiconductor device disposed above the redistribution structure and comprising a plurality of semiconductor dies stacked on one another, a dielectric layer covering a top surface and a side surface of each of the plurality of semiconductor dies, and a passivation layer disposed above the dielectric layer, wherein an outermost surface of the passivation layer is an inclined surface inclined relative to a vertical side surface of the dielectric layer; as well as An encapsulation material is disposed above the redistribution structure and laterally encapsulates the semiconductor device.

6. The semiconductor package according to claim 5, wherein The semiconductor device further includes a connector disposed above an uppermost one of the plurality of semiconductor dies, and the passivation layer laterally surrounds the connector.

7. The semiconductor package according to claim 6, wherein: A top surface of the connector is coplanar with a top surface of the passivation layer and is bonded to the redistribution structure.

8. The semiconductor package according to claim 5, wherein From the cross-sectional view, an acute angle is formed between the outermost surface of the passivation layer and the bottom surface of the passivation layer.

9. The semiconductor package according to claim 8, wherein The acute angle is less than 90° and equal to or greater than 70°.

10. The semiconductor package according to claim 5, wherein The invention further includes a package substrate, which is bonded to the redistribution structure through a plurality of conductive bumps.

Images