Power switch circuit

Abstract

The utility model relates to a power switch circuit, which comprises a controller, a switch sub-circuit and a switch delay sub-circuit, and is characterized in that the power input end of the switch sub-circuit is electrically connected with an external power supply, the power output end of the switch sub-circuit is electrically connected with a load, and the control end of the switch sub-circuit is electrically connected with the controller; and the switch delay sub-circuit is electrically connected with the switch sub-circuit. According to the utility model, the switching time of the power switch can be prolonged by arranging the switch time-delay sub-circuit, so that the instant charging current during the switching of the power switch is reduced, and the problem that the switching time of the switching power supply in the prior art is too short is solved. And the power supply voltage of the pre-stage circuit drops due to the fact that the load requests the instant large current.

Description

Technical Field

[0001] The utility model relates to the technical field of power switches, and more particularly to a power switch circuit. Background Art

[0002] In existing electronic products, the internal PMOS power switching circuit of the front-stage circuit will instantly charge the large capacitor or other load of the subsequent circuit with a large current at the moment of switching. This is because the power is powered on too quickly and too quickly, and the load is suddenly powered up, which will suddenly demand a very large current, causing the power supply voltage of the front-stage circuit to drop and causing system abnormal operation.

[0003] The prior art discloses a power switch circuit, one end of which is coupled to a voltage input end and the other end is coupled to a voltage output end, and is used to control the on and off of the voltage input end and the voltage output end, wherein the voltage input end is coupled to an external power supply, and the voltage output end is used to power a load device; the power switch circuit includes a self-starting circuit and a main switch circuit connected in parallel; the self-starting circuit is used to make the voltage input end and the voltage output end conduct for a preset time through the self-starting circuit when the external power supply is powered off and then powered on; the main switch circuit is used to receive a control signal sent by the load device, and based on the control signal The voltage input terminal and the voltage output terminal are controlled to be turned on or off through the main switch circuit; the self-starting circuit includes: a first switch element, including a first connection terminal, a second connection terminal and a first enable terminal, the first connection terminal being coupled to the voltage input terminal, and the second connection terminal being coupled to the voltage output terminal; a discharge branch, one end of which is coupled to the voltage input terminal and the other end is grounded; an energy storage unit, one end of which is coupled to the voltage input terminal and the first enable terminal respectively, and the other end is grounded, when the voltage of the energy storage unit is less than a preset starting voltage, the first switch element is turned on, and the starting voltage is less than the output voltage of the external power supply. However, the power switch circuit also has the problem of excessive instantaneous current when the power is switched, which causes the power supply voltage of the previous stage circuit to drop, resulting in abnormal system operation. Utility Model Content

[0004] The utility model provides a power switch circuit, which solves the technical problem in the prior art that the power supply voltage of the front-stage circuit drops at the moment when the switch power is switched.

[0005] In order to achieve the above utility model purpose, the technical solution adopted is:

[0006] The utility model provides a power switch circuit, including a controller, a switch subcircuit and a switch delay subcircuit, wherein:

[0007] The power input terminal of the switch subcircuit is electrically connected to an external power supply, the power output terminal of the switch subcircuit is electrically connected to a load, and the control terminal of the switch subcircuit is electrically connected to the controller;

[0008] The switch delay sub-circuit is electrically connected to the switch sub-circuit.

[0009] In the above technical means, by setting a switch delay sub-circuit, the switching time of the power switch can be extended, thereby reducing the instantaneous charging current when the power switch is switched, solving the technical problem in the prior art that at the moment of switching the switch power, the load demands an instantaneous large current, thereby causing the power supply voltage of the previous circuit to drop.

[0010] Furthermore, the switch sub-circuit includes a PMOS transistor Q5 and a resistor R4, wherein:

[0011] The source of the PMOS transistor Q5 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R4 respectively;

[0012] The drain of the PMOS transistor Q5 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load;

[0013] The gate of the PMOS tube Q5 is electrically connected to the switch delay sub-circuit;

[0014] The other end of the resistor R4 is electrically connected to the controller and the switch delay sub-circuit respectively.

[0015] Furthermore, the switch delay sub-circuit includes a resistor R5 and a capacitor C3, wherein:

[0016] One end of the resistor R5 is electrically connected to the other end of the resistor R4;

[0017] The other end of the resistor R5 is electrically connected to one end of the capacitor C3 and the gate of the PMOS transistor Q5 respectively;

[0018] The other end of the capacitor C3 is grounded.

[0019] Furthermore, it also includes a capacitor C5, wherein:

[0020] One end of the capacitor C5 is electrically connected to the drain of the PMOS transistor Q5 and the load respectively;

[0021] The other end of the capacitor C5 is grounded.

[0022] Furthermore, the switch sub-circuit includes a PMOS transistor Q2, a resistor R1 and a transistor Q1, wherein:

[0023] The source of the PMOS transistor Q2 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R1 respectively;

[0024] The drain of the PMOS tube Q2 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load;

[0025] The gate of the PMOS tube Q2 is electrically connected to the switch delay sub-circuit;

[0026] The other end of the resistor R1 is electrically connected to the collector of the transistor and the switch delay sub-circuit respectively;

[0027] The base of the transistor is electrically connected to the controller;

[0028] The emitter of the transistor is grounded.

[0029] Furthermore, the switch delay sub-circuit includes a resistor R2 and a capacitor C1, wherein:

[0030] One end of the resistor R2 is electrically connected to the other end of the resistor R1;

[0031] The other end of the resistor R2 is electrically connected to one end of the capacitor C1 and the gate of the PMOS transistor Q2 respectively;

[0032] The other end of the capacitor C1 is grounded.

[0033] Furthermore, a resistor is provided between the base of the transistor and the controller.

[0034] Furthermore, a resistor is provided between the base of the transistor and the emitter of the transistor.

[0035] Furthermore, it also includes a capacitor C2, wherein:

[0036] One end of the capacitor C2 is electrically connected to the drain of the PMOS transistor Q2 and the load respectively;

[0037] The other end of the capacitor C2 is grounded.

[0038] Furthermore, it also includes a capacitor C2, wherein:

[0039] One end of the capacitor C2 is electrically connected to the drain of the PMOS transistor Q2 and the load respectively;

[0040] The other end of the capacitor C2 is grounded.

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] This utility model is primarily used for optimizing the design of PMOS power switch application circuits within electronic products, preventing the front-stage circuit from instantaneously charging large capacitors or other loads in the back-stage circuit with large currents at the moment the power switch is switched. This can occur when the power is powered on too quickly and too quickly, causing the load to suddenly draw a very large current, thereby causing the front-stage circuit's power supply voltage to drop and causing system abnormalities. Through the circuit optimization design of this utility model, the power switch switching time can be extended, thereby reducing the instantaneous charging current, preventing the front-stage circuit's power supply voltage from dropping and affecting the normal operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a power switch circuit provided by an embodiment of the present utility model;

[0044] Figure 2 A circuit diagram of a power switch circuit provided by an embodiment of the present utility model;

[0045] Figure 3 The embodiment of the present invention provides Figure 2 Schematic diagram of the voltage waveform at the switching moment of the switch sub-circuit;

[0046] Figure 4 The embodiment of the present invention provides Figure 2 Schematic diagram of the voltage waveform at the switching moment after the switching sub-circuit in the figure is added with the switching delay sub-circuit;

[0047] Figure 5 A circuit diagram of another power switch circuit provided by an embodiment of the present utility model;

[0048] Figure 6 The embodiment of the present invention provides Figure 5 Schematic diagram of the voltage waveform at the switching moment of the switch sub-circuit;

[0049] Figure 7 The embodiment of the present invention provides Figure 5 Schematic diagram of the voltage waveform at the switching moment after the switching sub-circuit in the figure is added with the switching delay sub-circuit. DETAILED DESCRIPTION

[0050] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0051] In order to better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product size;

[0052] It is understandable to those skilled in the art that some well-known structures and descriptions thereof may be omitted in the drawings.

[0053] Example 1

[0054] This embodiment provides a power switch circuit, such as Figure 1 As shown, it includes a controller, a switch subcircuit and a switch delay subcircuit, wherein:

[0055] The power input terminal of the switch subcircuit is electrically connected to an external power supply, the power output terminal of the switch subcircuit is electrically connected to a load, and the control terminal of the switch subcircuit is electrically connected to the controller;

[0056] The switch delay sub-circuit is electrically connected to the switch sub-circuit.

[0057] In this embodiment, by setting a switch delay sub-circuit, the switching time of the power switch can be extended, thereby reducing the instantaneous charging current when the power switch is switched, solving the technical problem in the prior art that at the moment of switching the switch power, the load demands an instantaneous large current, thereby causing the power supply voltage of the previous circuit to drop.

[0058] In a preferred embodiment, a circuit diagram of a power switch circuit is as follows: Figure 2 As shown, the switch sub-circuit includes a PMOS tube Q5 and a resistor R4:

[0059] The source of the PMOS transistor Q5 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R4 respectively;

[0060] The drain of the PMOS transistor Q5 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load;

[0061] The gate of the PMOS tube Q5 is electrically connected to the switch delay sub-circuit;

[0062] The other end of the resistor R4 is electrically connected to the controller and the switch delay sub-circuit respectively.

[0063] In this embodiment, a PMOS transistor Q5 and a resistor R4 form a power switch control circuit. A controller controls the enable pin (i.e., the drain of the PMOS transistor Q5) to turn the PMOS transistor on and off. When the enable pin is low, the PMOS transistor Q5 is turned on, and the 5V_IN network (external power supply) and the 5V_OUT network (load) are connected. When the enable pin is high, the PMOS transistor Q5 is turned off, and the 5V_IN network and the 5V_OUT network are disconnected. This controls the power supply of the subsequent circuit, achieving a low-power circuit design.

[0064] However, in the above-mentioned switching subcircuit, when the PMOS tube Q5 is turned on, the front-stage circuit will instantly charge the large capacitor or other load of the back-stage circuit with a large current. Because the power supply is powered on too quickly and too quickly, the load is instantly powered on and will suddenly demand a very large current, causing the power supply voltage of the front-stage circuit to drop and the system to work abnormally. Waveform measurement is as follows Figure 3 shown.

[0065] Therefore, a switch delay subcircuit is used to extend the switching time of the power switch and reduce the instantaneous charging current, thereby solving the technical problem of the power supply voltage drop of the previous stage circuit.

[0066] In a further embodiment, the switch delay subcircuit includes a resistor R5 and a capacitor C3, wherein:

[0067] One end of the resistor R5 is electrically connected to the other end of the resistor R4;

[0068] The other end of the resistor R5 is electrically connected to one end of the capacitor C3 and the gate of the PMOS transistor Q5 respectively;

[0069] The other end of the capacitor C3 is grounded.

[0070] In this embodiment, the PMOS transistor Q5 is turned on and off by controlling the enable pin using a controller. When the enable pin is low, capacitor C3 discharges through resistor R5 and the controller's enable pin. During the discharge process of capacitor C3, the PMOS transistor Q5 slowly turns on, and the 5V_IN power network charges the large capacitor of the subsequent 5V_OUT power network. The discharge time of capacitor C3 can last for several milliseconds, which is enough for the large capacitor of the subsequent circuit to complete charging. Therefore, after the PMOS transistor Q5 is fully turned on, the 5V_IN network and the 5V_OUT network are connected. The subsequent load does not draw large current from the previous circuit, so the previous power network does not experience power drops, achieving a function similar to a power soft switch. When the enable pin is high, the PMOS transistor Q5 is not turned on, and the 5V_IN network and the 5V_OUT network are disconnected. This controls the power supply of the subsequent circuit and realizes the design of a low-power circuit.

[0071] like Figure 4 As shown, the switch sub-circuit in this embodiment cooperates with the switch delay sub-circuit to prevent the power supply voltage of the previous circuit from dropping and affecting the normal working state of the system. The waveform measurement diagram is shown in FIG. Figure 4 shown.

[0072] In a preferred embodiment, a capacitor C5 is further included, wherein:

[0073] One end of the capacitor C5 is electrically connected to the drain of the PMOS transistor Q5 and the load respectively;

[0074] The other end of the capacitor C5 is grounded.

[0075] Example 2

[0076] This embodiment provides a power switch circuit, such as Figure 1 As shown, it includes a controller, a switch subcircuit and a switch delay subcircuit, wherein:

[0077] The power input terminal of the switch subcircuit is electrically connected to an external power supply, the power output terminal of the switch subcircuit is electrically connected to a load, and the control terminal of the switch subcircuit is electrically connected to the controller;

[0078] The switch delay sub-circuit is electrically connected to the switch sub-circuit.

[0079] In this embodiment, by setting a switch delay sub-circuit, the switching time of the power switch can be extended, thereby reducing the instantaneous charging current when the power switch is switched, solving the technical problem in the prior art that at the moment of switching the switch power, the load demands an instantaneous large current, thereby causing the power supply voltage of the previous circuit to drop.

[0080] In another preferred embodiment, a circuit diagram of a power switch circuit is as follows: Figure 5 As shown, the switch sub-circuit includes a PMOS tube Q2, a resistor R1 and a transistor Q1:

[0081] The source of the PMOS transistor Q2 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R1 respectively;

[0082] The drain of the PMOS tube Q2 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load;

[0083] The gate of the PMOS tube Q2 is electrically connected to the switch delay sub-circuit;

[0084] The other end of the resistor R1 is electrically connected to the collector of the transistor and the switch delay sub-circuit respectively;

[0085] The base of the transistor is electrically connected to the controller;

[0086] The emitter of the transistor is grounded.

[0087] In this embodiment, a power switch control circuit is formed using a PMOS transistor Q2, a transistor Q1, and a resistor R1. A controller is used to control the enable pin (the drain of the PMOS transistor Q2) to turn the PMOS transistor Q2 on and off. When the enable pin is high, the transistor Q1 is turned on, the PMOS transistor Q2 is turned on, and the 5V_IN and 5V_OUT networks are connected. When the enable pin is low, the transistor Q1 is turned off, the PMOS transistor Q2 is turned off, and the 5V_IN and 5V_OUT networks are disconnected. This controls the power supply of the subsequent circuitry, achieving a low-power circuit design.

[0088] However, in the above-mentioned switching subcircuit, when the PMOS tube Q2 is turned on, the front-stage circuit will instantly charge the large capacitor or other load of the back-stage circuit with a large current. Because the power supply is powered on too quickly and too quickly, the load is instantly powered on and will suddenly demand a very large current, causing the power supply voltage of the front-stage circuit to drop and the system to work abnormally. Waveform measurement is as follows Figure 6 shown.

[0089] In a further embodiment, the switch delay subcircuit includes a resistor R2 and a capacitor C1, wherein:

[0090] One end of the resistor R2 is electrically connected to the other end of the resistor R1;

[0091] The other end of the resistor R2 is electrically connected to one end of the capacitor C1 and the gate of the PMOS transistor Q2 respectively;

[0092] The other end of the capacitor C1 is grounded.

[0093] In this embodiment, a controller is used to control the enable pin to turn PMOS transistor Q2 on and off. When the enable pin is high, capacitor C1 discharges through resistor R2 and transistor Q1. During the discharge process, PMOS transistor Q2 slowly turns on, and the 5V_IN power network charges the large capacitor of the subsequent 5V_OUT power network. The discharge time of capacitor C1 can last for several milliseconds, which is enough for the large capacitor of the subsequent circuit to complete charging. After PMOS transistor Q2 is fully turned on, the 5V_IN network and the 5V_OUT network are connected. The subsequent load does not draw large current from the previous circuit, so the previous power network does not experience power drops, achieving a function similar to a power soft switch. When the enable pin is low, the PMOS transistor is turned off, and the 5V_IN network and the 5V_OUT network are disconnected. This controls the power supply of the subsequent circuit and realizes the design of a low-power circuit.

[0094] like Figure 7As shown, the switch sub-circuit in this embodiment cooperates with the switch delay sub-circuit to prevent the power supply voltage of the previous circuit from dropping and affecting the normal working state of the system. The waveform measurement diagram is shown in FIG. Figure 4 shown.

[0095] In a further embodiment, a resistor is further provided between the base of the transistor and the controller.

[0096] In a specific embodiment, the resistance is set to 4.7k ohms.

[0097] In a further embodiment, a resistor is further provided between the base of the transistor and the emitter of the transistor.

[0098] In a specific embodiment, the resistance is set to 47k ohms.

[0099] In a further embodiment, a capacitor C2 is further included, wherein:

[0100] One end of the capacitor C2 is electrically connected to the drain of the PMOS transistor Q2 and the load respectively;

[0101] The other end of the capacitor C2 is grounded.

[0102] The same or similar reference numerals correspond to the same or similar components;

[0103] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;

[0104] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. A person skilled in the art will be able to make other variations or modifications based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A power switch circuit, characterized in that: It includes a controller, a switch subcircuit and a switch delay subcircuit, wherein: The power input terminal of the switch subcircuit is electrically connected to an external power supply, the power output terminal of the switch subcircuit is electrically connected to a load, and the control terminal of the switch subcircuit is electrically connected to the controller; The switch delay sub-circuit is electrically connected to the switch sub-circuit.

2. The power switch circuit according to claim 1, wherein: The switch sub-circuit includes a PMOS transistor Q5 and a resistor R4, wherein: The source of the PMOS transistor Q5 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R4 respectively; The drain of the PMOS transistor Q5 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load; The gate of the PMOS tube Q5 is electrically connected to the switch delay sub-circuit; The other end of the resistor R4 is electrically connected to the controller and the switch delay sub-circuit respectively.

3. The power switch circuit according to claim 2, wherein: The switch delay subcircuit includes a resistor R5 and a capacitor C3, wherein: One end of the resistor R5 is electrically connected to the other end of the resistor R4; The other end of the resistor R5 is electrically connected to one end of the capacitor C3 and the gate of the PMOS transistor Q5 respectively; The other end of the capacitor C3 is grounded.

4. The power switch circuit according to claim 2 or 3, characterized in that: Also included is capacitor C5, where: One end of the capacitor C5 is electrically connected to the drain of the PMOS transistor Q5 and the load respectively; The other end of the capacitor C5 is grounded.

5. The power switch circuit according to claim 1, wherein: The switch sub-circuit includes a PMOS transistor Q2, a resistor R1 and a transistor Q1, wherein: The source of the PMOS transistor Q2 serves as the power input terminal of the switch sub-circuit and is electrically connected to an external power supply and one end of the resistor R1 respectively; The drain of the PMOS tube Q2 serves as the power output terminal of the switch sub-circuit and is electrically connected to the load; The gate of the PMOS tube Q2 is electrically connected to the switch delay sub-circuit; The other end of the resistor R1 is electrically connected to the collector of the transistor and the switch delay sub-circuit respectively; The base of the transistor is electrically connected to the controller; The emitter of the transistor is grounded.

6. The power switch circuit according to claim 5, wherein: The switch delay subcircuit includes a resistor R2 and a capacitor C1, wherein: One end of the resistor R2 is electrically connected to the other end of the resistor R1; The other end of the resistor R2 is electrically connected to one end of the capacitor C1 and the gate of the PMOS transistor Q2 respectively; The other end of the capacitor C1 is grounded.

7. The power switch circuit according to claim 6, wherein: A resistor is further provided between the base of the transistor and the controller.

8. The power switch circuit according to claim 7, wherein: A resistor is further provided between the base of the transistor and the emitter of the transistor.

9. The power switch circuit according to claim 5, wherein: Also included is capacitor C2, where: One end of the capacitor C2 is electrically connected to the drain of the PMOS transistor Q2 and the load respectively; The other end of the capacitor C2 is grounded.

10. The power switch circuit according to any one of claims 5 to 8, characterized in that: Also included is capacitor C2, where: One end of the capacitor C2 is electrically connected to the drain of the PMOS transistor Q2 and the load respectively; The other end of the capacitor C2 is grounded.

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