Power factor correction circuit

Abstract

A power factor correction circuit includes: an AC power source; the first bridge arm comprises a first semiconductor device and a second semiconductor device which are connected in series; the second bridge arm is connected with the first bridge arm in parallel and comprises a third semiconductor device and a fourth semiconductor device which are connected in series; the third bridge arm is connected with the first bridge arm and the second bridge arm in parallel and comprises a first auxiliary diode and a second auxiliary diode which are connected in series, and the anode of the first auxiliary diode and the cathode of the second auxiliary diode are electrically connected to the first end of the alternating current power supply; the cathode of the first auxiliary diode is electrically connected to the first ends of the first semiconductor device and the third semiconductor device, and the anode of the second auxiliary diode is electrically connected to the second ends of the second semiconductor device and the fourth semiconductor device; the at least one first auxiliary capacitor is connected to the two ends of the third semiconductor device or the fourth semiconductor device in parallel; and the at least one second auxiliary capacitor is connected to the two ends of the first auxiliary diode or the second auxiliary diode in parallel.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, in particular to a power factor correction circuit. Background Art

[0002] Figure 1A A specific topology diagram of an existing power factor correction circuit is shown. The power factor correction circuit includes an AC power supply AC, a bidirectional switch S1, a first bridge arm and a second bridge arm. The first bridge arm includes a first diode D1 and a second diode D2 connected in series with each other, the second end of the first diode D1 is connected to the first end of the second diode D2 and is coupled to the first end of the AC power supply AC through a first inductor element L1; the second bridge arm is connected in parallel with the first bridge arm and includes a third diode D3 and a fourth diode D4 connected in series with each other, the second end of the third diode D3 is connected to the first end of the fourth diode D4 and the second end of the AC power supply; the first end of the bidirectional switch S1 is connected to the second end of the first diode D1 and the second end of the first inductor element L1, and the second end of the bidirectional switch S1 is connected to the first end of the fourth diode D4 and the second end of the AC power supply AC.

[0003] Figures 1B-1C for Figure 1A The equivalent schematic diagram of the power factor correction circuit shown in the figure is combined with Figures 1A-1C The power factor correction circuit also includes an output capacitor C1 and an output load R1. The output capacitor C1 and the output load R1 are respectively connected in parallel with the second bridge arm. When the load is relatively light, the energy stored in the inductor is small and is insufficient to turn on D1 and D4. At the same time, since D4 is not conducting, the voltage between points A and C jumps. Ca, Cb, and Cc are the parasitic capacitances of the jump points A, B, and C to the ground, respectively, which will cause common-mode noise.

[0004] like Figures 2A-2B As shown in the figure, Cd1, Cd2, Cd3, and Cd4 are the junction capacitances of D1, D2, D3, and D4, respectively. The equivalent junction capacitance of D4 is Cd3 + Cd4. A common solution to reducing common-mode noise is to connect a capacitor, Cadd, in parallel across D4. The capacitance of Cadd is much greater than the equivalent junction capacitance of D4, Cd3 + Cd4, resulting in a smaller voltage change across D4 and thus reducing common-mode noise. However, when the AC input is high voltage and lightly loaded, and bidirectional switch S1 is inoperative, the addition of Cadd causes the rectifier bridge formed by D1-D4 to become asymmetrical, creating a voltage doubling effect. This increases the bus voltage, exceeding the withstand voltage of the bus capacitors and damaging them.

[0005] Therefore, how to reduce the common-mode noise of the power factor correction circuit has become an urgent problem to be solved in this field. Utility Model Content

[0006] The purpose of this application is to provide a power factor correction circuit that can solve one or more defects of the prior art.

[0007] To achieve the above-mentioned objectives, the present invention provides a power factor correction circuit, comprising: an AC power supply having a first end and a second end; a first bridge arm comprising a first semiconductor device and a second semiconductor device connected in series with each other, the second end of the first semiconductor device being connected to the first end of the second semiconductor device and coupled to the first end of the AC power supply through a first inductor element; a second bridge arm connected in parallel with the first bridge arm, comprising a third semiconductor device and a fourth semiconductor device connected in series with each other, the second end of the third semiconductor device being connected to the first end of the fourth semiconductor device and the second end of the AC power supply; a third bridge arm connected in parallel with the first bridge arm and the second bridge arm, comprising a first auxiliary diode and a second auxiliary diode connected in series with each other, the anode of the first auxiliary diode and the cathode of the second auxiliary diode being electrically connected to the first end of the AC power supply, the cathode of the first auxiliary diode being electrically connected to the first end of the first semiconductor device and the first end of the third semiconductor device, and the anode of the second auxiliary diode being electrically connected to the second end of the second semiconductor device and the second end of the fourth semiconductor device; at least one first auxiliary capacitor connected in parallel to both ends of the third semiconductor device or both ends of the fourth semiconductor device; and at least one second auxiliary capacitor connected in parallel to both ends of the first auxiliary diode or both ends of the second auxiliary diode.

[0008] According to an embodiment of the present invention, the first auxiliary capacitor is connected in parallel to both ends of the third semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the second auxiliary diode.

[0009] According to an embodiment of the present invention, the first auxiliary capacitor is connected in parallel to both ends of the fourth semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode.

[0010] According to an embodiment of the present invention, the first auxiliary capacitor is connected in parallel to both ends of the third semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode.

[0011] According to an embodiment of the present invention, the first auxiliary capacitor is connected in parallel to both ends of the fourth semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the second auxiliary diode.

[0012] According to one embodiment of the present case, the power factor correction circuit includes two first auxiliary capacitors and two second auxiliary capacitors, the two first auxiliary capacitors are respectively connected in parallel to the two ends of the third semiconductor device and the two ends of the fourth semiconductor device, and the two second auxiliary capacitors are respectively connected in parallel to the two ends of the first auxiliary diode and the two ends of the second auxiliary diode.

[0013] According to an embodiment of the present invention, the capacitance of the first auxiliary capacitor is equal to the capacitance of the second auxiliary capacitor.

[0014] According to one embodiment of the present case, the power factor correction circuit further includes a bidirectional switch, wherein the first end of the bidirectional switch is connected to the second end of the first semiconductor device and the second end of the first inductor element, and the second end of the bidirectional switch is connected to the first end of the fourth semiconductor device and the second end of the AC power supply.

[0015] According to an embodiment of the present invention, the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are diodes.

[0016] According to an embodiment of the present invention, the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are switches.

[0017] In the power factor correction circuit provided in this case, the first auxiliary diode and the second auxiliary diode are connected in series to form a third bridge arm, the third semiconductor device and the fourth semiconductor device are connected in series to form a second bridge arm, and the second bridge arm and the third bridge arm form a rectifier bridge. By connecting the third semiconductor device or the fourth semiconductor device in parallel with the auxiliary capacitor in the second bridge arm, and connecting the first auxiliary diode or the second auxiliary diode in parallel with the auxiliary capacitor in the third bridge arm, the common-mode noise in the power factor correction circuit is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution implemented in this case, the following is a brief introduction to the drawings required for use in the embodiments.

[0019] Figure 1A A specific topology diagram of an existing power factor correction circuit;

[0020] Figures 1B-1C for Figure 1A The equivalent schematic diagram of the topological structure of the power factor correction circuit shown;

[0021] Figure 2A A specific topology diagram of another existing power factor correction circuit;

[0022] Figure 2B for Figure 2A The equivalent schematic diagram of the topological structure of the power factor correction circuit shown;

[0023] Figure 3A A topological diagram of a power factor correction circuit according to the first embodiment of the present invention;

[0024] Figure 3B for Figure 3A The equivalent schematic diagram of the topological structure of the power factor correction circuit shown;

[0025] Figure 3C is a voltage waveform diagram across the fourth semiconductor device;

[0026] Figure 3D for Figure 3A The simulation waveform diagram of the power factor correction circuit shown;

[0027] Figure 4A A topological diagram of a power factor correction circuit according to a second embodiment of the present invention;

[0028] Figure 4B for Figure 4A The equivalent schematic diagram of the topological structure of the power factor correction circuit shown;

[0029] Figure 4C is a voltage waveform diagram across the fourth semiconductor device;

[0030] Figure 4D for Figure 4A The simulation waveform diagram of the power factor correction circuit shown;

[0031] Figure 5 This is a topology diagram of a power factor correction circuit according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings, however, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this case will be thorough and complete and will fully and completely convey the concept of the example embodiments to those skilled in the art.

[0033] When introducing the elements / components / etc. described and / or illustrated herein, the terms "a", "an", "the", "" and "at least one" are used to indicate the presence of one or more elements / components / etc. The terms "comprising", "including" and "having" are used to indicate open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. In addition, the terms "first", "second", etc. in the claims are used only as labels and are not numerical limitations on their objects. The same numbers in the drawings represent the same or similar components. On the other hand, well-known components and steps are not described in the embodiments to avoid unnecessary limitations on the present disclosure. In addition, to simplify the drawings, some known and commonly used structures and elements will be depicted in a simple schematic manner in the drawings.

[0034] The power factor correction circuit of the utility model includes an AC power supply, a first bridge arm, a second bridge arm, a third bridge arm, at least one first auxiliary capacitor and at least one second auxiliary capacitor. The AC power supply has a first end and a second end; the first bridge arm includes a first semiconductor device and a second semiconductor device connected in series with each other, the second end of the first semiconductor device is connected to the first end of the second semiconductor device and is coupled to the first end of the AC power supply through a first inductor element; the second bridge arm is connected in parallel with the first bridge arm, including a third semiconductor device and a fourth semiconductor device connected in series with each other, the second end of the third semiconductor device is connected to the first end of the fourth semiconductor device and the second end of the AC power supply; the third bridge arm is connected in parallel with the first bridge arm and the second bridge arm, including a first auxiliary diode and a second auxiliary diode connected in series with each other, the anode of the first auxiliary diode and the cathode of the second auxiliary diode are electrically connected to the first end of the AC power supply, the cathode of the first auxiliary diode is electrically connected to the first end of the first semiconductor device and the first end of the third semiconductor device, and the anode of the second auxiliary diode is electrically connected to the second end of the second semiconductor device and the second end of the fourth semiconductor device; at least one first auxiliary capacitor is connected in parallel to both ends of the third semiconductor device or both ends of the fourth semiconductor device; and at least one second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode or both ends of the second auxiliary diode.

[0035] Figure 3A FIG. 1 is a schematic diagram of the topological structure of the power factor correction circuit 100 according to the first embodiment of the present invention. Figure 3AAs shown, the power factor correction circuit 100 includes an AC power source AC, a first bridge arm, a second bridge arm, a third bridge arm, a first auxiliary capacitor C3, and a second auxiliary capacitor C4. The AC power source AC has a first end and a second end; the first bridge arm includes a first semiconductor device D1 and a second semiconductor device D2 connected in series with each other, the second end of the first semiconductor device D1 is connected to the first end of the second semiconductor device D2 and is coupled to the first end of the AC power source AC through a first inductor element L1; the second bridge arm is connected in parallel with the first bridge arm, and includes a third semiconductor device D3 and a fourth semiconductor device D4 connected in series with each other, the second end of the third semiconductor device D3 is connected to the first end of the fourth semiconductor device D4 and the second end of the AC power source AC; the third bridge arm is connected in parallel with the first bridge arm and the second bridge arm. The first auxiliary diode D5 and the second auxiliary diode D6 are connected in series, the anode of the first auxiliary diode D5 and the cathode of the second auxiliary diode D6 are electrically connected to the first end of the alternating current power supply AC, the cathode of the first auxiliary diode D5 is electrically connected to the first end of the first semiconductor device D1 and the first end of the third semiconductor device D3, and the anode of the second auxiliary diode D6 is electrically connected to the second end of the second semiconductor device D2 and the second end of the fourth semiconductor device D4; the first auxiliary capacitor C3 is connected in parallel to the two ends of the fourth semiconductor device D4; the second auxiliary capacitor C4 is connected in parallel to the two ends of the first auxiliary diode D5.

[0036] Reference Figure 3A The third bridge arm formed by the first auxiliary diode D5 and the second auxiliary diode D6 connected in series is used to provide a path for surge current or lightning current. The first auxiliary diode D5, the second auxiliary diode D6, the third semiconductor device D3, and the fourth semiconductor device D4 form a rectifier bridge. For example, during the positive half-cycle, the surge current flows from the first end of the AC power supply AC through the first auxiliary diode D5, the output capacitor C1, and the fourth semiconductor device D4 to the second end of the AC power supply AC. During the negative half-cycle, the surge current flows from the second end of the AC power supply AC through the third semiconductor device D3, the output capacitor C1, and the second auxiliary diode D6 to the first end of the AC power supply AC.

[0037] Figure 3B for Figure 3A The equivalent schematic diagram of the topology of the power factor correction circuit is shown as Figure 3B As shown, the first auxiliary capacitor C3 is connected in parallel to both ends of the fourth semiconductor device D4, and the second auxiliary capacitor C4 is connected in parallel to both ends of the first auxiliary diode D5. The first auxiliary capacitor C3 and the second auxiliary capacitor C4 are equivalently connected in parallel to both ends of the fourth semiconductor device D4. Figure 3C is a voltage waveform diagram across the fourth semiconductor device, Figure 3D for Figure 3A The simulation waveform of the power factor correction circuit shown in the figure is combined with Figure 3C and Figure 3D , the voltage fluctuation across the fourth semiconductor device D4 is small, so the common-mode noise of the power factor correction circuit is small. At this time, the bus voltage Vout will reach a balance and be below its withstand voltage value.

[0038] The first auxiliary capacitor C3 is connected in parallel to both ends of the fourth semiconductor device D4, and the second auxiliary capacitor C4 is connected in parallel to both ends of the first auxiliary diode D5, which can effectively reduce the voltage jump across both ends of the fourth semiconductor device D4 and solve the common-mode noise problem caused by the failure of the third semiconductor device D3 and the fourth semiconductor device D4 to conduct when the load is light.

[0039] In this embodiment, the capacitance of the first auxiliary capacitor C3 is equal to that of the second auxiliary capacitor C4, so that the rectifier bridge formed by the first auxiliary diode D5, the second auxiliary diode D6 and the third semiconductor device D3 and the fourth semiconductor device D4 is symmetrical, thereby balancing the bus voltage.

[0040] Figure 4A FIG. 2 is a topological diagram of a power factor correction circuit 200 according to a second embodiment of the present invention. Figure 4A As shown, the power factor correction circuit 200 includes an AC power supply AC, a first bridge arm, a second bridge arm, a third bridge arm, a first auxiliary capacitor C3, and a second auxiliary capacitor C4. The topology of the power factor correction circuit 200 is substantially the same as that of the first embodiment, and the similarities are not repeated here. The difference is that the first auxiliary capacitor C3 is connected in parallel to both ends of the third semiconductor device D3, and the second auxiliary capacitor C4 is connected in parallel to both ends of the second auxiliary diode D6.

[0041] Figure 4B for Figure 4A The equivalent schematic diagram of the topology of the power factor correction circuit is shown as Figure 4B As shown, the first auxiliary capacitor C3 is connected in parallel to both ends of the third semiconductor device D3; the second auxiliary capacitor C4 is connected in parallel to both ends of the second auxiliary diode D6, and the first auxiliary capacitor C3 and the second auxiliary capacitor C4 are equivalently connected in parallel to both ends of the fourth semiconductor device D4. Figure 4C is a voltage waveform diagram across the fourth semiconductor device, Figure 4D for Figure 4A The simulation waveform of the power factor correction circuit shown in the figure is combined with Figure 4C and Figure 4D , the voltage fluctuation across the fourth semiconductor device D4 is small, so the common-mode noise of the power factor correction circuit is small. At this time, the bus voltage Vout will reach a balance and be below its withstand voltage value.

[0042] The first auxiliary capacitor C3 is connected in parallel to both ends of the third semiconductor device D3; the second auxiliary capacitor C4 is connected in parallel to both ends of the second auxiliary diode D6, which can effectively reduce the voltage jump across both ends of the fourth semiconductor device D4 and solve the common-mode noise problem caused by the failure of the third semiconductor device D3 and the fourth semiconductor device D4 to conduct when the load is light.

[0043] In this embodiment, the capacitance of the first auxiliary capacitor C3 is equal to that of the second auxiliary capacitor C4, so that the rectifier bridge formed by the first auxiliary diode D5, the second auxiliary diode D6 and the third semiconductor device D3 and the fourth semiconductor device D4 is symmetrical, thereby balancing the bus voltage.

[0044] In other embodiments, the topology of the power factor correction circuit is substantially the same as that of the first embodiment. However, the locations of the first auxiliary capacitor C3 and the second auxiliary capacitor C4 are not limited to those described in the first and second embodiments. For example, the first auxiliary capacitor C3 can be connected in parallel across the fourth semiconductor device D4 while the second auxiliary capacitor C4 is connected in parallel across the second auxiliary diode D6. Alternatively, the first auxiliary capacitor C3 can be connected in parallel across the third semiconductor device D3 while the second auxiliary capacitor C4 is connected in parallel across the first auxiliary diode D5. Preferably, the first auxiliary capacitor C3 and the second auxiliary capacitor C4 have equal capacitance.

[0045] Figure 5 FIG. 3 is a topological diagram of a power factor correction circuit 300 according to a third embodiment of the present invention. Figure 5 As shown, the power factor correction circuit 300 includes an AC power supply AC, a first bridge arm, a second bridge arm, a third bridge arm, two first auxiliary capacitors C3 and C5, and two second auxiliary capacitors C4 and C6. The topology of the power factor correction circuit 300 is roughly the same as that of the first embodiment, and the similarities are not repeated here. The difference is that the two first auxiliary capacitors C3 and C5 are connected in parallel to the third semiconductor device D3 and the fourth semiconductor device D4, respectively; the two second auxiliary capacitors C6 and C4 are connected in parallel to the first auxiliary diode D5 and the second auxiliary diode D6, respectively. The first auxiliary capacitors C3, C5 and the second auxiliary capacitors C4 and C6 are equivalently connected in parallel to the fourth semiconductor device D4, which can effectively reduce the voltage jump across the fourth semiconductor device D4 and solve the common-mode noise problem caused by the failure of the third semiconductor device D3 and the fourth semiconductor device D4 to conduct when the load is light.

[0046] In this embodiment, the capacitance of the first auxiliary capacitors C3 and C5 is equal to the capacitance of the second auxiliary capacitors C4 and C6, so that the rectifier bridge formed by the first auxiliary diode D5, the second auxiliary diode D6 and the third semiconductor device D3 and the fourth semiconductor device D4 is symmetrical, thereby balancing the bus voltage.

[0047] like Figure 3A 、 4A As shown in Figures 5 and 6, the power factor correction circuit further includes a bidirectional switch S1. A first end of the bidirectional switch S1 is connected to the second end of the first semiconductor device D1 and the second end of the first inductor L1. A second end of the bidirectional switch S1 is connected to the first end of the fourth semiconductor device D4 and the second end of the AC power source AC. The first semiconductor device D1, the second semiconductor device D2, the third semiconductor device D3, and the fourth semiconductor device D4 are diodes.

[0048] In other embodiments, the power factor correction circuit may not include the bidirectional switch S1, and the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are switches, such as MOSFET, GaN, or SiC.

[0049] In the power factor correction circuit provided in this case, the first auxiliary diode and the second auxiliary diode are connected in series to form a third bridge arm, the third semiconductor device and the fourth semiconductor device are connected in series to form a second bridge arm, and the second bridge arm and the third bridge arm form a rectifier bridge. By connecting the third semiconductor device or the fourth semiconductor device in parallel with the auxiliary capacitor in the second bridge arm, and connecting the first auxiliary diode or the second auxiliary diode in parallel with the auxiliary capacitor in the third bridge arm, the common-mode noise in the power factor correction circuit is effectively reduced.

[0050] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of protection of the present invention shall be based on the scope defined by the appended claims.

Claims

1. A power factor correction circuit, characterized in that: include: An AC power source having a first terminal and a second terminal; a first bridge arm comprising a first semiconductor device and a second semiconductor device connected in series, wherein the second end of the first semiconductor device is connected to the first end of the second semiconductor device and coupled to the first end of the AC power supply via a first inductor; a second bridge arm connected in parallel with the first bridge arm, comprising a third semiconductor device and a fourth semiconductor device connected in series, wherein the second end of the third semiconductor device is connected to the first end of the fourth semiconductor device and the second end of the AC power supply; a third bridge arm connected in parallel with the first bridge arm and the second bridge arm, comprising a first auxiliary diode and a second auxiliary diode connected in series, wherein an anode of the first auxiliary diode and a cathode of the second auxiliary diode are electrically connected to a first terminal of the AC power supply, a cathode of the first auxiliary diode is electrically connected to a first terminal of the first semiconductor device and a first terminal of the third semiconductor device, and an anode of the second auxiliary diode is electrically connected to a second terminal of the second semiconductor device and a second terminal of the fourth semiconductor device; at least one first auxiliary capacitor connected in parallel to both ends of the third semiconductor device or both ends of the fourth semiconductor device; and At least one second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode or both ends of the second auxiliary diode.

2. The power factor correction circuit according to claim 1, characterized in that: The first auxiliary capacitor is connected in parallel to both ends of the third semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the second auxiliary diode.

3. The power factor correction circuit according to claim 1, wherein: The first auxiliary capacitor is connected in parallel to both ends of the fourth semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode.

4. The power factor correction circuit according to claim 1, wherein: The first auxiliary capacitor is connected in parallel to both ends of the third semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the first auxiliary diode.

5. The power factor correction circuit according to claim 1, characterized in that: The first auxiliary capacitor is connected in parallel to both ends of the fourth semiconductor device, and the second auxiliary capacitor is connected in parallel to both ends of the second auxiliary diode.

6. The power factor correction circuit according to claim 1, characterized in that: The power factor correction circuit includes two first auxiliary capacitors and two second auxiliary capacitors, the two first auxiliary capacitors are respectively connected in parallel to the two ends of the third semiconductor device and the two ends of the fourth semiconductor device, and the two second auxiliary capacitors are respectively connected in parallel to the two ends of the first auxiliary diode and the two ends of the second auxiliary diode.

7. The power factor correction circuit according to any one of claims 1 to 6, characterized in that: The capacitance of the first auxiliary capacitor is equal to the capacitance of the second auxiliary capacitor.

8. The power factor correction circuit according to claim 1, wherein: The power factor correction circuit also includes a bidirectional switch, a first end of the bidirectional switch is connected to the second end of the first semiconductor device and the second end of the first inductor element, and a second end of the bidirectional switch is connected to the first end of the fourth semiconductor device and the second end of the AC power supply.

9. The power factor correction circuit according to claim 8, characterized in that: The first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are diodes.

10. The power factor correction circuit according to claim 1, wherein: The first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are switches.

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