Amplification circuit capable of adjusting gain

Abstract

The utility model relates to the technical field of operational amplification circuits, in particular to an amplification circuit capable of adjusting gain. Comprising an MCU-AD sampling end, a first filter circuit, a resistor R2, a power supply filter circuit, an operational amplifier U1A, a negative power supply BAT-end, a first adjustable gain circuit, a second adjustable gain circuit, a third adjustable gain circuit, a second filter circuit and an amplified signal, and the MCU-AD sampling end is sequentially connected with the resistor R2; in the gain-adjustable amplifying circuit, the first adjustable gain circuit, the second adjustable gain circuit and the third adjustable gain circuit are arranged on the operational amplifier U1A, so that the functions of simplifying the operational amplifying circuit and adjusting the amplification factor of the operational amplifying circuit in an increased or decreased manner are realized; the effects of flexible gain adjustment and signal amplification are achieved by adjusting different resistor paths under the condition that a boost chip is not used.

Description

Technical Field

[0001] The utility model relates to the technical field of operational amplifier circuits, in particular to an amplifier circuit with adjustable gain. Background Art

[0002] The rapid development of the new energy vehicle industry has placed higher demands on electronic control systems, particularly in signal processing and power management. Operational amplifier circuits, as core components for signal conditioning and processing, are widely used in new energy vehicles. However, existing operational amplifier circuits often face challenges in practical applications, including complex design, numerous components, high cost, and large size. Some operational amplifier circuits also have fixed amplification factors that cannot be flexibly adjusted according to actual needs, and the amplification factor cannot be increased or decreased, impacting detection control accuracy, signal authenticity, and subsequent processing.

[0003] For example, application number CN201920312470.X discloses an automatically adjustable variable gain amplifier circuit, which includes an input impedance matching circuit, a negative feedback control voltage conversion circuit, a main operational amplifier circuit and an output matching circuit. The input impedance matching circuit realizes the frequency band selection of the variable gain amplifier circuit and meets the input matching requirements within the frequency band: the negative feedback control voltage conversion circuit converts the control voltage with a larger output variation range into a voltage with a smaller variation range to achieve adjustable gain, and the operational amplifier circuit provides the open-loop gain of the circuit to achieve signal amplification, and the output matching circuit realizes output impedance matching within the frequency band received by the variable gain amplifier circuit to expand the gain bandwidth. However, the negative feedback control voltage conversion circuit has a limited gain adjustment range and is easily affected by external factors such as temperature changes and power supply fluctuations, resulting in gain drift or instability.

[0004] The variable gain amplifier circuit disclosed in the above utility model patent has the problem that it is unable to reduce the amplification factor when needed during the amplification process, resulting in excessive signal amplification, saturation distortion, and inability to meet the changing signal processing requirements. Therefore, the present application proposes an amplifier circuit with adjustable gain, which solves the above problems while not using a boost chip, so that the power supply module can operate stably within a wide voltage range without affecting the circuit function. Utility Model Content

[0005] The purpose of the present invention is to provide an amplifier circuit with adjustable gain to solve the technical problems mentioned in the above background technology.

[0006] In order to achieve the above-mentioned purpose, the utility model discloses an amplifier circuit with adjustable gain, including an MCU-AD sampling terminal, a first filtering circuit, a resistor R2, a power supply filtering circuit, an operational amplifier U1A, a negative power supply BAT-terminal, a first adjustable gain circuit, a second adjustable gain circuit, a third adjustable gain circuit, a second filtering circuit and an amplified signal, and the MCU-AD sampling terminal is sequentially connected in series with the resistor R2 and the output terminal of pin 6 of the operational amplifier U1A, wherein the operational amplifier U1A includes 8 pins, namely the output terminal of pin 6, the negative power supply terminal of pin 4, the reverse input terminal of pin 2, the non-reverse input terminal of pin 3 and the positive power supply terminal of pin 8, as well as the offset idle terminals of pins 1 and 5 and the strobe terminal of pin 7, and the power supply filtering circuit is connected to the positive power supply terminal of pin 8 of the operational amplifier U1A for filtering the negative power supply terminal through the power supply filtering circuit. The circuit provides power to the operational amplifier U1A, the negative power supply terminal of pin 4 of the operational amplifier U1A is connected to the negative power supply BAT-terminal, the first filtering circuit is topologically connected between the MCU-AD sampling terminal and the resistor R2, the non-inverting input terminal of pin 3 of the operational amplifier U1A is connected in series with the first adjustable gain circuit, the second adjustable gain circuit is connected in series between the inverting input terminal of pin 2 of the operational amplifier U1A and the output terminal of pin 6 of the operational amplifier U1A, the third adjustable gain circuit is topologically connected in series between the other end of the second adjustable gain circuit and the inverting input terminal of pin 2 of the operational amplifier U1A, the amplified signal is connected between the first adjustable gain circuit and the third adjustable gain circuit, and the second filtering circuit is connected in parallel at both ends of the amplified signal.

[0007] Optionally, the first filtering circuit includes a capacitor C2 and a ground terminal BAT-, and one end of the capacitor C2 and the ground terminal BAT- are connected in series, and the other end of the capacitor C2 is topologically connected between the MCU-AD sampling terminal and the first filtering circuit;

[0008] The power supply filter circuit includes a 5V power supply terminal, a capacitor C1, and a ground BAT-terminal, and the 5V power supply terminal is sequentially connected in series with the capacitor C1 and the ground BAT-terminal, and is located between the 5V power supply terminal and the capacitor C1 and topologically connected to the positive power supply terminal of pin 8 of the operational amplifier U1A;

[0009] The second filtering circuit includes a capacitor C3 and a ground terminal BAT-, and one end of the capacitor C3 and the ground terminal BAT- are connected in series. The other end of the capacitor C3 is topologically connected between the first adjustable gain circuit and the amplified signal. The capacitor C3 and the ground terminal BAT- are topologically intersected between the third adjustable gain circuit and the amplified signal.

[0010] Optionally, the first adjustable gain circuit includes a non-inverting input terminal resistor R1, a resistor R3 and an MCU-controlled switch S1, and the resistor R2 and the MCU-controlled switch S1 are connected in series to form an adjustment circuit, and then connected in parallel to the two ends of the non-inverting input terminal resistor R1. By controlling the switch of the MCU-controlled switch S1, the resistor R3 is controlled to be connected in parallel with the non-inverting input terminal resistor R1 to the input loop, which is used to adjust the value of the input non-inverting input terminal resistor R1 to change the input impedance of the operational amplifier U1A and affect the gain, that is, when the MCU-controlled switch S1 is closed, the resistor R3 is not connected, and the input impedance is the resistance value of the non-inverting input terminal resistor R1. When the MCU-controlled switch S1 is turned on, the resistor R3 is connected, and the input impedance becomes the resistance value of the non-inverting input terminal resistor R1 in parallel with the resistor R3;

[0011] The second adjustable gain circuit includes a resistor R4, a resistor R7, and an MCU-controlled switch S3. The resistor R7 and the MCU-controlled switch S3 are connected in series to form an adjustment circuit and then connected in parallel to the two ends of the resistor R4. By controlling the switch of the MCU-controlled switch S3, the resistor R7 is controlled to be connected in parallel with the resistor R4 to the input loop, which is used to adjust the value of the feedback resistor R4 to change the gain of the operational amplifier U1A. When the MCU-controlled switch S3 is closed, the resistor R7 is not connected, the feedback resistor is the resistance value of R4, and the gain is low. When the MCU-controlled switch S3 is opened, the resistor R7 is connected, the feedback resistor becomes the resistance value of the resistor R4 in parallel with the resistor R7, and the gain is improved.

[0012] The third adjustable gain circuit includes an inverting input resistor R5, a resistor R6, and an MCU-controlled switch S2. The resistor R6 and the MCU-controlled switch S2 are connected in series to form an adjustment circuit, and then connected in parallel to the two ends of the inverting input resistor R5. By controlling the switch of the MCU-controlled switch S2, the resistor R6 is controlled to be connected in parallel with the inverting input resistor R5 to the input loop, which is used to adjust the value of the feedback inverting input resistor R5 to change the gain of the operational amplifier U1A. When the MCU-controlled switch S2 is closed, the resistor R6 is not connected, and the feedback resistor is the resistance value of R5. When the MCU-controlled switch S2 is turned on, the resistor R6 is connected, and the feedback resistor becomes the resistance value of the inverting input resistor R5 in parallel with the resistor R6, affecting the gain and feedback characteristics of the circuit.

[0013] Optionally, one end of the MCU-controlled switch S3 is connected between the resistor R2 and the output end of pin 6 of the operational amplifier U1A, one end of the resistor R7 is connected to the inverting input end of pin 2 of the operational amplifier U1A, one end of the resistor R4 is connected to one end of the MCU-controlled switch S3, and the other end of the resistor R4 is connected between the resistor R7 and the inverting input end of pin 2 of the operational amplifier U1A;

[0014] The two ends of the non-inverting input resistor R1 are respectively connected to the non-inverting input end of pin 3 of the operational amplifier U1A and one end of the amplified signal, one end of the resistor R3 is connected between the non-inverting input end of pin 3 of the operational amplifier U1A and the non-inverting input resistor R1, and one end of the MCU control switch S1 is connected between the non-inverting input resistor R1 and one end of the amplified signal;

[0015] The resistor R4 intersects at a node between the resistor R7 and the inverting input terminal of pin 2 of the operational amplifier U1A, and is topologically connected to one end of the inverting input terminal resistor R5. The other end of the inverting input terminal resistor R5 is connected to the other end of the amplified signal, and one end of the resistor R6 is connected between the resistor R4 and the inverting input terminal resistor R5. One end of the MCU control switch S2 is connected between the inverting input terminal resistor R5 and the other end of the amplified signal.

[0016] Optionally, the resistance of the in-phase input resistor R1 is equal to the resistance of the inverting input resistor R5, both are 10kΩ, with an accuracy of 1%, and are used to set the input impedance and limit the input current. The resistance of the resistor R3 is equal to the resistance of the resistor R6 and the resistor R7, both are 10kΩ, with an accuracy of 1%, and are used to adjust the input impedance through the MCU controlling the switch S1 in parallel at both ends of R1, and to adjust the impedance of the input signal end through the MCU controlling the switch S2 in parallel at both ends of the resistor R5, and to adjust the feedback resistance through the MCU controlling the switch S3 in parallel at both ends of R4 to change the gain of the operational amplifier U1A, and the resistor R4 is an adjustable resistor, and the resistance of the resistor R4 is 10-20 times that of the inverting input resistor R5, and is used to increase the amplification factor. The resistance of the resistor R2 is 1kΩ, with an accuracy of 1%, and is used to be connected in series in the output sampling circuit to ensure the accuracy of the sampling signal.

[0017] Optionally, the capacitance of the capacitor C1 is 100 μF and the withstand voltage is 50 V, and it is used to remove high-frequency noise in the 5V power supply voltage; the capacitance of the capacitor C2 is 10 nF and the withstand voltage is 50 V, and it is used to filter noise in the signal; the capacitance of the capacitor C3 is 1 μF and the withstand voltage is 50 V, and it is used to filter noise in the amplified signal.

[0018] Optionally, the amplification factor calculation of the amplifier circuit includes Formula 1: when the MCU control switch S1, the MCU control switch S2, and the MCU control switch S3 are all disconnected, the amplification factor of the amplifier circuit N=R4 / R5, where N represents the amplification factor, R4 represents the resistance value of the resistor R4, R5 represents the resistance value of the inverting input terminal resistor R5, and / represents a division sign;

[0019] Formula 2: When the MCU control switch S1 is closed and the MCU control switches S2 and S3 are open, the amplification factor of the amplifier circuit is N = (R4||R7) / R5, where R4||R7 represents the sum of the resistances of resistors R4 and R7 in parallel, and / / represents a parallel relationship.

[0020] Formula 3: When the MCU control switch S1 is open and the MCU control switches S2 and S3 are closed, the amplification factor of the amplifier circuit is N = R4 / (R5|R6), where R5|R6 represents the sum of the resistances of the inverting input resistor R5 and the parallel resistor R6.

[0021] Compared with the prior art, the utility model has the following advantages:

[0022] In this gain-adjustable amplifier circuit, by setting the structure of the first adjustable gain circuit, the second adjustable gain circuit and the third adjustable gain circuit on the operational amplifier U1A, the operational amplifier circuit is simplified, and the function of increasing or decreasing the amplification factor of the operational amplifier circuit is achieved. Without using a boost chip, the effect of flexible gain adjustment and signal amplification is achieved by adjusting different resistance paths. By setting the structure of the first filter circuit, the power supply filter circuit and the second filter circuit, the function of improving the signal-to-noise ratio of the signal is achieved, ensuring the purity and stability of the signal, further improving the performance of the operational amplifier, making it have higher flexibility and adaptability, and suitable for various signal processing and power management applications in the new energy vehicle industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic structural diagram of the gain-adjustable amplifier circuit of the present invention.

[0024] The figures are marked as follows: 1. MCU-AD sampling terminal; 2. First filtering circuit; 3. Resistor R2; 4. Power supply filtering circuit; 5. Operational amplifier U1A; 6. Negative power supply BAT-terminal; 7. First adjustable gain circuit; 8. Second adjustable gain circuit; 9. Third adjustable gain circuit; 10. Second filtering circuit; Amplified signal 11. Amplified signal. DETAILED DESCRIPTION

[0025] The technical solution of the present utility model is described in detail below through specific embodiments.

[0026] Reference Figure 1 As shown, the utility model discloses an adjustable gain amplifier circuit structure, including an MCU-AD sampling terminal 1, a first filter circuit 2, a resistor R23, a power supply filter circuit 4, an operational amplifier U1A5, a negative power supply BAT-terminal 6, a first adjustable gain circuit 7, a second adjustable gain circuit 8, a third adjustable gain circuit 9, a second filter circuit 10 and an amplified signal 11, and the MCU-AD sampling terminal 1 is sequentially connected in series with the resistor R23 and the output terminal of pin 6 of the operational amplifier U1A5, wherein the operational amplifier U1A5 includes 8 pins, namely the output terminal of pin 6, the negative power supply terminal of pin 4, the reverse input terminal of pin 2, the non-reverse input terminal of pin 3 and the positive power supply terminal of pin 8, as well as the offset idle terminals of pins 1 and 5 and the strobe terminal of pin 7, the power supply filter circuit 4 is connected to the positive power supply terminal of pin 8 of the operational amplifier U1A5, and the output terminal of pin 8 is connected in series with the resistor R23 and the output terminal of pin 6 of the operational amplifier U1A5. The operational amplifier U1A5 is powered by the power filter circuit 4. The negative power supply terminal of pin 4 of the operational amplifier U1A5 is connected to the negative power supply BAT-terminal 6. The first filter circuit 2 is topologically connected between the MCU-AD sampling terminal 1 and the resistor R23. The non-inverting input terminal of pin 3 of the operational amplifier U1A5 is connected in series with the first adjustable gain circuit 7. The second adjustable gain circuit 8 is connected in series between the inverting input terminal of pin 2 of the operational amplifier U1A5 and the output terminal of pin 6 of the operational amplifier U1A5. The third adjustable gain circuit 9 is topologically connected in series between the other end of the second adjustable gain circuit 8 and the inverting input terminal of pin 2 of the operational amplifier U1A5. The amplified signal 11 is connected between the first adjustable gain circuit 7 and the third adjustable gain circuit 9, and the second filter circuit 10 is connected in parallel at both ends of the amplified signal 11.

[0027] Preferably, the first filtering circuit 2 includes a capacitor C2 and a ground terminal BAT-, and one end of the capacitor C2 is connected in series with the ground terminal BAT-, and the other end of the capacitor C2 is topologically connected between the MCU-AD sampling terminal 1 and the first filtering circuit 2;

[0028] The power supply filter circuit 4 includes a 5V power supply terminal, a capacitor C1, and a ground BAT-terminal, and the 5V power supply terminal is sequentially connected in series with the capacitor C1 and the ground BAT-terminal, and is located between the 5V power supply terminal and the capacitor C1 and topologically connected to the positive power supply terminal of pin 8 of the operational amplifier U1A5;

[0029] The second filter circuit 10 includes a capacitor C3 and a ground terminal BAT-, with one end of the capacitor C3 and the ground terminal BAT- connected in series. The other end of the capacitor C3 is topologically connected between the first adjustable gain circuit 7 and the amplified signal 11. The capacitor C3 and the ground terminal BAT- are topologically intersected between the third adjustable gain circuit 9 and the amplified signal 11.

[0030] Preferably, the first adjustable gain circuit 7 includes a non-inverting input terminal resistor R1, a resistor R3, and an MCU-controlled switch S1, and the resistor R2 and the MCU-controlled switch S1 are connected in series to form an adjustment circuit, and then connected in parallel to both ends of the non-inverting input terminal resistor R1. By controlling the switch of the MCU-controlled switch S1, the resistor R3 is controlled to be connected in parallel with the non-inverting input terminal resistor R1 to the input loop, which is used to adjust the value of the input non-inverting input terminal resistor R1 to change the input impedance of the operational amplifier U1A5 and affect the gain. That is, when the MCU-controlled switch S1 is closed, the resistor R3 is not connected, and the input impedance is the resistance value of the non-inverting input terminal resistor R1. When the MCU-controlled switch S1 is opened, the resistor R3 is connected, and the input impedance becomes the resistance value of the non-inverting input terminal resistor R1 in parallel with the resistor R3.

[0031] The second adjustable gain circuit 8 includes a resistor R4, a resistor R7, and an MCU-controlled switch S3. The resistor R7 and the MCU-controlled switch S3 are connected in series to form an adjustment circuit and then connected in parallel to the two ends of the resistor R4. By controlling the on / off of the MCU-controlled switch S3, the resistor R7 is controlled to be connected in parallel with the resistor R4 to the input loop, which is used to adjust the value of the feedback resistor R4 to change the gain of the operational amplifier U1A5. When the MCU-controlled switch S3 is closed, the resistor R7 is not connected, the feedback resistor is the resistance value of R4, and the gain is low. When the MCU-controlled switch S3 is opened, the resistor R7 is connected, and the feedback resistor becomes the resistance value of the resistor R4 in parallel with the resistor R7, thereby increasing the gain.

[0032] The third adjustable gain circuit 9 includes an inverting input resistor R5, a resistor R6, and an MCU-controlled switch S2. The resistor R6 and the MCU-controlled switch S2 are connected in series to form an adjustment circuit and then connected in parallel to the two ends of the inverting input resistor R5. By controlling the switch of the MCU-controlled switch S2, the resistor R6 is controlled to be connected in parallel with the inverting input resistor R5 to the input loop, which is used to adjust the value of the feedback inverting input resistor R5 to change the gain of the operational amplifier U1A5. When the MCU-controlled switch S2 is closed, the resistor R6 is not connected, and the feedback resistor is the resistance value of R5. When the MCU-controlled switch S2 is turned on, the resistor R6 is connected, and the feedback resistor becomes the resistance value of the inverting input resistor R5 in parallel with the resistor R6, which affects the gain and feedback characteristics of the circuit.

[0033] Preferably, one end of the MCU-controlled switch S3 is connected between the resistor R23 and the output terminal of pin 6 of the operational amplifier U1A5, one end of the resistor R7 is connected to the inverting input terminal of pin 2 of the operational amplifier U1A5, one end of the resistor R4 is connected to one end of the MCU-controlled switch S3, and the other end of the resistor R4 is connected between the resistor R7 and the inverting input terminal of pin 2 of the operational amplifier U1A5;

[0034] The two ends of the non-inverting input resistor R1 are respectively connected to the non-inverting input terminal of pin 3 of the operational amplifier U1A5 and one end of the amplified signal 11. One end of the resistor R3 is connected between the non-inverting input terminal of pin 3 of the operational amplifier U1A5 and the non-inverting input resistor R1. One end of the MCU-controlled switch S1 is connected between the non-inverting input resistor R1 and one end of the amplified signal 11.

[0035] Resistor R4 intersects at a node between resistor R7 and the inverting input terminal of pin 2 of operational amplifier U1A5, and is topologically connected to one end of the inverting input terminal resistor R5. The other end of the inverting input terminal resistor R5 is connected to the other end of the amplified signal 11, and one end of resistor R6 is connected between resistor R4 and the inverting input terminal resistor R5. One end of the MCU control switch S2 is connected between the inverting input terminal resistor R5 and the other end of the amplified signal 11.

[0036] Preferably, the resistance of the resistor R1 at the in-phase input end is equal to the resistance of the resistor R5 at the inverting input end, both are 10kΩ, with an accuracy of 1%, and are used to set the input impedance, limit the input current, and ensure the stability of the input signal. The resistance of the resistor R3 is equal to the resistance of the resistor R6 and the resistor R7, both are 10kΩ, with an accuracy of 1%, and are used to adjust the input impedance by controlling the switch S1 in parallel at both ends of R1 through the MCU, adjust the impedance of the input signal end by controlling the switch S2 in parallel at both ends of the resistor R5 through the MCU, and adjust the feedback resistance by controlling the switch S3 in parallel at both ends of R4 through the MCU to change the gain of the operational amplifier U1A5. The resistor R4 is an adjustable resistor, and the resistance of the resistor R4 is 10-20 times that of the inverting input end resistor R5, and is used to increase the amplification factor. The resistance of the resistor R23 is 1kΩ, with an accuracy of 1%, and is used to be connected in series in the output sampling circuit to ensure the accuracy of the sampling signal and limit the output current.

[0037] Preferably, the capacitance of capacitor C1 is 100μF and the withstand voltage is 50V, which is used for power supply filtering to remove high-frequency noise in the 5V power supply voltage. The capacitance of capacitor C2 is 10nF and the withstand voltage is 50V, which is used to filter noise in the signal to ensure signal stability. The capacitance of capacitor C3 is 1μF and the withstand voltage is 50V, which is used to filter noise in the amplified signal 11 to improve signal quality.

[0038] Preferably, the amplification factor calculation of the amplifier circuit includes Formula 1: When the MCU control switch S1, the MCU control switch S2, and the MCU control switch S3 are all disconnected, the amplification factor of the amplifier circuit is N=R4 / R5, where N represents the amplification factor, R4 represents the resistance value of the resistor R4, R5 represents the resistance value of the inverting input terminal resistor R5, and / represents a division sign;

[0039] Formula 2: When the MCU control switch S1 is closed and the MCU control switches S2 and S3 are open, the amplification factor of the amplifier circuit is N = R4||R7 / R5, where R4||R7 represents the sum of the resistances of resistors R4 and R7 in parallel, and / / represents a parallel relationship.

[0040] Formula 3: When the MCU control switch S1 is open and the MCU control switches S2 and S3 are closed, the amplification factor of the amplifier circuit is N = R4 / R5|R6, where R5|R6 represents the sum of the resistances of the inverting input resistor R5 in parallel with the resistor R6.

[0041] Working principle: By opening or closing the combination of MCU control switch S1, MCU control switch S2, and MCU control switch S3, different resistance paths are switched to adjust the feedback resistance value to change the gain of the operational amplifier U1A5. First, the amplified signal 11 is input into the non-inverting input terminal of pin 3 of the operational amplifier U1A5 through the non-inverting input terminal resistor R1, and is connected to the ground BAT- terminal through the inverting input terminal resistor R5, and filtered by capacitor C3; then it is switched through MCU control switch S1, MCU control switch S2, and MCU control switch S3. Different feedback resistance paths are used to adjust the gain. For example, resistor R6 is connected in parallel with or disconnected from the inverting input resistor R5 by controlling the MCU to close or open switch S2, thereby adjusting the size of the inverting input resistor R5 of the operational amplifier. Resistor R3 is connected in parallel with or disconnected from the non-inverting input resistor R1 by controlling the MCU to close or open switch S1, thereby adjusting the size of the non-inverting input resistor R1 of the operational amplifier. Resistor R7 is connected in parallel with or disconnected from the resistor R4 by controlling the MCU to close or open switch S3, thereby adjusting the size of the feedback resistor R4 of the operational amplifier.

[0042] Finally, the operational amplifier U1A5 amplifies the input amplified signal 11 according to the gain set by the feedback network. The amplified signal is output through the pin 6 output terminal of the operational amplifier U1A5 and connected to the MCU-AD sampling terminal 1 through the resistor R23 for sampling and processing.

[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the design concept of the present invention should be included in the scope of protection of the present invention.

Claims

1. An amplifier circuit with adjustable gain, characterized in that: The invention comprises an MCU-AD sampling terminal (1), a first filtering circuit (2), a resistor R2 (3), a power filtering circuit (4), an operational amplifier U1A (5), a negative power supply BAT-terminal (6), a first adjustable gain circuit (7), a second adjustable gain circuit (8), a third adjustable gain circuit (9), a second filtering circuit (10) and an amplified signal (11), wherein the MCU-AD sampling terminal (1) is sequentially connected in series with the resistor R2 (3) and the output terminal of the pin 6 of the operational amplifier U1A (5), the power filtering circuit (4) is connected to the positive power supply terminal of the pin 8 of the operational amplifier U1A (5), the negative power supply terminal of the pin 4 of the operational amplifier U1A (5) is connected to the negative power supply BAT-terminal (6), and is located between the MCU-AD sampling terminal (1) and the resistor R2 ( 3), the first filter circuit (2) is topologically connected between the non-inverting input terminal of pin 3 of the operational amplifier U1A (5) and the first adjustable gain circuit (7) is connected in series, the second adjustable gain circuit (8) is connected in series between the inverting input terminal of pin 2 of the operational amplifier U1A (5) and the output terminal of pin 6 of the operational amplifier U1A (5), the third adjustable gain circuit (9) is topologically connected in series between the other end of the second adjustable gain circuit (8) and the inverting input terminal of pin 2 of the operational amplifier U1A (5), the amplified signal (11) is connected between the first adjustable gain circuit (7) and the third adjustable gain circuit (9), and the two ends of the amplified signal (11) are connected in parallel with the second filter circuit (10).

2. The gain-adjustable amplifier circuit according to claim 1, wherein: The first filter circuit (2) comprises a capacitor C2 and a ground BAT-terminal, wherein one end of the capacitor C2 and the ground BAT-terminal are connected in series, and the other end of the capacitor C2 is topologically connected between the MCU-AD sampling terminal (1) and the first filter circuit (2); The power supply filter circuit (4) includes a 5V power supply terminal, a capacitor C1 and a ground BAT-terminal, and the 5V power supply terminal is sequentially connected in series with the capacitor C1 and the ground BAT-terminal, and is located between the 5V power supply terminal and the capacitor C1 and is topologically connected to the positive power supply terminal of pin 8 of the operational amplifier U1A (5); The second filtering circuit (10) includes a capacitor C3 and a ground BAT-terminal, wherein one end of the capacitor C3 and the ground BAT-terminal are connected in series, the other end of the capacitor C3 is topologically connected between the first adjustable gain circuit (7) and the amplified signal (11), and the capacitor C3 and the ground BAT-terminal are topologically intersected between the third adjustable gain circuit (9) and the amplified signal (11).

3. The gain-adjustable amplifier circuit according to claim 2, wherein: The first adjustable gain circuit (7) comprises a common-mode input resistor R1, a resistor R3 and an MCU control switch S1, wherein the resistor R2 and the MCU control switch S1 are connected in series to form an adjustment circuit and then connected in parallel to both ends of the common-mode input resistor R1; The second adjustable gain circuit (8) comprises a resistor R4, a resistor R7 and an MCU controlled switch S3, wherein the resistor R7 and the MCU controlled switch S3 are connected in series to form an adjustment circuit and then connected in parallel to both ends of the resistor R4; The third adjustable gain circuit (9) comprises an inverting input terminal resistor R5, a resistor R6 and an MCU controlled switch S2, wherein the resistor R6 and the MCU controlled switch S2 are connected in series to form an adjustment circuit and then connected in parallel to both ends of the inverting input terminal resistor R5.

4. The gain-adjustable amplifier circuit according to claim 3, wherein: One end of the MCU control switch S3 is connected between the resistor R2 (3) and the output end of pin 6 of the operational amplifier U1A (5), one end of the resistor R7 is connected to the inverting input end of pin 2 of the operational amplifier U1A (5), one end of the resistor R4 is connected to one end of the MCU control switch S3, and the other end of the resistor R4 is connected between the resistor R7 and the inverting input end of pin 2 of the operational amplifier U1A (5); The two ends of the non-inverting input terminal resistor R1 are respectively connected to the non-inverting input terminal of pin 3 of the operational amplifier U1A (5) and one end of the amplified signal (11); one end of the resistor R3 is connected between the non-inverting input terminal of pin 3 of the operational amplifier U1A (5) and the non-inverting input terminal resistor R1; and one end of the MCU control switch S1 is connected between the non-inverting input terminal resistor R1 and one end of the amplified signal (11); The resistor R4 intersects the node between the resistor R7 and the inverting input terminal of pin 2 of the operational amplifier U1A (5), and is topologically connected to one end of the inverting input terminal resistor R5. The other end of the inverting input terminal resistor R5 is connected to the other end of the amplified signal (11). One end of the resistor R6 is connected between the resistor R4 and the inverting input terminal resistor R5. One end of the MCU control switch S2 is connected between the inverting input terminal resistor R5 and the other end of the amplified signal (11).

5. The gain-adjustable amplifier circuit according to claim 4, wherein: The resistance of the resistor R1 at the in-phase input terminal is equal to the resistance of the resistor R5 at the inverting input terminal, both of which are 10kΩ, with an accuracy of 1%. The resistance of the resistor R3 is equal to the resistance of the resistor R6 and the resistor R7, both of which are 10kΩ, with an accuracy of 1%. The resistor R4 is an adjustable resistor, and the resistance of the resistor R4 is 10-20 times that of the inverting input terminal resistor R5. The resistance of the resistor R2 (3) is 1kΩ, with an accuracy of 1%.

6. The gain-adjustable amplifier circuit according to claim 4, wherein: The capacitance of the capacitor C1 is 100 μF and the withstand voltage is 50 V. The capacitance of the capacitor C2 is 10 nF and the withstand voltage is 50 V. The capacitance of the capacitor C3 is 1 μF and the withstand voltage is 50 V.

7. The gain-adjustable amplifier circuit according to claim 4, wherein: The amplification factor calculation of the amplifier circuit includes Formula 1: When the MCU control switch S1, the MCU control switch S2 and the MCU control switch S3 are all disconnected, the amplification factor of the amplifier circuit is N=R4 / R5, where N represents the amplification factor, R4 represents the resistance value of the resistor R4, R5 represents the resistance value of the inverting input terminal resistor R5, and / represents a division sign; Formula 2: When the MCU control switch S1 is closed and the MCU control switches S2 and S3 are open, the amplification factor of the amplifier circuit is N = (R4||R7) / R5, where R4||R7 represents the sum of the resistances of resistors R4 and R7 in parallel, and / / represents a parallel relationship. Formula 3: When the MCU control switch S1 is open and the MCU control switches S2 and S3 are closed, the amplification factor of the amplifier circuit is N = R4 / (R5|R6), where R5|R6 represents the sum of the resistances of the inverting input resistor R5 and the parallel resistor R6.

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