SIC power semiconductor aging test device
By designing a SiC MOSFET aging test device with a substrate structure of parallel connections and multi-layer copper traces, high-frequency switching performance testing of SiC MOSFET devices is achieved, solving the problem of insufficient flexibility of existing test devices and providing a more stable and reliable test solution.
Patent Information
- Application Number
- CN202422413661.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-08
AI Technical Summary
Existing SiC MOSFET power device testing equipment cannot effectively test device performance under high-frequency switching, resulting in inflexible and impractical testing.
A SIC power semiconductor aging test device is designed. It uses SiC MOSFET devices connected in parallel and uses a substrate with copper traces on different layers to avoid electrical signal interference. It supports high-speed voltage and current changes. The device can be detachably plugged in and installed, and is suitable for the TO-247-4pin package.
It realizes the high-frequency switching performance test of SiC MOSFET devices, filling the testing gap in the market. It has the advantages of simple structure, stable operation, simple operation, safety and reliability.
Smart Images
Figure CN223413416U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power device testing, in particular to a SIC power semiconductor aging testing device. Background Art
[0002] SiC MOSFETs are currently widely used in everyday applications, including home appliances, industrial automation, new energy vehicles, photovoltaics, and wind power. Evaluating the suitability of SiC MOSFETs for these applications requires numerous tests, including static, dynamic, and reliability. However, existing SiC MOSFET evaluation equipment is not flexible or practical enough to test device performance under high-frequency switching conditions.
[0003] Therefore, a SIC power semiconductor aging test device is designed to overcome the above problems. Utility Model Content
[0004] The purpose of this utility model is to overcome the shortcomings of the existing technology and provide a SIC power semiconductor aging test device with a simple and reasonable structure, stable operation, simple operation, and safe and reliable performance. This utility model is mainly used for reliability testing of SiC MOSFETs. The platform is compatible with the TO-247-4 pin package and can be plugged in and installed. Compared with traditional SiC MOSFET reliability testing, which cannot test device performance under high-frequency switching, this solution fills this gap in the current market and achieves different reliability testing purposes.
[0005] The utility model is realized through the following technical solution: a SIC power semiconductor aging test device, comprising a test device body, wherein the test device body comprises a substrate and a plurality of groups of SiC mosfet devices arranged on the substrate, wherein the plurality of groups of SiC mosfet devices are connected in parallel with each other, and the G pole power pole, D pole power pole, S pole power pole, and S pole signal pole of each group of SiC mosfet devices are separately led out through a first lead, a second lead, a third lead, and a fourth lead, for subsequent access to a drive board drive signal and access to a power capacitor.
[0006] Preferably, the substrate uses copper routing on different layers to avoid the first lead, the second lead, the third lead and the fourth lead from crossing after being led out, causing electrical signal interference, and the D-pole power line and the S-pole power line in each group of SiCmosfet devices are set to be thickened to meet the GS pole aging high-speed voltage changes and the DS pole aging high-speed voltage and current changes.
[0007] Preferably, the D-pole power terminal and the S-pole power terminal of each group of SiC mosfet devices are directly connected to the power capacitor by screws, so as to provide the voltage of the DS pole and meet the requirements of high-speed voltage and current changes. The terminals of the G-pole power pole and the SX-pole signal pole receive the driving board signal to control the SIC mosfet device to perform high-speed switching.
[0008] Preferably, the pin size of each group of SiCmosfet devices satisfies direct plug-in installation on the substrate, so that each group of SiCmosfet devices is detachably installed, which is convenient for installation, fixation, and repeated disassembly and testing.
[0009] Preferably, the substrate is a PCB board.
[0010] The beneficial effects of the utility model are as follows:
[0011] The utility model designs a SIC power semiconductor aging test device, which is mainly used in reliability testing of SiC MOSFETs. The platform is adapted to the TO-247-4pin package and can be plugged in and installed. Compared with traditional SiC MOSFET reliability testing, which cannot test the device performance under high-frequency switching, the solution of the utility model fills the gap in this test item in the current market and achieves different reliability testing purposes. It has many advantages such as simple and reasonable structure, stable operation, simple operation, safety and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 This is the electrical connection principle diagram of the utility model.
[0013] Figure 2 This is a schematic diagram of the connection of different copper layers in the present invention.
[0014] Figure 3 It is a structural diagram of the device in this utility model. DETAILED DESCRIPTION
[0015] In order to enable those skilled in the art to more clearly understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below with reference to the accompanying drawings and embodiments.
[0016] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by terms such as "upper", "lower", "left", "right", "inside", "outside", "horizontal", and "vertical" are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or original referred to must have a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.
[0017] The present invention will be described in detail below with reference to the accompanying drawings: Figure 1 As shown, a SIC power semiconductor aging test device includes a test device body, which includes a substrate 1 and multiple groups of SiC mosfet devices 2 arranged on the substrate 1. The multiple groups of SiC mosfet devices are connected in parallel with each other. The G pole power pole, D pole power pole, S pole power pole, and SX pole signal pole of each group of SiC mosfet devices 2 are separately led out through the first lead 3, the second lead 4, the third lead 5, and the fourth lead 6 for the subsequent access of the drive board drive signal and the access of the power capacitor.
[0018] The substrate 1 uses different layers of copper wiring, such as Figure 2 As shown, a four-layer structure is adopted, which can effectively avoid the first lead 3, the second lead 4, the third lead 5 and the fourth lead 6 from crossing after being led out, causing electrical signal interference, and the D-pole power line and the S-pole power line in each group of SiCmosfet devices 2 are set to be thickened to meet the GS pole aging high-speed voltage change and the DS pole aging high-speed voltage and current change.
[0019] The D-pole power terminal and the S-pole power terminal of each group of SiC mosfet devices 2 are directly connected to the power capacitor by screws, which are used to provide the voltage of the DS pole and meet the requirements of high-speed voltage and current changes. The terminals of the G-pole power pole and the SX-pole signal pole connect the driving board signal to control the SIC mosfet device to perform high-speed switching.
[0020] like Figure 3 As shown, the size of the pins 7 of each group of SiC mosfet devices 2 meets the requirements for direct plug-in installation on the substrate 1, so that each group of SiC mosfet devices 2 is detachable, which is convenient for installation, fixation and repeated disassembly and testing. The substrate 1 is a PCB board.
[0021] The utility model designs a SIC power semiconductor aging test device, which is mainly used in reliability testing of SiC MOSFETs. The platform is adapted to the TO-247-4pin package and can be plugged in and installed. Compared with traditional SiC MOSFET reliability testing, which cannot test the device performance under high-frequency switching, the solution of the utility model fills the gap in this test item in the current market and achieves different reliability testing purposes. It has many advantages such as simple and reasonable structure, stable operation, simple operation, safety and reliability.
[0022] The specific embodiments described herein are merely illustrative of the principles and effects of this utility model and are not intended to limit this utility model. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this utility model shall be covered by the claims of this utility model.
Claims
1. A SIC power semiconductor aging test device, comprising a test device body, characterized in that: The test device body comprises a substrate (1) and a plurality of SiC mosfet devices (2) arranged on the substrate (1), wherein the plurality of SiC mosfet devices are connected in parallel with each other, and the G pole power pole, D pole power pole, S pole power pole, and SX pole signal pole of each SiC mosfet device (2) are led out separately through a first lead (3), a second lead (4), a third lead (5), and a fourth lead (6), for access to subsequent drive board drive signals and access to power capacitors; The size of the pins (7) of each group of SiCmosfet devices (2) satisfies direct plug-in installation on the substrate (1), so that each group of SiCmosfet devices (2) is detachably installed, facilitating installation, fixation, and repeated assembly and disassembly testing.
2. The SIC power semiconductor aging test device according to claim 1, characterized in that: The substrate (1) uses copper wiring in different layers to avoid the first lead (3), the second lead (4), the third lead (5) and the fourth lead (6) from crossing after being led out, thereby causing electrical signal interference. In addition, the D-pole power line and the S-pole power line in each group of SiC MOSFET devices (2) are thickened to meet the requirements of high-speed voltage change of GS pole aging and high-speed voltage and current change of DS pole aging.
3. The SIC power semiconductor aging test device according to claim 1 or 2, characterized in that: The D-pole power terminal and the S-pole power terminal of each group of SiC mosfet devices (2) are directly connected to the power capacitor by screw fixation, which is used to provide the voltage of the DS pole and meet the requirements of high-speed voltage and current changes. The terminals of the G-pole power pole and the SX-pole signal pole receive the driver board signal and are used to control the SIC mosfet device to perform high-speed switching.
4. The SIC power semiconductor aging test device according to claim 1, characterized in that: The substrate (1) is a PCB board.