Escalator state monitoring data collector

Abstract

The utility model discloses an escalator state monitoring data collector, which belongs to the technical field of data collection equipment and comprises an SOC (system on chip) processor, an FPGA (field programmable gate array) chip, an A / D (analog / digital) collection circuit, a signal conditioning circuit, a sensor interface circuit, an external communication module and a power supply module. According to the utility model, the SOC processor, the FPGA chip, the A / D acquisition circuit, the signal conditioning circuit, the switch chip and the PHY chip work cooperatively to form a high-performance data acquisition and calculation unit, so that the complexity of a diagnosis system using the acquisition device is reduced; the hardware cost is reduced, the maintenance is simplified, the reliability is improved, the production and installation processes are reduced, the debugging difficulty is reduced, more application scenes exist in narrow space occasions, and the market of original products is expanded to a certain extent.

Description

Technical Field

[0001] The utility model belongs to the technical field of data acquisition equipment, and in particular relates to an escalator state monitoring data collector. Background Art

[0002] The escalator condition monitoring system monitors the status of important transmission components in the escalator in real time to ensure the safety of escalator operation and provide predictive maintenance and repairs. The main transmission components in the escalator include: drive motor, reduction gearbox, main drive sprocket, step tensioner, handrail, etc. When these transmission components fail, it will directly affect the operation of the elevator and the safety of passengers. Based on the usage of the escalator, by establishing a condition monitoring system on the escalator equipment, the operating status information of the escalator is constantly collected, analyzed, and fault diagnosis is performed, so that a reasonable maintenance plan can be arranged to ensure that the escalator operates in a healthy state.

[0003] Existing monitoring systems usually set up multiple sensors for the main components of escalators, such as Figure 1 As shown in the figure, the analog sensor output signals are collected by acquisition devices and converted into digital signals for easy transmission and processing. This process includes filtering, gain adjustment, A / D acquisition, data preprocessing, and internal communication protocol transmission. Only then can the data be transmitted to the local computer for subsequent edge computing tasks. As the primary computing power of the entire system, the local computer is responsible for all computing tasks. It processes the collected device operating data using a predetermined algorithm to derive a diagnosis of the device's operating status and transmits this diagnosis via Ethernet. The computing network composed of switches and routers bridges the communication between the local computer and the network monitoring server. Applications on the network server access local computers at different sites to obtain diagnostic results for the equipment at that site and, based on the results, alert maintenance personnel whether maintenance is required.

[0004] The acquisition of escalator status and diagnosis of faults are the core functions of the entire system, requiring a significant amount of computing power. The current mainstream solutions require the additional configuration of industrial computers as computing units to provide sufficient computing power for fault diagnosis. This not only takes up a lot of space and requires additional power supply configuration, but also requires more design to ensure EMC compatibility with other equipment. As the number of points requiring collection and testing increases within a site, the amount of data increases. Therefore, the entire diagnostic system faces additional hardware costs and high maintenance costs due to issues such as large data processing equipment, high power consumption, complex network topology, and multiple cascades between devices. Utility Model Content

[0005] The technical problem solved by the utility model is to provide an escalator status monitoring data collector to solve the problem of excessively high additional hardware costs caused by factors such as large size, high power consumption, complex network topology, and multiple cascades between devices of data processing equipment.

[0006] Technical solution: In order to solve the above technical problems, the technical solution adopted by this utility model is as follows:

[0007] An escalator status monitoring data collector includes a SOC processor, an FPGA chip connected to the SOC processor, an A / D acquisition circuit connected to the FPGA chip, a signal conditioning circuit connected to the A / D acquisition circuit, a sensor interface circuit connected to the signal conditioning circuit, an external communication module connected to the SOC processor, and a power supply module connected to the SOC processor, the FPGA chip, the A / D acquisition circuit, the signal conditioning circuit, and the external communication module.

[0008] Furthermore, the external communication module includes a switch chip and a PHY chip.

[0009] Furthermore, the sensor interface circuit includes a sensor interface and a sensor power supply circuit connected to the sensor interface, and the sensor power supply circuit is connected to the FPGA chip.

[0010] Furthermore, the power supply module includes a first power supply circuit, a second power supply circuit, a third power supply circuit, a fourth power supply circuit, a fifth power supply circuit, a sixth power supply circuit, a seventh power supply circuit, an eighth power supply circuit, a ninth power supply circuit, a tenth power supply circuit and an eleventh power supply circuit.

[0011] Furthermore, the first power supply circuit is connected to the signal conditioning circuit, and the second power supply circuit and the third power supply circuit are connected to the A / D acquisition circuit.

[0012] Furthermore, the fourth power supply circuit, the fifth power supply circuit and the sixth power supply circuit are all connected to the SOC processor.

[0013] Furthermore, the seventh power supply circuit is connected to the external communication module.

[0014] Furthermore, the eighth power supply circuit, the ninth power supply circuit, the tenth power supply circuit and the eleventh power supply circuit are all connected to the FPGA chip.

[0015] Furthermore, the SOC processor adopts RK3568J processor, and the FPGA chip adopts XC7A35T-2FGG484I chip.

[0016] Beneficial effects: Compared with the prior art, the utility model has the following advantages:

[0017] 1. The SOC processor, FPGA chip, A / D acquisition circuit, signal conditioning circuit, switch chip and PHY chip work together to form a high-performance data acquisition and calculation unit, reducing the complexity of the diagnostic system using the collector;

[0018] 2. Reduce hardware costs: This utility model integrates multiple independent functional modules into a single device, effectively reducing the number and variety of required parts, thereby significantly reducing material procurement costs. In addition, the integrated multi-functional design allows for standardized production and assembly processes, further reducing manufacturing costs;

[0019] 3. Simplified maintenance: The integrated design makes the overall structure of the equipment more compact, reduces failure points, and improves system reliability. When maintenance is required, users only need to focus on a single device rather than multiple scattered components, which simplifies the maintenance process, shortens maintenance time, and reduces maintenance costs.

[0020] 4. Improved reliability: By optimizing the connection between internal components, the utility model enhances the collaborative working ability between functional modules, reduces problems caused by interface connection failure or signal interference, and significantly improves the stability and reliability of the system;

[0021] 5. Reduce production and installation processes: The integrated design of this utility model greatly simplifies the assembly steps, reducing the need for station settings and operator training on the production assembly line;

[0022] 6. Reduced debugging difficulty: The integrated device interface and diagnostic process are more simplified, which not only makes the initial installation and configuration more intuitive and simple, but also allows for quick location and resolution of problems encountered during subsequent use, improving system availability and user experience.

[0023] 7. As the size of the equipment is reduced, it has more usage scenarios in places with limited space, which has expanded the market of the original product to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the hardware topology diagram of the existing diagnostic system;

[0025] Figure 2 FIG. 4 is a hardware topology diagram of a diagnostic system using the collector of this embodiment.

[0026] Figure 3 This is a functional block diagram of a collector according to an embodiment of the present utility model;

[0027] Figure 4 It is a structural block diagram of the power supply module of the embodiment. DETAILED DESCRIPTION

[0028] The present invention will be further illustrated below with reference to specific embodiments. The embodiments are implemented based on the technical solutions of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0029] like Figure 3 As shown, an escalator condition monitoring data collector includes a SOC processor 1, an FPGA chip 2, an A / D acquisition circuit 3, a signal conditioning circuit 4, a sensor interface circuit 5, an external communication module 6, and a power supply module 7. SOC (Sys-On-Chip) is an embedded operating system on a chip (SOC), characterized by high integration, high performance, low power consumption, small size, low cost, and high reliability. The SOC processor 1 can replace the existing external computer. In this embodiment, the SOC processor 1 uses an RK3568J processor and runs the Linux operating system. Existing software is ported and developed within the Linux operating system environment. It calculates the pre-processed data from the FPGA chip 2 according to a diagnostic algorithm to obtain diagnostic results. It also handles external communication protocol integration and communication. While providing greater computing power than the original diagnostic system, it can significantly reduce the size of the diagnostic system. Its low power consumption also reduces reliance on power supply power, thereby reducing the size of the power supply and further reducing the overall system size. Furthermore, the high integration of the SOC processor allows it to be easily integrated with other devices. FPGA chip 2 is connected to SOC processor 1. In this embodiment, FPGA chip 2 uses the XC7A35T-2FGG484I chip, which aggregates and preprocesses collected multi-channel data. The FPGA's I / O interface flexibility and high concurrency offer unmatched advantages over other controllers in multi-channel acquisition and complex communication environments. A / D acquisition circuit 3 is connected to FPGA chip 2, performing A / D sampling, converting analog signals into digital signals that are easy to process and calculate, and controlling sampling noise. Signal conditioning circuit 4 is connected to A / D acquisition circuit 3 to control signal noise and impedance matching. Sensor interface circuit 5 is connected to signal conditioning circuit 4 to provide power and signal access for sensors, complying with EMC interface design requirements. External communication module 6 is connected to SOC processor 1 and is responsible for external network communication. Power supply module 7 is connected to SOC processor 1, FPGA chip 2, A / D acquisition circuit 3, signal conditioning circuit 4, and external communication module 6 to provide power.

[0030] like Figure 3As shown, the external communication module 6 includes a switch chip 61 and a PHY chip 62. The external communication module 6 is a peripheral of the SOC processor 1 and is responsible for communication with the external network. The switch chip 61 adopts an onboard Gigabit Ethernet communication dual-port switch chip, and the PHY chip 62 adopts an onboard Gigabit Ethernet communication PHY chip.

[0031] like Figure 3 As shown, the sensor interface circuit 5 includes a sensor interface 51 and a sensor power supply circuit 52. The sensor interface 51 is connected to the sensor power supply circuit 52. The sensor interface 51 is used to connect multiple external sensors in a plug-in manner. The sensor power supply circuit 52 is connected to the FPGA chip 2. The sensor power supply circuit 52 is used to provide power to the sensor.

[0032] like Figure 3 and Figure 4 As shown, the power supply module 7 includes a first power supply circuit 71, a second power supply circuit 72, a third power supply circuit 73, a fourth power supply circuit 74, a fifth power supply circuit 75, a sixth power supply circuit 76, a seventh power supply circuit 77, an eighth power supply circuit 78, a ninth power supply circuit 79, a tenth power supply circuit 710 and an eleventh power supply circuit 711.

[0033] The first power supply circuit 71 is connected to the signal conditioning circuit 4 . The first power supply circuit 71 uses an onsemi MC79M12CDTRKG model LDO to step down a 15V DC voltage into a 12V DC voltage for use by the signal conditioning circuit 4 .

[0034] The second power supply circuit 72 and the third power supply circuit 73 are connected to the A / D acquisition circuit 3. The second power supply circuit 72 uses Onsemi MC79M08CDTRKG model LDO to step down the 12V DC voltage into 8V DC voltage for powering the A / D acquisition circuit 3. The third power supply circuit 73 uses Onsemi MC79M05BDTRKG model LDO to step down the 8V DC voltage into 5V DC voltage for powering the A / D sampling circuit.

[0035] The fourth power supply circuit 74, the fifth power supply circuit 75 and the sixth power supply circuit 76 are all connected to the SOC processor 1. The fourth power supply circuit 74 uses the MPS MP2143DJ model DC-DC to step down the 5V DC voltage to 3.3V for use by the RK3568J model SOC processor 1. The fifth power supply circuit 75 uses the MPS MP2143DJ model DC-DC to step down the 15V DC voltage to 5.0V for use by the RK3568J model SOC processor 1, and uses the MPS MP2143DJ model DC-DC to step down the 5V DC voltage to 3.3V for use by the RK3568J model SOC processor 1.

[0036] The seventh power supply circuit 77 is connected to the external communication module 6 and uses HGSEMI MIC29302S / TR model LDO to step down the 5V DC voltage to 3.7V for use by the switch chip 61 and the PHY chip 62.

[0037] The eighth power supply circuit 78, the ninth power supply circuit 79, the tenth power supply circuit 710 and the eleventh power supply circuit 711 are all connected to the FPGA chip 2. The eighth power supply circuit 78 uses the MPS MP2143DJ model DC-DC to step down the 15V DC voltage to 5V for use as the power supply for the XC7020CLG400 model FPGA chip 2. The ninth power supply circuit 79 uses the MPS MP2143DJ model DC-DC to step down the 5V DC voltage to 3.3V for use by the XC7020CLG400 model FPGA chip 2. The tenth power supply circuit 710 uses the MPS MP2143DJ model DC-DC to step down the 5V DC voltage to 1.8V for use by the XC7020CLG400 model FPGA chip 2. The eleventh power supply circuit 711 uses the MPS MP2143DJ model DC-DC to step down the 5V DC voltage to 1.0V for use by the XC7020CLG400 model FPGA chip 2.

[0038] When the collector in this embodiment is operating, the XC7A35T-2FGG484I FPGA chip 2 receives control signals from the RK3568J SOC processor 1, completes the configuration of the subsequent circuitry, and operates the A / D acquisition circuit 3 and signal conditioning circuit 4 to collect signals from the sensors (the sensors are located in the main components of the escalator). The XC7A35T-2FGG484I FPGA chip 2 then receives and caches the data collected by the A / D acquisition circuit 3. They communicate using a proprietary protocol over a three-way high-speed SPI bus. The XC7A35T-2FGG484I FPGA chip 2 notifies the RK3568J SOC processor 1 via an interrupt signal that data is ready for transmission and awaits the read bus from the RK3568J SOC processor 1. When data transmission begins, the data signal is 32 bits wide, and data transmission is time-sharing by channel. When the SOC processor 1 receives the data, it performs DMA and stores the data in the memory space. When the memory caches 1S data, it performs a predetermined algorithm calculation on the 1S data and sends the calculation result to the network server (such as Figure 2 On the other hand, it continues to receive and DMA buffer the next second's data from FPGA chip 2 (model XC7A35T-2FGG484I).

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. An escalator status monitoring data collector, characterized in that: The invention comprises a SOC processor (1), an FPGA chip (2) connected to the SOC processor (1), an A / D acquisition circuit (3) connected to the FPGA chip (2), a signal conditioning circuit (4) connected to the A / D acquisition circuit (3), a sensor interface circuit (5) connected to the signal conditioning circuit (4), an external communication module (6) connected to the SOC processor (1), and a power supply module (7) connected to the SOC processor (1), the FPGA chip (2), the A / D acquisition circuit (3), the signal conditioning circuit (4), and the external communication module (6).

2. The escalator status monitoring data collector according to claim 1, characterized in that: The external communication module (6) includes a switch chip (61) and a PHY chip (62).

3. The escalator status monitoring data collector according to claim 2, characterized in that: The sensor interface circuit (5) comprises a sensor interface (51) and a sensor power supply circuit (52) connected to the sensor interface (51), and the sensor power supply circuit (52) is connected to the FPGA chip (2).

4. The escalator status monitoring data collector according to claim 2, characterized in that: The power supply module (7) comprises a first power supply circuit (71), a second power supply circuit (72), a third power supply circuit (73), a fourth power supply circuit (74), a fifth power supply circuit (75), a sixth power supply circuit (76), a seventh power supply circuit (77), an eighth power supply circuit (78), a ninth power supply circuit (79), a tenth power supply circuit (710), and an eleventh power supply circuit (711).

5. The escalator status monitoring data collector according to claim 4, characterized in that: The first power supply circuit (71) is connected to the signal conditioning circuit (4), and the second power supply circuit (72) and the third power supply circuit (73) are connected to the A / D acquisition circuit (3).

6. The escalator status monitoring data collector according to claim 4, characterized in that: The fourth power supply circuit (74), the fifth power supply circuit (75) and the sixth power supply circuit (76) are all connected to the SOC processor (1).

7. The escalator status monitoring data collector according to claim 4, characterized in that: The seventh power supply circuit (77) is connected to the external communication module (6).

8. The escalator status monitoring data collector according to claim 4, characterized in that: The eighth power supply circuit (78), the ninth power supply circuit (79), the tenth power supply circuit (710) and the eleventh power supply circuit (711) are all connected to the FPGA chip (2).

9. The escalator status monitoring data collector according to claim 1, characterized in that: The SOC processor (1) adopts an RK3568J processor, and the FPGA chip (2) adopts an XC7A35T-2FGG484I chip.

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