DDR5 test module
By integrating the FPGA acquisition component and the DDR5 test module of the power supply unit on the server motherboard, the problem of the inability to locate memory connection faults in the existing technology is solved, and rapid fault location and efficient repair are achieved.
Patent Information
- Application Number
- CN202422837077.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-11-21
AI Technical Summary
Existing technologies cannot effectively locate the location of memory connection faults on server motherboards, making maintenance and adjustments after motherboard function testing difficult.
A DDR5 test module is designed, which integrates FPGA acquisition components, power supply units and connection units on a circuit board. The conductive contact components cooperate with the connector of the motherboard to be tested to simulate the memory card connection, perform data acquisition and power supply, and use the FPGA acquisition components to perform step-by-step conduction control to quickly locate the fault location.
It improves the efficiency and reliability of motherboard testing, can quickly locate faulty connections, and facilitates maintenance.
Smart Images
Figure CN223413699U_ABST
Abstract
Description
Technical Field
[0001] The utility model is applied to the technical field of motherboard testing, and particularly relates to a DDR5 test module. Background Art
[0002] A server is a device used to provide computing or application services in a network environment. It works by installing various modules on the motherboard, including processors, RAM, and other modules. As the functions of server motherboards in the manufacturing industry continue to increase, the performance requirements for testing memory modules are also gradually increasing. The CPU architecture is constantly updated and the server motherboards under test are constantly upgraded. The new technology field of DDR5 has higher performance, larger DIMM capacity, stronger data integrity, and is easier to maintain. In order to ensure the normal operation of the server, the connectors connecting the processor and RAM on the motherboard and the corresponding module functions need to be tested to check the reliability of the corresponding functions. Directly connecting the memory card for testing does not allow the specific location of the fault to be obtained, which is not conducive to maintenance and adjustment after the motherboard function test.
[0003] If a test module for performing a mainboard memory function test can be provided, the test efficiency and reliability of the mainboard can be improved. Utility Model Content
[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a server mainboard DDR5 test module that is convenient for locating the fault position.
[0005] The technical solution adopted by the present utility model is as follows: the present utility model includes a processing unit, a connection unit and a power supply unit arranged on a circuit board, the circuit board is provided with a conductive contact assembly that cooperates with the connector of the motherboard to be tested, the processing unit, the connection unit and the power supply unit are all conductively connected to corresponding contacts of the conductive contact assembly, the processing unit includes an FPGA acquisition assembly that performs data acquisition through the conductive contact assembly, the connection unit includes a JATG interface and a JATG control assembly that cooperate with the FPGA acquisition assembly, and the power supply unit collects power from the connector of the motherboard to be tested and converts the power supply.
[0006] As can be seen from the above scheme, the FPGA acquisition component, power supply unit, and connection unit are integrated on the circuit board, and a conductive contact component capable of cooperating with the connector of the motherboard under test is provided, thereby realizing the simulated memory card connection and connecting the power to the connector through the power supply unit. The FPGA acquisition component is then used to collect data to obtain the operating information of the motherboard connector under test and perform functional testing. The conduction control is carried out by several conduction units of the FPGA acquisition component, thereby achieving step-by-step conduction, thereby realizing the rapid location of the faulty connection and facilitating maintenance. The connection unit is used for cascade conduction of multiple test modules.
[0007] A preferred solution is that the connection unit further includes several groups of general logic circuits and multiplexers, the input terminals of the JATG interface are correspondingly connected to the FPGA acquisition component through several groups of the general logic circuits, and the JATG control component switches the paths of the several groups of the general logic circuits through the multiplexer.
[0008] A preferred solution is that the present invention further includes a memory connected to the FPGA acquisition component.
[0009] A preferred solution is that the FPGA acquisition component includes a plurality of conduction units, and the FPGA acquisition component is connected to corresponding contacts of the conductive contact assembly through the plurality of conduction units. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 It is a system block diagram of the utility model;
[0011] Figure 2 is a circuit schematic diagram of the conductive contact assembly;
[0012] Figure 3 It is the circuit schematic diagram of the first part of the FPGA acquisition component;
[0013] Figure 4 It is the circuit schematic diagram of the second part of the FPGA acquisition component;
[0014] Figure 5 It is the circuit schematic diagram of the third part of the FPGA acquisition component;
[0015] Figure 6 is a circuit schematic diagram of the power supply unit;
[0016] Figure 7 is a circuit schematic diagram of the memory;
[0017] Figure 8 is a circuit schematic diagram of the JATG control component;
[0018] Figure 9This is the first part of the circuit schematic diagram of the JATG interface;
[0019] Figure 10 This is the second part of the circuit schematic diagram of the JATG interface. DETAILED DESCRIPTION
[0020] like Figures 1 to 10 As shown, in this embodiment, the utility model includes a processing unit 2, a connection unit 3, and a power supply unit 4 provided on a circuit board 1. The circuit board 1 is provided with a conductive contact assembly 11 that cooperates with the connector of the motherboard to be tested. The processing unit 2, the connection unit 3, and the power supply unit 4 are all conductively connected to corresponding contacts of the conductive contact assembly 11. The processing unit 2 includes an FPGA acquisition component U3A\U3B\U3C\U3D\U3E for data acquisition through the conductive contact assembly 11. The connection unit 3 includes a JATG interface 31 and a JATG control component 32 that cooperate with the FPGA acquisition component U3A\U3B\U3C\U3D\U3E. The power supply unit 4 collects power from the connector of the motherboard to be tested and converts the power supply. The FPGA acquisition component U3A\U3B\U3C\U3D\U3E is an FPGA chip with model number EP4CE15F23C8N.
[0021] In this embodiment, the connection unit 3 also includes several groups of general logic circuits and a multiplexer U11. The input terminals of the JATG interface 31 are connected to the FPGA acquisition components U3A\U3B\U3C\U3D\U3E through several groups of the general logic circuits. The JATG control component 32 switches the path switching of several groups of the general logic circuits through the multiplexer U11. The JATG control component 32 is a processor chip U12 with the model of STM8L152K6U6TR. The processor chip U12 is used to control the cascade signal, and the multiplexer U11 is used to control the conduction of the cascade signal.
[0022] In this embodiment, the utility model also includes a memory U9 connected to the FPGA acquisition component U3A\U3B\U3C\U3D\U3E, and the memory U9 is a memory chip with model M25P80-VMW6TP. The memory U9 is used for firmware burning.
[0023] The FPGA acquisition component U3A\U3B\U3C\U3D\U3E includes several conduction units, and the FPGA acquisition component U3A\U3B\U3C\U3D\U3E is connected to the corresponding contacts of the conductive contact component 11 through the several conduction units.
[0024] In this embodiment, the power supply unit 4 includes power management chips of model MP1482DS-LF-Z and SC1565IS-2.5TRT. The power supply unit 4 receives the 12V and 3.3V power supplies provided by the connector of the motherboard to be tested and provides them to each unit after conversion.
[0025] Although the embodiments of the present invention are described with practical solutions, they do not limit the meaning of the present invention. For those skilled in the art, it is obvious to modify the implementation scheme and combine it with other solutions based on this description.
Claims
1. DDR5 test module, characterized by: It comprises a processing unit (2), a connection unit (3) and a power supply unit (4) arranged on a circuit board (1); a conductive contact assembly (11) cooperating with a connector of a motherboard to be tested is arranged on the circuit board (1); the processing unit (2), the connection unit (3) and the power supply unit (4) are all conductively connected to corresponding contacts of the conductive contact assembly (11); the processing unit (2) comprises an FPGA acquisition assembly for performing data acquisition through the conductive contact assembly (11); the connection unit (3) comprises a JATG interface (31) and a JATG control assembly (32) cooperating with the FPGA acquisition assembly; and the power supply unit (4) acquires power from the connector of the motherboard to be tested and converts the power.
2. The DDR5 test module according to claim 1, wherein: The connection unit (3) further includes a plurality of groups of general logic circuits and a multiplexer (U11), the input terminals of the JATG interface (31) are connected to the FPGA acquisition component via the plurality of groups of general logic circuits, and the JATG control component (32) switches the paths of the plurality of groups of general logic circuits via the multiplexer (U11).
3. The DDR5 test module according to claim 1, wherein: It also includes a memory (U9) connected to the FPGA acquisition component.
4. The DDR5 test module according to claim 1, wherein: The FPGA acquisition component comprises a plurality of conduction units, and the FPGA acquisition component is connected to corresponding contacts of the conductive contact component (11) via the plurality of conduction units.