Package structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises a substrate; a photonic integrated circuit on the substrate; an electronic integrated circuit on the photonic integrated circuit; the first connecting piece is positioned between the electronic integrated circuit and the photon integrated circuit and is used for electrically connecting the electronic integrated circuit and the photon integrated circuit; the second connecting pieces are located between the electronic integrated circuit and the photon integrated circuit, the second connecting pieces are not electrically connected with the electronic integrated circuit and the photon integrated circuit, the second connecting pieces are continuously distributed on the first side edge and the second side edge of the bottom face of the electronic integrated circuit, and the distribution density of the second connecting pieces is higher than that of the first connecting pieces. The utility model aims to provide a packaging structure so as to at least improve the yield of the packaging structure.

Description

Technical Field

[0001] The utility model relates to a packaging structure. Background Art

[0002] Figures 1 to 2 The formation process of a 2.5-dimensional (D) silicon photonic (Si-Ph) package (PKG) in the prior art is shown, wherein Figure 1 The figure shows a CoS (Chip on Substrate) process, where a photonic integrated circuit (PIC) 1 is bonded to a substrate 2, and an underfill layer 3 is placed between the PIC 1 and the substrate 2. Figure 2 The figure shows a CoC (Chip on Chip) process for bonding an electronic integrated circuit (EIC) 4 to the PIC 1 .

[0003] Because the prior art applies an underfill layer 3 between the PIC 1 and substrate 2 before bonding the EIC 4, the EIC 4 is subject to the warpage of both the PIC 1 and substrate 2 during bonding. The warpage of the substrate 2 is greater, and the density of bumps 5 in the peripheral area of ​​the EIC 4 is lower. This can lead to cracking of the solder balls 5 in the peripheral area of ​​the EIC 4. Stress analysis of the prior art package revealed that the highest stress region occurs in the overlap area between the EIC 4 and the PIC 1. Utility Model Content

[0004] In view of the problems existing in the related art, the purpose of the present invention is to provide a packaging structure to at least improve the yield of the packaging structure.

[0005] To achieve the above-mentioned objectives, the present invention provides a packaging structure, comprising: a substrate; a photonic integrated circuit, located on the substrate; an electronic integrated circuit, located on the photonic integrated circuit; a first connector, located between the electronic integrated circuit and the photonic integrated circuit, for electrically connecting the electronic integrated circuit and the photonic integrated circuit; a second connector, located between the electronic integrated circuit and the photonic integrated circuit, the second connector not electrically connecting the electronic integrated circuit and the photonic integrated circuit, the second connector being continuously distributed at a first side edge and a second side edge of a bottom surface of the electronic integrated circuit, the distribution density of the second connector being higher than the distribution density of the first connector.

[0006] In some embodiments, the packaging structure further includes: an underfill layer located between the photonic integrated circuit and the electronic integrated circuit.

[0007] In some embodiments, the second connectors are further continuously distributed on a third side of the bottom surface of the electronic integrated circuit opposite to the first side, and the distribution density of the second connectors on the third side is greater than the distribution density of the first connectors.

[0008] In some embodiments, the second connector has a size larger than the first connector.

[0009] In some embodiments, the diameter of the second connector is 10 μm to 45 μm.

[0010] In some embodiments, the diameter of the second connector is 30 μm to 40 μm.

[0011] In some embodiments, the pitch of the second connectors is smaller than the pitch of the first connectors.

[0012] In some embodiments, the pitch of the second connectors is 40 μm to 80 μm.

[0013] In some embodiments, the second connector is further located between the first connectors.

[0014] In some embodiments, the second connecting member is located outside the first connecting member.

[0015] In some embodiments, the first connecting member and the second connecting member include bumps.

[0016] In some embodiments, the first connector and the second connector include solder balls.

[0017] In some embodiments, the substrate has lateral dimensions that are larger than lateral dimensions of the photonic integrated circuit.

[0018] In some embodiments, the electronic integrated circuit has lateral dimensions that are greater than lateral dimensions of the photonic integrated circuit.

[0019] An embodiment of the present application also provides a packaging structure, including: a substrate; a photonic integrated circuit located on the substrate; an electronic integrated circuit located on the photonic integrated circuit; a first connector and a second connector located between the electronic integrated circuit and the photonic integrated circuit, the first connector being used to electrically connect the electronic integrated circuit and the photonic integrated circuit, the second connector not electrically connecting the electronic integrated circuit and the photonic integrated circuit, the bottom surface of the electronic integrated circuit including a middle area, a first area located between the middle area and a first side edge of the bottom surface, and a second area located between the middle area and a second side edge of the bottom surface connected to the first side edge, the distribution density of the first connector and the second connector in the first area and the second area being greater than the distribution density in the middle area.

[0020] In some embodiments, the bottom surface of the electronic integrated circuit includes a third area between the middle area and a third side of the bottom surface opposite to the first side, and the first and second connectors are distributed more densely in the third area than in the middle area.

[0021] In some embodiments, in the first region, a distribution density of the first connectors is less than a distribution density of the second connectors.

[0022] In some embodiments, the distribution density of the second connecting members in the first region is greater than that in the middle region.

[0023] In some embodiments, in the second region, a distribution density of the first connectors is less than a distribution density of the second connectors.

[0024] In some embodiments, the distribution density of the second connecting members in the second region is greater than that in the middle region.

[0025] The beneficial technical effects of the present utility model are:

[0026] In the embodiment of the present application, second connectors are continuously distributed at the first side and the second side of the bottom surface of the electronic integrated circuit to strengthen the connection between the electronic integrated circuit and the photonic integrated circuit in an area where the warping of the electronic integrated circuit is large (and therefore the stress is also large), and the distribution density of the second connectors is increased in this area. The distribution density of the second connectors is higher than the distribution density of the first connectors to reduce the possibility of breakage of the first connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without inventive work. It is worth noting that, according to standard industry practices, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the clarity of discussion, the sizes of the various components can be arbitrarily increased or decreased.

[0028] Figures 1 to 2 The formation process of the 2.5D silicon photonic package of the prior art is shown, wherein Figure 1 shows the CoS process, Figure 2 A CoC process is shown.

[0029] Figures 3 to 20 The diagram shows a process for forming a packaging structure according to an embodiment of the present application.

[0030] Figure 3 Providing a substrate is shown.

[0031] Figure 4 Bump bonding of a photonic integrated circuit to a substrate is shown.

[0032] Figure 5 The electronic integrated circuit is shown joined to the photonic integrated circuit via a first connection.

[0033] Figure 6 Shown is the corresponding Figure 5 A more detailed diagram of .

[0034] Figure 7 A first connector and an under bump metallurgy disposed on a photonic integrated circuit are shown.

[0035] Figure 8 Shows some embodiments of the present application corresponding to Figure 5 and Figure 6 Top view of the steps shown.

[0036] Figure 9 The layout of the solder balls on the bottom surface of the EIC in the control group and the layout of the first connectors on the bottom surface of the electronic integrated circuit in the experimental group 1 are shown.

[0037] Figure 10 The layout of the first connectors on the bottom surface of the electronic integrated circuit in Experimental Group 2 is shown.

[0038] Figure 11 The layout of the first connecting elements on the bottom surface of the electronic integrated circuit in experimental groups 3-4 is shown.

[0039] Figure 12 The layout of the first connectors on the bottom surface of the electronic integrated circuit in Experimental Group 5 is shown.

[0040] Figure 13 The strain simulation diagram of the solder ball of the control group is shown.

[0041] Figure 14 The strain simulation diagram of the solder balls of experimental group 1 is shown.

[0042] Figure 15 The strain simulation diagram of the solder balls of experimental group 2 is shown.

[0043] Figure 16 The strain simulation diagram of the solder balls of Experimental Group 3 is shown.

[0044] Figure 17 The strain simulation diagram of the solder balls of experimental group 4 is shown.

[0045] Figure 18 The strain simulation diagram of the solder balls of experimental group 5 is shown.

[0046] Figure 19The formation of a second underfill layer between the photonic integrated circuit and the substrate is shown.

[0047] Figure 20 The formation of an underfill layer between a photonic integrated circuit and an electronic integrated circuit is shown.

[0048] Figure 21 Shown with Figure 8 Different embodiments. DETAILED DESCRIPTION

[0049] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.

[0050] The embodiments of the present application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative and diagrammatic and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

[0051] As used herein, the terms "substantially," "substantially," and "approximately" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.

[0052] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivatives (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific orientation.

[0053] For ease of description, “first,” “second,” “third,” etc. may be used herein to distinguish different components in a figure or a series of figures. “First,” “second,” “third,” etc. are not intended to describe the corresponding components.

[0054] Figures 3 to 20 The diagram shows a process of forming the package structure 100 according to an embodiment of the present application.

[0055] Figure 3 It is shown that a substrate 10 is provided.

[0056] Figure 4 The photonic integrated circuit 20 is shown bonded to the substrate 10 via bumps 70 , which in some embodiments are controlled collapse chip connection (C4) bumps. In some embodiments, the lateral dimensions of the substrate 10 are larger than the lateral dimensions of the photonic integrated circuit 20 .

[0057] Figure 5 The electronic integrated circuit 30 is shown bonded to the photonic integrated circuit 20 via a first connector 40. The first connector 40 is located between the electronic integrated circuit 30 and the photonic integrated circuit 20 to electrically connect the electronic integrated circuit 30 and the photonic integrated circuit 20. In some embodiments, the lateral dimensions of the electronic integrated circuit 30 are larger than the lateral dimensions of the photonic integrated circuit 20.

[0058] Figure 6 Shown is the corresponding Figure 5 , in which the first connecting member 40 includes a bump 42 disposed on the bottom surface of the electronic integrated circuit 30 and a solder ball 44 connecting the bump 42 and the photonic integrated circuit 20.

[0059] Figure 7 The diagram shows a first connector 40 and an underbump metallurgy 22 disposed on the photonic integrated circuit 20. The first connector 40 engages the underbump metallurgy 22 to electrically connect the photonic integrated circuit 20. The bump 42 includes a copper layer 420 and a nickel layer 422. The material of the solder ball 44 is, for example, SnAg. The underbump metallurgy 22 includes a copper layer 220 with a thickness of, for example, 5 μm, a nickel layer 222 with a thickness of, for example, 3 μm, and a gold layer 224 with a thickness of, for example, 0.2 to 0.5 μm. After the solder ball 44 contacts the gold layer 224, a reaction will occur to form an intermetallic compound (IMC) AuSn4 between the two. The IMC is brittle and can withstand less stress. The location of the crack is analyzed using EDS (Energy Dispersive Spectrometer, X-ray energy spectrometer). It can be found that the location of the crack is usually located at the part where the IMC is generated. In the embodiment of the present application, when the electronic integrated circuit 30 is bonded to the photonic integrated circuit 20, a bottom filling layer is not formed between the photonic integrated circuit 20 and the substrate 10. Therefore, only the warping of the photonic integrated circuit 20 directly bonded to the electronic integrated circuit 30 (the warping amount is small) is transferred to the electronic integrated circuit 30, and the warping of the substrate 10 (the warping amount is large) is not transferred to the electronic integrated circuit 30. The embodiment of the present application reduces the occurrence of cracks in the first connector 40 in the edge area.

[0060] Figure 8 Shows some embodiments of the present application corresponding to Figure 5 and Figure 6 The top view of the step shown in FIG. 4 shows a first connector 40 and a second connector 50 obscured by the electronic integrated circuit 30 using dashed lines. In some embodiments of the present application, a second connector 50 is further provided between the electronic integrated circuit 30 and the photonic integrated circuit 20. The second connector 50 has the same structure as the first connector 40, but differs from the first connector 40 in that the second connector 50 is a dummy connector electrically isolated from the electronic integrated circuit 30 and the photonic integrated circuit 20. That is, the second connector 50 does not electrically connect the electronic integrated circuit 30 and the photonic integrated circuit 20. The second connector 50 is used to physically connect the electronic integrated circuit 30 and the photonic integrated circuit 20, thereby securing the electronic integrated circuit 30 and the photonic integrated circuit 20 together with the first connector 40, further reducing the risk of cracking of the first connector 40.

[0061] Table 1 shows a comparison between the experimental group of the present application and the control group of the prior art, wherein the experimental group and the control group are compared at room temperature (25° C.).

[0062] The control group is an embodiment of the prior art, in which before bonding the EIC 4, an underfill layer 3 is placed between the PIC 1 and the substrate 2, and the layout of the solder balls 5 on the bottom surface of the EIC 4 is as follows: Figure 9 As shown, the diameter of the solder balls 5 is 30 μm, the pitch is 80 μm, and the area covered by the solder balls 5 on the bottom surface of the EIC 4 is 4.6%. Figure 13 The strain simulation diagram of the solder ball 5 of the control group is shown, wherein the plastic strain of the solder ball 5 reaches the maximum plastic strain ratio of 7.25%, and the solder ball 5 with the largest strain is located at Figure 13 In the corner area a.

[0063] Experimental group 1 is an embodiment of the present application, wherein before bonding the electronic integrated circuit 30, no underfill layer 62 is formed between the photonic integrated circuit 20 and the substrate 10, and the layout of the first connector 40 on the bottom surface of the electronic integrated circuit 30 is as follows: Figure 9 As shown, the diameter of the first connecting member 40 is 30 μm, the pitch is 80 μm, and the ratio of the area covered by the first connecting member 40 on the bottom surface of the electronic integrated circuit 30 is 4.6%. Figure 14 The strain simulation diagram of the solder ball 44 of the first connector 40 of the experimental group 1 is shown, wherein the plastic strain of the solder ball 44 reaches the maximum plastic strain at a ratio of 6.25%, which is improved by 13.7% compared with the prior art (the plastic strain of the solder ball 44 is reduced). The solder ball 44 with the largest strain is located at Figure 14 The embodiment of the present application changes the order of applying the bottom filling layer 62, which significantly improves the problem of cracking of the solder balls 44 of the first connector 40. Only the solder balls 44 located at the corners of the electronic integrated circuit 30 may have the problem of cracking.

[0064] Experimental group 2 is an embodiment of the present application, wherein before bonding the electronic integrated circuit 30, no bottom filling layer 62 is formed between the photonic integrated circuit 20 and the substrate 10, and the layout of the first connector 40 on the bottom surface of the electronic integrated circuit 30 is as follows: Figure 10 As shown, the diameter of the first connecting member 40 is 30 μm, the pitch is 80 μm, and the ratio of the area covered by the first connecting member 40 and the second connecting member 50 on the bottom surface of the electronic integrated circuit 30 is 6.4%. Figure 15 The strain simulation diagram of the solder ball 44 of the first connector 40 of the experimental group 2 is shown, wherein the plastic strain of the solder ball 44 reaches the maximum plastic strain at a ratio of 6.24%, which is improved by 13.9% compared with the prior art (the plastic strain of the solder ball 44 is reduced). The solder ball 44 with the largest strain is located at Figure 15 In the corner area c.

[0065] Experimental group 3 is an embodiment of the present application, wherein before bonding the electronic integrated circuit 30, no underfill layer 62 is formed between the photonic integrated circuit 20 and the substrate 10, and the layout of the first connector 40 on the bottom surface of the electronic integrated circuit 30 is as follows: Figure 11 As shown, the diameter of the first connecting member 40 and the second connecting member 50 is 35 μm, the pitch is 80 μm, and the ratio of the area covered by the first connecting member 40 and the second connecting member 50 on the bottom surface of the electronic integrated circuit 30 is 8.5%. Figure 16 The strain simulation diagram of the solder ball 44 of the first connector 40 of the experimental group 3 is shown, wherein the plastic strain of the solder ball 44 reaches the maximum plastic strain at a ratio of 6.01%, which is improved by 17% compared with the prior art (the plastic strain of the solder ball 44 is reduced). The solder ball 44 with the largest strain is located at Figure 16 In the corner area d.

[0066] Experimental group 4 is an embodiment of the present application, wherein before bonding the electronic integrated circuit 30, no underfill layer 62 is formed between the photonic integrated circuit 20 and the substrate 10, and the layout of the first connector 40 on the bottom surface of the electronic integrated circuit 30 is as follows: Figure 11 As shown, the diameter of the first connector 40 and the second connector 50 is 35 μm (the diameter of the first connector 40 and the second connector 50 is increased compared to Experimental Group 3), the pitch is 80 μm, and the ratio of the area covered by the first connector 40 and the second connector 50 on the bottom surface of the electronic integrated circuit 30 is 11.6%. Figure 17 The strain simulation diagram of the solder ball 44 of the first connector 40 of the experimental group 4 is shown, wherein the plastic strain of the solder ball 44 reaches the maximum plastic strain at a ratio of 5.08%, which is improved by 20% compared with the prior art (the plastic strain of the solder ball 44 is reduced). The solder ball 44 with the largest strain is located at Figure 17 In the corner area e.

[0067] Experimental group 5 is a preferred embodiment of the present application, wherein before bonding the electronic integrated circuit 30, no bottom filling layer 62 is formed between the photonic integrated circuit 20 and the substrate 10, and the layout of the first connecting member 40 on the bottom surface of the electronic integrated circuit 30 is as follows: Figure 12 As shown, the diameter of the first connecting member 40 and the second connecting member 50 is 30 μm, the pitch is 45 μm, and the ratio of the area covered by the first connecting member 40 and the second connecting member 50 on the bottom surface of the electronic integrated circuit 30 is 19.4%. Figure 18 The strain simulation diagram of the solder ball 44 of the first connector 40 of the experimental group 5 is shown, wherein the plastic strain of the solder ball 44 reaches the maximum plastic strain at a ratio of 4.04%, which is improved by 44% compared with the prior art (the plastic strain of the solder ball 44 is reduced). The solder ball 44 with the largest strain is located at Figure 18 In the corner area f.

[0068]

[0069] Table 1

[0070] In the embodiment of the present application, second connectors 50 are continuously distributed at the first side 31 and the second side 32 of the bottom surface of the electronic integrated circuit 30 to strengthen the connection between the electronic integrated circuit 30 and the photonic integrated circuit 20 in an area where the warping of the electronic integrated circuit 30 is large (and therefore the stress is also large), and the distribution density of the second connectors 50 in this area is increased. The distribution density of the second connectors 50 is higher than the distribution density of the first connectors 40 to reduce the possibility of cracking of the first connectors 40.

[0071] Figure 19 It is shown that a second underfill layer 62 is formed between the photonic integrated circuit 20 and the substrate 10 , and the second underfill layer 62 covers the bumps 70 .

[0072] Figure 20 The bottom fill layer 60 is formed between the photonic integrated circuit 20 and the electronic integrated circuit 30. The bottom fill layer 60 covers the first connector 40 (and the second connector 50). Thus, the production of the package structure 100 is completed. The package structure 100 is a cubic package (Cubic Package, CuP) as a chip-on-substrate (CoCoS). In some embodiments, a plurality of photonic integrated circuits 20 and the electronic integrated circuits 30 thereon are formed on a continuous substrate 10. Figure 20 After the steps of , a singulation process (such as cutting) is performed to obtain Figure 20 The singulated package structure 100 is shown.

[0073] Figure 21 Shown with Figure 8 In a different embodiment, the second connectors 50 are further distributed on a third side 33 of the bottom surface of the electronic integrated circuit 30, opposite the first side 31, and are continuous with the second connectors 50 on the second side 32. The distribution density of the second connectors 50 on the third side 33 is greater than the distribution density of the first connectors 40. Generally, the stress on one side of the electronic integrated circuit 30 is greatest, while the stress on the two adjacent sides gradually decreases away from the side. In the embodiment of the present application, the second connectors 50 are provided on three consecutive sides of the bottom surface of the electronic integrated circuit 30 to strengthen the connection between the electronic integrated circuit 30 and the photonic integrated circuit 20 in the region of the electronic integrated circuit 30 where the stress is greater, further reducing the likelihood of cracking of the first connectors 40.

[0074] The size of the second connector 50 is the same as or larger than the size of the first connector 40, and the pitch 50 of the second connector is the same as or smaller than the pitch of the first connector 40. Because the second connector 50 does not electrically connect the electronic integrated circuit 30 and the photonic integrated circuit 20, the spacing between the second connectors 50 can be smaller than that of the first connector 40. Even if adjacent second connectors 50 are bridged, no short circuit will occur. In some embodiments, the diameter of the second connector 50 is 10 μm to 45 μm. In some embodiments, the diameter of the second connector 50 is 30 μm to 40 μm. In some embodiments, the pitch of the second connector 50 is 40 μm to 80 μm.

[0075] The bottom surface of the electronic integrated circuit 30 includes a middle region (low stress region), a first region (high stress region) located between the middle region and the first side 31 of the bottom surface, a second region (high stress region) located between the middle region and the second side 32 of the bottom surface connected to the first side 31, and a third region (high stress region) located between the middle region and the third side 33. The distribution density of the first connectors 40 and the second connectors 50 in the first, second, and third regions is greater than the distribution density in the middle region. In some embodiments, the distribution density of the first connectors 40 is less than the distribution density of the second connectors 50 in the first region. The distribution density of the second connectors 50 in the first region is greater than the distribution density in the middle region. In the second region, the distribution density of the first connectors 40 is less than the distribution density of the second connectors 50. The distribution density of the second connectors 50 in the second region is greater than the distribution density in the middle region.

[0076] In some embodiments, the second connecting member 50 is located outside the first connecting member 40. Figures 10 to 12 In some embodiments, the second connecting member 50 is further located between the first connecting members 40. Figure 10 In the embodiment shown, the second connecting member 50 and the first connecting member 40 are located in the same row and column. Figure 11 In the embodiment shown, Figure 10 On the basis of the shown layout, an additional row and column of second connecting members 50 are added.

[0077] The embodiments of the present application solve the problem of first connector 40 cracking by changing the application order of the bottom filling layer 62 and / or adding second connectors 40 as dummy bumps in the area with low density of first connectors 40 below the electronic integrated circuit 30, thereby significantly improving the stress in the area.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A packaging structure, characterized in that: include: substrate; a photonic integrated circuit located on the substrate; an electronic integrated circuit located on the photonic integrated circuit; a first connecting member, located between the electronic integrated circuit and the photonic integrated circuit, for electrically connecting the electronic integrated circuit and the photonic integrated circuit; A second connecting member is located between the electronic integrated circuit and the photonic integrated circuit. The second connecting member does not electrically connect the electronic integrated circuit and the photonic integrated circuit. The second connecting member is continuously distributed at the first side edge and the second side edge of the bottom surface of the electronic integrated circuit. The distribution density of the second connecting member is higher than the distribution density of the first connecting member.

2. The packaging structure according to claim 1, wherein: The second connectors are further continuously distributed on a third side of the bottom surface of the electronic integrated circuit opposite to the first side, and a distribution density of the second connectors on the third side is greater than a distribution density of the first connectors.

3. The packaging structure according to claim 1, wherein: The second connecting member has a size greater than that of the first connecting member.

4. The packaging structure according to claim 3, wherein: The diameter of the second connecting member is 10 μm to 45 μm.

5. The packaging structure according to claim 3, wherein: The diameter of the second connecting member is 30 μm to 40 μm.

6. The packaging structure according to claim 1, wherein: A pitch of the second connecting members is smaller than a pitch of the first connecting members.

7. The packaging structure according to claim 6, wherein: The pitch of the second connecting members is 40 μm to 80 μm.

8. The packaging structure according to claim 1, wherein: The second connecting member is located outside the first connecting member.

9. The packaging structure according to claim 1, wherein: The lateral dimension of the substrate is larger than the lateral dimension of the photonic integrated circuit.

10. The packaging structure according to claim 9, wherein: The electronic integrated circuit has a lateral dimension greater than a lateral dimension of the photonic integrated circuit.

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