Test structure for monitoring injection shadow effect

Abstract

The utility model provides a test structure for monitoring an injection shadow effect. The test structure comprises a substrate, an active region, a metal interconnection structure and a polycrystalline silicon structure, the active regions are arranged on the substrate, and the polycrystalline silicon structure stretches across at least one active region and covers part of the surface of the active region; a metal interconnection structure is arranged on at least one active region and is used for connecting out a target active region; wherein the target active region comprises at least one active region which is determined in the at least one active region on the basis of the polycrystalline silicon structure and / or the boundary of the active region. The test structure is simple in structure and easy to manufacture, is suitable for monitoring the injection shadow effect in the IO manufacturing process, can effectively judge the influence degree of the injection shadow effect on the working characteristics of a device, and is beneficial to improving the performance level and the product yield of the device.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor design and production, and in particular relates to a test structure for monitoring injection shadow effects. Background Art

[0002] In the semiconductor manufacturing process, ion implantation is a key step used to dope semiconductor materials. Under ideal process conditions, ion implantation perpendicular to the wafer is relatively uniform. However, in the well / LDD / PKT (well / lightly doped drain / pocket doping) ion implantation process, in order to reduce the channel effect, the ion implantation is generally not perpendicular to the silicon wafer, but the wafer is tilted at a certain angle to implant, which will cause a shadow effect. Normal AA / STI (active area / shallow trench isolation) boundaries are also prone to step height (step height, that is, the height difference between different material layers on the wafer surface), which is unstable. If a wall of "poly (polysilicon)" is placed across, the impact of the implantation shadow effect will be aggravated. For details, please refer to Figure 11 The diagram shows the formation of the implantation shadow effect. In the diagram, Polysilicon refers to polycrystalline silicon, Substrate refers to substrate, Ion Beam refers to ion beam, doped region refers to doped region, and shadowed region refers to shadow region.

[0003] With the continuous development of large-scale integrated circuit (LSI) process technology, the integration of circuits continues to increase. In the 28nm IO process flow, L-shaped and U-shaped poly (L-shaped polysilicon structures and U-shaped polysilicon structures) are allowed. Compared with a single line-shaped poly (i.e., a linear polysilicon structure), L-shaped and U-shaped gate resistances are lower. At the same time, for U-shaped poly, two fingers share a source or drain, which to a certain extent also reduces the layout area and parasitic capacitance, improving the AC performance of the device. However, when such poly has corners, it also exacerbates the injection shadow effect, that is, the phenomenon that ions cannot be injected into the bottom area, which ultimately affects parameters such as the threshold voltage of the transistor, thereby resulting in yield loss.

[0004] Currently, there is no test structure to monitor these process weaknesses. Therefore, a test structure is needed to monitor and characterize the impact of the injection shadow effect, determine the extent of the shadow effect on device operating characteristics, and study how to minimize the shadow effect. Utility Model Content

[0005] In order to solve all or part of the problems in the prior art mentioned above, the present invention provides a test structure for monitoring injection shadow effect, so as to monitor and characterize the influence of injection shadow effect on the operating characteristics of the device.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a test structure for monitoring implant shadowing effects, the test structure comprising a substrate, an active area, a metal interconnect structure, and a polysilicon structure; the active area is disposed on the substrate, the polysilicon structure spanning at least one of the active areas and covering a portion of the surface of the active area; a metal interconnect structure is disposed on at least one of the active areas for connecting to a target active area; wherein the target active area includes at least one active area region including an ion implantation region, determined based on the polysilicon structure and / or the boundaries of the active area within at least one of the active areas. Through this test structure, the resistance of the target active area can be measured, and by observing the different resistance changes under different polysilicon structures, the impact of implant shadowing effects on devices with different polysilicon structures can be monitored and characterized.

[0007] In some embodiments, the target active region includes an active area; the metal interconnect structure includes contact holes; and at least one contact hole is provided at each end of the target active region for connecting the target active region. The resistance of a single active area region can be measured to characterize operating characteristics.

[0008] In some embodiments, the target active area includes multiple active regions; the metal interconnect structure includes contact holes and metal lines; at least one contact hole is provided at each end of each active region, and the multiple active regions are connected in series by the metal lines and the contact holes. The resistance of the multiple active regions can be measured to characterize operating characteristics and improve test sensitivity.

[0009] In some embodiments, the polysilicon structure is a linear polysilicon structure or an L-shaped polysilicon structure; the polysilicon structure includes a first polysilicon portion covering a portion of the surface of the active area; the L-shaped polysilicon structure also includes a second polysilicon portion arranged in a direction perpendicular to the first polysilicon portion; the first polysilicon portion and the second polysilicon portion are connected to each other to form the L-shaped polysilicon structure or are connected through the remaining polysilicon portion in the L-shaped polysilicon structure to form the L-shaped polysilicon structure. The L-shaped polysilicon structure can be monitored and characterized, that is, a test structure is provided that can monitor the implant shadowing effect when polysilicon has corners.

[0010] In some embodiments, the polysilicon structure is a U-shaped polysilicon structure; the polysilicon structure includes at least two first polysilicon portions covering a portion of the surface of the active area; the polysilicon structure also includes a second polysilicon portion arranged in a direction perpendicular to the first polysilicon portion; the first polysilicon portion and the second polysilicon portion are interconnected to form the U-shaped polysilicon structure or are connected through the remaining polysilicon portion in the polysilicon structure to form the U-shaped polysilicon structure. The U-shaped polysilicon structure can be monitored and characterized, that is, a test structure is provided that can monitor the implant shadowing effect when polysilicon has corners.

[0011] In some embodiments, the test structure further includes dummy polysilicon; the dummy polysilicon spans at least one of the active areas and covers a portion of the surface of the surrounding active areas; wherein the surrounding active areas refer to active area regions that do not belong to the target active area. By providing dummy polysilicon (dummy poly) around the test structure and increasing the amount of polysilicon around the test structure, the area of ​​ion implantation in that area is increased, which may increase the impact of the implant shadow effect. The test structure of this embodiment can be used to test the impact of the implant shadow effect on the device when the surrounding polysilicon is increased and the degree of the impact can be characterized.

[0012] In some of the embodiments, the setting is based on at least one preset information of polysilicon morphology, width of the first polysilicon portion, distance value between polysilicon and active area, total length of the second polysilicon portion, width value of the second polysilicon portion, number of first polysilicon portions, width value of target active area, length value of target active area, distance value of adjacent target active area, and width value of virtual polysilicon.

[0013] On the other hand, the present application also provides a test structure for monitoring the injection shadow effect, comprising a substrate, an active area, a metal interconnect structure and a polysilicon structure; the active area is arranged on the substrate, the polysilicon structure spans at least one of the active areas and covers a portion of the surface of the active area; a metal interconnect structure is arranged on at least one of the active areas for connecting a target object; wherein the target object includes a target active area or a target transistor; the target active area includes at least one active area region determined in at least one of the active areas based on the boundary of the polysilicon structure and / or the active area; when the target object is a target transistor, the gate port, source port, drain port and body port of the target transistor are connected through the metal interconnect structure. Through this test structure, the influence of the polysilicon part on the injection shadow effect can be monitored and characterized by measuring the resistance of the active area (the target object uses the target active area) or measuring the electrical properties such as the threshold voltage (Vts) and source-drain current (Ids) of the MOS (the target object uses the target transistor), and the changes in the electrical properties under different polysilicon parts.

[0014] In some embodiments, when the target object is a target active area, the test structure for monitoring the injection shadow effect is set based on the test structure described in any one of the first aspects.

[0015] When the target object is a target transistor, it is set based on the preset position information of the target transistor in the polysilicon part; the test structure for monitoring the injection shadow effect is set based on the test structure described in the first aspect (morphological limitation of the polysilicon structure, description limitation of the virtual polysilicon, and preset information setting limitation).

[0016] Compared with the prior art, the main beneficial effects of the present invention are: 1) providing a test structure for monitoring and characterizing the injection shadow effect; 2) providing a variety of test structures that can effectively monitor and characterize the impact of the shadow effect in various situations; 3) different test methods can be used for monitoring and characterization, with a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic diagram of a test structure of a linear polysilicon structure provided in Example 1 of the present utility model.

[0019] Figure 2 This is a schematic diagram of a test structure of an L-shaped polysilicon structure provided in Example 2 of the present utility model.

[0020] Figure 3 This is a schematic diagram of a test structure of a U-shaped polysilicon structure provided in Example 3 of the present utility model.

[0021] Figure 4 This is a schematic diagram of a test structure for adjusting the number of fingers in a U-shaped polysilicon structure and the location of a target active area, provided in Example 4 of the present invention. Figure a shows the test structure when the target active area is active area region A, and figure b shows the test structure when the target active area is active area region B.

[0022] Figure 5 This is a schematic diagram of a test structure in the presence of virtual polysilicon provided in the fifth embodiment of the present invention.

[0023] Figure 6 A schematic diagram of a test structure in which a target active area includes multiple active area regions is provided in Example 6 of the present utility model.

[0024] Figure 7 This is a schematic diagram of a test structure of a linear polysilicon structure provided in Example 7 of the present utility model.

[0025] Figure 8 This is a schematic diagram of a test structure of an L-shaped polysilicon structure provided in Example 8 of the present utility model.

[0026] Figure 9 This is a schematic diagram of a test structure of a U-shaped polysilicon structure provided in Example 9 of the present utility model.

[0027] Figure 10 This is a schematic diagram of a structure for adjusting the number of fingers of a U-shaped polysilicon structure and the position of a target transistor provided by the tenth embodiment of the present invention. Figures a and b are schematic diagrams of test structures with two different target transistor positions.

[0028] Figure 11 Schematic diagram of injecting shadow effect into (Shadow Effect). DETAILED DESCRIPTION

[0029] The aforementioned and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are merely references to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0030] The presence of polysilicon structures can affect the injection shadowing effect, which in turn affects device performance. By measuring the resistance of the active area or electrical properties such as the transistor's threshold voltage and source-drain current, the impact of the injection shadowing effect can be monitored and characterized. For example, the greater the injection shadowing effect, the larger the shadowed area, the weaker the corresponding active area's electrical capacity, and the greater the measured resistance of the active area. To this end, the following test structures have been designed to monitor and characterize the injection shadowing effect in IO processes.

[0031] Example 1:

[0032] like Figure 1 FIG2 is a schematic diagram of a test structure for monitoring an injection shadow effect provided by the first embodiment of the present invention, wherein the polysilicon structure is a linear polysilicon structure.

[0033] A test structure for monitoring the injection shadow effect. In this embodiment, the test structure includes: a substrate (not shown), an active area (i.e., AA), a contact hole (i.e., CT), and a polysilicon structure (i.e., Poly). The active area is disposed on the substrate, and the polysilicon structure is a long strip (i.e., a linear polysilicon structure) that spans the active area and covers a portion of the surface of the active area. The portion of the linear polysilicon structure that covers the surface of the active area is referred to herein as the first polysilicon portion, and the portion that exceeds the active area is referred to as the remaining polysilicon portion. In this embodiment, the linear polysilicon structure exceeds the active area in both the upper and lower directions. In other embodiments, the linear polysilicon structure may exceed the active area on one side, or may not exceed the active area on both sides.

[0034] In this embodiment, the first polysilicon portion divides the active area into two small active area regions on the left and right. Here, we can determine an active area region as the target active area to be connected for testing based on the polysilicon structure (i.e., the first polysilicon portion therein) and / or the boundary of the active area. Here, the active area region on the right is taken as the target active area, and four contact holes (i.e., a part of the metal interconnection structure, which is generally connected to the active area region as a pin through a metal wire) are set on the active area region on the right for connection. The contact holes are set in groups of two and are respectively set at the upper and lower ends of the active area on the same side of the first polysilicon portion. In other embodiments, there are at least two contact holes, and at least one is set at each of the upper and lower ends of the active area to realize the two-terminal method of measuring resistance or the four-terminal method of measuring resistance. It can be understood that the target active area includes the area after ion implantation.

[0035] like Figure 1As shown, in this embodiment, testing can be performed through the above four pins (only the contact holes are marked in the figure, and metal wires are generally used as pins). That is, the resistance of the target active area of ​​the MOS in the off state can be measured through the above four pins using the Kelvin four-terminal method. The resistance area measured is the resistance of the target active area between the two voltage contacts V1 and V2. The specific calculation method is as follows: R = abs(V1-V2) / I1 or R = abs(V1-V2) / I2, where abs refers to the absolute value; V1 and V2 are the voltage values ​​measured by applying current to pins V1 and V2, respectively, and I1 and I2 are the current values ​​measured by applying voltage to pins I1 and I2, respectively. Alternatively, the two-terminal method can be used for measurement, that is, selecting a contact hole at each end of the target active area for testing. Generally, the Kelvin four-terminal method provides more accurate test results and is recommended. However, in other embodiments, when the number of contact holes is less than four, the two-terminal method can be used for testing.

[0036] In this embodiment, the contact holes are all arranged very close to the boundary, and the distance from the boundary to the target active area can be ignored, so the measured resistance value is the resistance value of the entire target active area on the right side.

[0037] In fact, during actual testing, the positions of I1 / V1 and I1 / V2 are interchangeable. In addition, in other embodiments, the positions of the contact holes are also adjustable, but the range of the target active area actually measured also changes accordingly.

[0038] In this embodiment, the target active area is described as a single active area region. To improve the sensitivity of the test results, in other embodiments, the target active area may include multiple active area regions, and the multiple active area regions are connected in series before being tested. That is, at least two contact holes are provided in each active area region, and the contact holes in two adjacent active area regions are sequentially connected through a metal interconnect structure (including contact holes and metal lines), thereby connecting the multiple active area regions in series. During testing, the resistance is tested by connecting through the contact holes at both ends of the test link formed by the series connection. The specific technical solution for the test structure in which the target active area includes multiple active area regions is described in the subsequent embodiments.

[0039] To characterize the impact of the shadow effect on devices with different first polysilicon widths (i.e., L), a test structure can be configured using preset information within the design rule (DR) as a variable dimension. Similarly, preset information such as the target active area width, target active area length, and distance between adjacent target active areas can also be configured as needed.

[0040] Example 2:

[0041] like Figure 2 The diagram shown is a schematic diagram of a test structure for monitoring the injection shadow effect provided by the second embodiment of the present invention, wherein the polysilicon structure is an L-shaped polysilicon structure.

[0042] The basic structure of the second embodiment is similar to that of the first embodiment, except that the shape of the polysilicon structure (i.e., polysilicon shape) is different. Figure 2 As shown, in this embodiment, the polysilicon structure includes a first polysilicon portion and a second polysilicon portion, and the second polysilicon portion is arranged in a direction perpendicular to the first polysilicon portion; here, the portion of the polysilicon structure covering the surface of the active area is called the first polysilicon portion, and the exceeding portion is the remaining polysilicon portion.

[0043] In this embodiment, the first polysilicon portion and the second polysilicon portion are formed by connecting the remaining polysilicon portion in the polysilicon structure; in other embodiments, the first polysilicon portion and the second polysilicon portion may be directly connected to form an L-shaped polysilicon structure.

[0044] In this embodiment, the polysilicon structure exceeds the range of the active area in both the upper and lower directions; in other embodiments, the polysilicon structure may exceed the range of the active area on one side or on neither side.

[0045] In this embodiment, a contact hole is also provided on the target active area to connect it out. In other embodiments, there are at least two contact holes, and at least one is provided at each of the upper and lower ends of the active area.

[0046] The connection and testing methods are the same as those in the first embodiment and will not be described in detail here.

[0047] In order to characterize the influence of the size of the polysilicon structure, in other embodiments, the width of the first polysilicon portion (ie, L in the figure), the total length of the second polysilicon portion (ie, L in the figure) bottom ), the width of the second polysilicon portion (ie, W bottom ), the distance between polysilicon and the active area (i.e., the Poly-to-AA space in the figure), the width of the target active area, the length of the target active area, and the distance between adjacent target active areas and other preset information can also be set according to needs.

[0048] In order to improve the sensitivity of the test results, in other embodiments, the target active region may include multiple active regions and the active regions are connected in series before testing. The connection method and the testing method are described in the first embodiment.

[0049] Example 3:

[0050] like Figure 3 The schematic diagram of a test structure for monitoring the injection shadow effect provided by the third embodiment of the present invention is shown, wherein the polysilicon structure is a U-shaped polysilicon structure.

[0051] The basic structure of the third embodiment is similar to that of the second embodiment, except for the shape of the polysilicon structure. Figure 3 As shown, in this embodiment, the polysilicon structure includes two first polysilicon sections (i.e., nfinger=2) and one second polysilicon section. The two first polysilicon sections are arranged in parallel, and the second polysilicon section is arranged in a direction perpendicular to the first polysilicon section. Here, the portion of the polysilicon structure covering the surface of the active area is called the first polysilicon section, and the exceeding portion is the remaining polysilicon portion.

[0052] In this embodiment, two segments of first polysilicon and one segment of second polysilicon are formed by sequentially connecting the remaining polysilicon portions in the polysilicon structure; in other embodiments, two segments of first polysilicon and one segment of second polysilicon can also be directly connected in sequence to form a U-shaped polysilicon structure.

[0053] In this embodiment, the polysilicon structure exceeds the range of the active area in both the upper and lower directions; in other embodiments, the polysilicon structure may exceed the range of the active area on one side or on neither side.

[0054] In this embodiment, four test pins are provided on the target active area (only four contact holes are shown in the figure; in practice, metal wires can be used to connect them as test pins). In other embodiments, at least two contact holes are provided (metal wires can be used to connect them as test pins during actual testing), with at least one contact hole provided at each of the upper and lower ends of the active area.

[0055] The test method is the same as that in Example 1 and will not be described in detail here.

[0056] In order to characterize the influence of the size of the polysilicon structure, in other embodiments, the width of the first polysilicon portion (ie, L in the figure), the total length of the second polysilicon portion (ie, L in the figure) bottom ), the width of the second polysilicon portion (ie, W bottom ), the distance between polysilicon and the active area (i.e., the Poly-to-AA space in the figure), the width of the target active area, the length of the target active area, and the distance between adjacent target active areas and other preset information can also be set according to needs.

[0057] To improve the sensitivity of the test results, in other embodiments, the target active region may include multiple active regions, and the active regions are connected in series before being tested. The connection method and the test method are described in the first embodiment.

[0058] Example 4:

[0059] like Figure 4 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the fourth embodiment of the present invention, wherein the polysilicon structure is a U-shaped polysilicon structure, and provides two specific implementation methods for the number of fingers and the target active area setting. Figure 4 a and b in FIG. 5 respectively show the test structure when the target active area is active area region A and the test structure when the target active area is active area region B.

[0060] The basic structure of the fourth embodiment is similar to that of the third embodiment, except for the shape of the polysilicon structure. Figure 4 As shown, in this embodiment, the first polysilicon portion has four segments (i.e., nfinger = 4) arranged in parallel across the active area, and the second polysilicon portion has three segments. The first and second polysilicon portions are sequentially connected through the remaining polysilicon portions, and the second polysilicon portions are staggered on both sides of the active area. In other embodiments, the first and second polysilicon portions can also be directly connected in sequence to form a U-shaped polysilicon structure.

[0061] In this embodiment, the polysilicon structure exceeds the range of the active area in both the upper and lower directions; in other embodiments, the polysilicon structure may exceed the range of the active area on one side or on neither side.

[0062] In other embodiments, there are at least two contact holes, and at least one contact hole is provided at each of the upper and lower ends of the corresponding active region. The testing method is the same as that of the first embodiment and will not be described in detail here.

[0063] It should be noted that, although in the present embodiment, the polysilicon structure is composed of four segments of the first polysilicon portion (i.e., the number of fingers of the U-shaped structure is four) and three segments of the second polysilicon portion, the specific number of fingers is not limited. In other embodiments, the number of fingers of the U-shaped polysilicon structure in the test structure can be other data that meets the design rules. In other embodiments, the first polysilicon portion has N segments, N is a positive integer, N ≥ 3, and is arranged in parallel on the active area, the second polysilicon portion has N-1 segments, the first polysilicon portion and the second polysilicon portion are connected in sequence or connected in sequence through the remaining polysilicon portion, and the second polysilicon portion is staggered on both sides of the active area, and there are at least 2 contact holes for connecting the target active area to the measured resistance.

[0064] In order to characterize the influence of the size of the polysilicon structure, in other embodiments, the width of the first polysilicon portion (ie, L in the figure), the total length of the second polysilicon portion (ie, L in the figure) bottom ), the width of the second polysilicon portion (ie, W bottom), the distance value between polysilicon and the active area (i.e., the Poly-to-AA space in the figure), the number of first polysilicon parts, the width value of the target active area, the length value of the target active area, and the distance value of adjacent target active areas and other preset information can also be set according to needs.

[0065] To improve the sensitivity of the test results, in other embodiments, the target active region may include multiple active regions, and the active regions are connected in series before being tested. The connection method and the test method are described in the first embodiment.

[0066] Embodiment 5:

[0067] like Figure 5 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the fifth embodiment of the present invention, in which virtual polysilicon is provided.

[0068] The basic structure of Example 5 is similar to that of Example 4, except that dummy polysilicon (i.e., Dummy Poly) is further provided. The dummy polysilicon spans at least one of the active areas and covers part of the surface of the surrounding active areas. The surrounding active areas refer to active areas that do not belong to the target active areas. The dummy polysilicon is provided in the test structure mainly to characterize the impact of the injection shadow effect on the test structure provided with different numbers of dummy polysilicon. The setting of dummy polysilicon simulates the actual working situation of the chip. The dummy polysilicon can be drawn manually or automatically filled in by the design software. If the value of the poly space (i.e., the distance between two adjacent first polysilicon portions) is large, some dummy polysilicon may be inserted.

[0069] like Figure 5 As shown, in this embodiment, two dummy polysilicon strips are provided. The dummy polysilicon strips are provided in parallel with the first polysilicon portion, and the two dummy polysilicon strips are provided on the active area where no contact holes are provided. Figure 5 It can be seen that the side of the dummy polysilicon away from the second polysilicon portion exceeds the boundary of the active region, while the side close to the second polysilicon portion is within the active region.

[0070] In other embodiments, there are at least two contact holes, and at least one is provided at each of the upper and lower ends of the active region. The testing method is the same as that of the first embodiment and will not be described in detail here.

[0071] In other embodiments, the number of fingers of the U-shaped polysilicon structure in the test structure can be other data that meets the design rules. In other embodiments, the first polysilicon portion has N segments, N is a positive integer, N ≥ 3, and is arranged in parallel on the active area. The second polysilicon portion has N-1 segments. The first polysilicon portion and the second polysilicon portion are connected in sequence or connected in sequence through the remaining polysilicon portion, and the second polysilicon portion is staggered on both sides of the active area. There are at least two contact holes for connecting the target active area to the measured resistance. At this time, the number of dummy polysilicon can also be increased accordingly and can be set on any active area without a contact hole.

[0072] In order to characterize the influence of the size of the polysilicon structure, in other embodiments, the width of the first polysilicon portion (ie, L in the figure), the total length of the second polysilicon portion (ie, L in the figure) bottom ), the width of the second polysilicon portion (ie, W bottom ), the distance value between polysilicon and the active area (i.e., the Poly-to-AA space in the figure), the number of first polysilicon parts, the width value of the target active area, the length value of the target active area, and the distance value of adjacent target active areas and other preset information can also be set according to needs.

[0073] To improve the sensitivity of the test results, in other embodiments, the target active region may include multiple active regions, and the active regions are connected in series before being tested. The connection method and the test method are described in the first embodiment.

[0074] Example 6:

[0075] like Figure 6 FIG2 is a schematic diagram of a test structure for monitoring injection shadow effects provided by a sixth embodiment of the present invention, wherein a target active area is provided with a plurality of active area regions.

[0076] To improve sensitivity, multiple active regions can be connected in series for testing. This embodiment provides a test structure that can connect multiple active regions in series and then test the resistance to characterize the impact of the injection shadow effect.

[0077] like Figure 6 As shown, the test structure includes: a substrate, an active area, a contact hole, a metal line (ie, M1), a first polysilicon portion, and a second polysilicon portion. Figure 6 As shown, in this embodiment, three active regions are arranged in parallel on the substrate in the vertical direction (the substrate is Figure 6(not shown in the figure), the first polysilicon portion has 12 segments, which are arranged across the three active areas in the form of three rows and four columns. The three segments of the first polysilicon portion in the same column are connected as a whole through the remaining part of the polysilicon structure, and then connected to the second polysilicon portion through the remaining part of the polysilicon structure, and the second polysilicon portions are staggered on both sides of the three active areas; the three active areas are divided into several small active areas by the 12 segments of the first polysilicon portions, and two contact holes are provided on the upper and lower sides of the small active area to be tested (in other embodiments, there are at least two contact holes), and all the small active areas to be tested (active areas with contact holes can be used as areas to be tested, that is, target active areas) are connected in series through metal wires into a test link, and are connected to the two first pins at the beginning and end of the link for testing.

[0078] Using the two-terminal method to measure resistance, the current flows from M1(snake pin1)→AA→M1→AA→M1→AA→M1→AA→M1→AA→M1→AA→M1(snake pin2), which includes Figure 6 The resistance values ​​of the six target active areas with contact holes are included in the calculation (the actual situation includes the resistance values ​​of the six target active areas and the resistance values ​​of the seven metal interconnect structures (contact holes and metal lines) used for connection. However, the resistance of the active area and the resistance of the metal interconnect structure are very different. The resistance value of the metal interconnect structure is very small and can be ignored. Of course, it can also be included in the calculation to obtain a more accurate result).

[0079] In order to characterize the influence of the size of the polysilicon structure, in other embodiments, the width of the first polysilicon portion (ie, L in the figure), the total length of the second polysilicon portion (ie, L in the figure) bottom ), the width of the second polysilicon portion (ie, W bottom ), the distance value between the polysilicon and the active area (i.e., the Poly-to-AA space in the figure), the number of first polysilicon parts, the width value of the target active area, the length value of the target active area, the distance value of the adjacent target active area, and the width value of the virtual polysilicon and other preset information can also be set according to needs.

[0080] In this embodiment, a U-shaped polysilicon structure is used as an example to introduce the test structure when the target active area includes multiple active area regions. It can be understood that the polysilicon structures in other embodiments, such as linear polysilicon structures or L-shaped polysilicon structures, can also be connected in series and tested with reference to this method.

[0081] Embodiment seven:

[0082] like Figure 7 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the seventh embodiment of the present utility model, wherein the polysilicon structure is a linear polysilicon structure.

[0083] A test structure for monitoring the injection shadowing effect. In this embodiment, the test structure includes: a substrate (not shown), an active area (i.e., AA), a contact hole (i.e., CT), and a polysilicon structure (i.e., Poly). The active area is disposed on the substrate, and the polysilicon structure is a long strip (i.e., a linear polysilicon structure) that spans the active area and covers a portion of the active area's surface. The portion of the linear polysilicon structure that covers the active area's surface is referred to herein as the first polysilicon portion, while the portion that exceeds the active area is referred to as the remaining polysilicon portion. In this embodiment, the polysilicon structure extends beyond the active area in both the vertical and horizontal directions. In other embodiments, the linear polysilicon structure may extend beyond the active area on one side, or may not extend beyond the active area on both sides.

[0084] In this embodiment, there are four contact holes, which are respectively arranged on the linear polysilicon structure, on the active area on both sides of the first polysilicon part in the polysilicon structure, and on the substrate (the substrate is located on the back of the active area and is not shown in the figure). It can be understood that the target object to be connected in the test structure here is a transistor structure, which may be referred to as the target transistor below. The above-mentioned four contact holes are respectively the gate port, source port, drain port and body port of the target transistor. The target transistor is connected by respectively connecting the gate port, source port, drain port and body port of the target transistor through a metal interconnect structure (including contact holes and metal lines).

[0085] When the test structure includes a target transistor, electrical properties such as threshold voltage (Vts) and source-drain current (Ids) can be measured through four contact holes of the target transistor.

[0086] In other embodiments, the test structure may include multiple target transistors. In this case, the multiple target transistors can be connected in parallel or in series through a metal interconnection structure (including contact holes and metal lines) to form a test structure. The number of target transistors can be in the range of 10,000 to 100,000 and can be connected through the metal interconnection structure. The relevant electrical performance can also be measured.

[0087] The following is a specific introduction using the parallel method as an example: through the gate port of the target transistor, the gate ports of multiple target transistors are connected together using metal wires, and any one of the contact holes is used as the port for connection to the test; the source ports are connected together using metal wires through the contact holes, and any one of the contact holes is used as the port for connection to the test; the drain ports are connected together using metal wires through the contact holes, and any one of the contact holes is used as the port for connection to the test; all the body ports are connected together using metal wires through the contact holes, and any one of the contact holes is used as the port for connection to the test; through the above 4 contact holes used as test ports, the electrical properties such as threshold voltage (Vts), source leakage current (Ids) and so on of multiple target transistors in parallel can be measured.

[0088] Threshold voltage measurement method: For NMOS, the source and body are grounded, the drain is connected to a positive voltage, and the gate is connected to a scan voltage. The threshold voltage is extracted when the drain current reaches a certain value. For PMOS, the source and body are grounded, the drain is connected to a negative voltage, and the gate is also connected to a scan voltage. The threshold voltage is extracted when the drain current reaches a certain value.

[0089] Source-drain current measurement method: Source-drain current is the saturation current of the inversion channel between the source and the drain. Usually, voltage is applied to the gate and the drain, the source and the body are grounded, and the current is measured at the drain.

[0090] In other embodiments, the number and positions of the contact holes are not strictly limited, that is, there are at least four contact holes, wherein the four contact holes for lead-out testing can be respectively set at any position on the polysilicon structure, any position on the active area on both sides of the first polysilicon part in the polysilicon structure, and any position on the substrate.

[0091] Embodiment 8:

[0092] like Figure 8 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the eighth embodiment of the present utility model, wherein the polysilicon structure is an L-shaped polysilicon structure.

[0093] The basic structure of the eighth embodiment is similar to that of the seventh embodiment, except for the shape of the polysilicon portion. Figure 8 As shown, in this embodiment, the polysilicon structure further includes a second polysilicon portion. The formation of the L-shaped polysilicon structure can refer to the second embodiment.

[0094] When the test structure is a target transistor, electrical properties such as threshold voltage (Vts) and source-drain current (Ids) can be measured through the four contact holes of the test structure.

[0095] When the test structure consists of multiple target transistors, a metal interconnection structure (including contact holes and metal lines) is also provided. Multiple target transistors are connected in parallel or in series through the metal interconnection structure to form a test structure. The number of target transistors can be in the range of 10,000 to 100,000 and can be connected through the metal interconnection structure. The relevant electrical performance can also be measured.

[0096] Embodiment 9:

[0097] like Figure 9 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the ninth embodiment of the present invention, wherein the polysilicon structure is a U-shaped polysilicon structure.

[0098] The basic structure of the ninth embodiment is similar to that of the eighth embodiment, except for the shape of the polysilicon structure. Figure 9 As shown in FIG. 1 , in this embodiment, the polysilicon structure is provided with two first polysilicon sections and one second polysilicon section. The formation of the U-shaped polysilicon structure may refer to the third embodiment.

[0099] It is understood that different test structures can be set based on the different preset positions of the target transistor in the polysilicon portion. Figure 9 As shown, the target transistor is located in the left portion of the polysilicon portion. In this embodiment, there are six contact holes (in other embodiments, at least four contact holes are sufficient). One contact hole is provided on the polysilicon structure and one contact hole is provided on the substrate. Two contact holes are provided on each of the active regions on both sides of the first polysilicon portion of the polysilicon structure. Electrical properties such as threshold voltage (Vts) and source-drain current (Ids) can be measured by using at least four contact holes, through the two contact holes provided on the polysilicon structure and the substrate, and by selecting either one contact hole or both contact holes on the left and right active regions.

[0100] When the test structure consists of multiple target transistors, a metal interconnection structure (including contact holes and metal lines) is also provided. Multiple target transistors are connected in parallel or in series through the metal interconnection structure to form a test structure. The number of target transistors can be in the range of 10,000 to 100,000 and can be connected through the metal interconnection structure. The relevant electrical performance can also be measured.

[0101] Embodiment 10:

[0102] like Figure 10 The figure shows a schematic diagram of a test structure for monitoring the injection shadow effect provided by the tenth embodiment of the present utility model, wherein the polysilicon structure is a U-shaped polysilicon structure, and provides two specific implementation methods for setting target transistors.

[0103] The basic structure of the tenth embodiment is similar to that of the ninth embodiment, except for the shape of the polysilicon structure. Figure 10 As shown, in this embodiment, the first polysilicon portion has four sections, which are arranged in parallel across the active area, and the second polysilicon portion has three sections. The formation of this polysilicon structure can refer to the fourth embodiment.

[0104] It is understood that different test structures can be set based on the different preset positions of the target transistor in the polysilicon portion. Figure 10 As shown, the first polysilicon portion has 4 segments (ie, nfinger=4), which corresponds to the presence of 4 preset positions of the target transistors. According to the symmetric relationship, Figure 10 There are two types of a and b. Figure 10 As shown, in this embodiment, there are 6 contact holes (in other embodiments, there may be at least 4 contact holes). Using the above at least 4 contact holes, electrical properties such as threshold voltage (Vts) and source-drain current (Ids) can be measured.

[0105] When the test structure consists of multiple target transistors, a metal interconnection structure (including contact holes and metal lines) is also provided. Multiple target transistors are connected in parallel or in series through the metal interconnection structure to form a test structure. The number of target transistors can be in the range of 10,000 to 100,000 and can be connected through the metal interconnection structure. The relevant electrical performance can also be measured.

[0106] In other embodiments, the number of fingers of the U-shaped polysilicon structure in the test structure can be other data that meet the design rules and is not limited to Figure 10 In other embodiments, the first polysilicon portion has N segments, where N is a positive integer and N≥3, and is arranged in parallel on the active area. The second polysilicon portion has N-1 segments. The first polysilicon portion and the second polysilicon portion are sequentially connected or sequentially connected through the remaining polysilicon portions. The second polysilicon portions are staggered on both sides of the active area. At least four contact holes are provided, respectively for connecting to the gate port, source port, drain port, and body port of the target transistor.

[0107] The above ten embodiments are used to illustrate ten test structures in combination with the accompanying drawings. The test structure of the present invention is not limited to the above embodiments. The test structure can be one or more. It can be one test structure in the embodiment or a combination of any multiple test structures in the embodiment. The number of target objects in the test structure can be in the range of 10,000 to 100,000. There is no requirement for each test structure to maintain the same number of variables, nor is there a limit on the measurement method. Each test structure can be measured individually, all in series, or all in parallel, and can be set according to the specific application scenario.

[0108] At the same time, a control group can be set up for the experiment. For example, the simplest one can be composed of one control group and one or more experimental groups. The experimental group can be the experimental group in the specific embodiment, which is obtained by simple size changes or quantity changes. For the control group and the experimental group, it is necessary to keep the other variables the same according to the purpose of the experiment. For the measurement method, the control group and the experimental group need to be tested separately, but for example, the basic units in the same control group / the same experimental group can be measured individually, all in series, or all in parallel, which can be set according to the specific application scenario.

Claims

1. A test structure for monitoring injection shadow effects, characterized in that The test structure includes a substrate, an active area, a metal interconnection structure and a polysilicon structure; The active area is provided on the substrate, and the polysilicon structure spans over at least one of the active areas and covers a portion of the surface of the active area; Disposing a metal interconnect structure on at least one of the active areas for connecting the target active area; The target active region includes at least one active region region including an ion implantation region determined in at least one of the active regions based on the polysilicon structure and / or the boundary of the active region.

2. A test structure for monitoring injection shadow effects according to claim 1, characterized in that: The target active region includes an active region area; The metal interconnect structure includes a contact hole; At least one contact hole is provided at each end of the target active area for connecting the target active area.

3. A test structure for monitoring injection shadow effects according to claim 1, characterized in that: The target active area includes a plurality of active area regions; The metal interconnect structure includes contact holes and metal lines; At least one contact hole is provided at both ends of each active region, and the multiple active regions are connected in series by metal wires and the contact holes.

4. A test structure for monitoring injection shadow effects according to claim 1, characterized in that: The polysilicon structure is a linear polysilicon structure or an L-shaped polysilicon structure; The polysilicon structure includes a first polysilicon portion covering a portion of the surface of the active area; Among them, the L-shaped polysilicon structure also includes a second polysilicon portion arranged in a direction perpendicular to the first polysilicon portion; the first polysilicon portion and the second polysilicon portion are connected to each other to form the L-shaped polysilicon structure or are connected through the remaining polysilicon portion in the L-shaped polysilicon structure to form the L-shaped polysilicon structure.

5. The test structure for monitoring injection shadow effect according to claim 1, characterized in that: The polysilicon structure is a U-shaped polysilicon structure; The polysilicon structure includes at least two first polysilicon portions covering a portion of the surface of the active area; The polysilicon structure further includes a second polysilicon portion arranged in a direction perpendicular to the first polysilicon portion; The first polysilicon portion and the second polysilicon portion are connected to each other to form the U-shaped polysilicon structure or are connected through the remaining polysilicon portion in the polysilicon structure to form the U-shaped polysilicon structure.

6. A test structure for monitoring injection shadow effects according to claim 5, characterized in that: The test structure also includes virtual polysilicon; The dummy polysilicon spans across at least one of the active areas and covers a portion of the surface of the surrounding active areas; The surrounding active area refers to an active area that does not belong to the target active area.

7. A test structure for monitoring injection shadow effects according to any one of claims 4 to 6, characterized in that: It is set based on at least one preset information of the polysilicon morphology, the width of the first polysilicon portion, the distance value between the polysilicon and the active area, the total length of the second polysilicon portion, the width value of the second polysilicon portion, the number of first polysilicon portions, the width value of the target active area, the length value of the target active area, the distance value of the adjacent target active area, and the width value of the virtual polysilicon.

8. A test structure for monitoring injection shadow effects, characterized in that including substrate, active area, metal interconnect structure and polysilicon structure; The active area is provided on the substrate, and the polysilicon structure spans over at least one of the active areas and covers a portion of the surface of the active area; Disposing a metal interconnect structure on at least one of the active areas for connecting a target object; Wherein, the target object includes a target active area or a target transistor; The target active region includes at least one active region area determined in at least one of the active regions based on the polysilicon structure and / or the boundary of the active region; When the target object is a target transistor, the gate port, source port, drain port and body port of the target transistor are connected through the metal interconnect structure.

9. A test structure for monitoring injection shadow effects according to claim 8, characterized in that: When the target object is a target transistor, it is set based on preset position information of the target transistor in the polysilicon structure.

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