High-voltage power supply management circuit applied to integrated circuit test carrier plate

Abstract

The utility model discloses a high-voltage power supply management circuit applied to an integrated circuit test carrier plate, which relates to the field of power supplies, and comprises a booster circuit used for completing boosting through a two-phase or more-phase time-interleaved booster circuit to obtain boosted voltage, the boosted voltage is output to the voltage doubling circuit; the voltage doubling circuit is used for doubling and rectifying the boosted voltage into high-voltage direct-current voltage to obtain doubled voltage and outputting the doubled voltage to the filter circuit; the filter circuit is used for smoothing the input double voltage; compared with the prior art, the high-voltage power supply management circuit has the beneficial effects that when analog and digital characteristic tests of a chip are carried out on an integrated circuit test platform, the power supply module usually provides a 12V or 15V power supply, and the high-voltage power supply management circuit can generate a 200-300V adjustable high-voltage direct-current power supply and is used for parameter tests of a high-voltage chip.

Description

Technical Field

[0001] The utility model relates to the field of power supplies, in particular to a high-voltage power management circuit applied to an integrated circuit test carrier board. Background Art

[0002] An IC test board is a small carrier designed to facilitate testing, programming, or connecting integrated circuits. It typically contains only a small number of wires and interfaces for connecting IC pins to other devices or test instruments.

[0003] With the increasing demand for high-voltage DC power management chips and modules, for example, low-voltage electrical appliance chips and modules require 220V DC test specifications, while piezoelectric ceramic sensors require a maximum DC bias of 200-300V to test the vibration G-value of piezoelectric ceramics under different bias conditions. However, existing integrated circuit test platforms only provide DC voltages no higher than 15V, necessitating a high-voltage DC power management circuit. Utility Model Content

[0004] The purpose of the present invention is to provide a high-voltage power management circuit for an integrated circuit test carrier, so as to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above objectives, the present invention provides the following technical solutions:

[0006] A high-voltage power management circuit for an integrated circuit test substrate, comprising:

[0007] A boost circuit, configured to boost the voltage by using a two-phase or more-phase time-interleaved boost circuit to obtain a boosted voltage, and output the boosted voltage to a voltage doubling circuit;

[0008] The voltage doubling circuit is used to double and rectify the boosted voltage into a high-voltage DC voltage, obtain the doubled voltage, and output it to the filter circuit;

[0009] The filter circuit is used to smooth the input doubled voltage and generate a stable output voltage to be output to the load and sampling circuit;

[0010] The sampling circuit is used to sample the output voltage, obtain the sampled voltage, and output it to the control circuit;

[0011] A control circuit is used to obtain the magnitude of the output voltage based on the sampled voltage and control the boost amplitude of the boost circuit;

[0012] The boost circuit is connected to the voltage doubling circuit, the voltage doubling circuit is connected to the filter circuit, the filter circuit is connected to the sampling circuit, the sampling circuit is connected to the control circuit, and the control circuit is connected to the boost circuit.

[0013] As a further solution of the present invention: the boost circuit includes an inductor L1, an inductor L2, a switch tube S1, and a switch tube S2. One end of the inductor L1 is connected to one end of the inductor L2 and the input voltage VIN, the other end of the inductor L1 is connected to the first end of the switch tube S1 and the voltage doubler circuit, the other end of the inductor L2 is connected to one end of the switch tube S2 and the voltage doubler circuit, the second end of the switch tube S1 is grounded, the second end of the switch tube S2 is grounded, the third end of the switch tube S1 is connected to the control circuit, and the third end of the switch tube S2 is connected to the control circuit.

[0014] As a further solution of the present invention: a voltage doubling circuit comprises diode D1A, diode D2A, diode D3A, diode D1B, diode D2B, diode D3B, capacitor C1A, capacitor C2A, capacitor C3A, capacitor C1B, capacitor C2B, and capacitor C3B, wherein the positive electrode of diode D1A is connected to the boost circuit, the negative electrode of diode D1A is connected to the positive electrode of diode D2A and one end of capacitor C1A, the negative electrode of diode D2A is connected to the positive electrode of diode D3A and one end of capacitor C2A, and the negative electrode of diode D3A is connected to the positive electrode of diode D3A and one end of capacitor C2A. Connect one end of capacitor C3A to the filter circuit, the other end of capacitor C1A is connected to the boost circuit, one end of capacitor C2B, and the other end of capacitor C3A, the other end of capacitor C2A is connected to one end of capacitor C1B, one end of capacitor C3B, and the boost circuit, the other end of capacitor C3B is connected to the filter circuit and the positive electrode of diode D3B, the negative electrode of diode D3B is connected to the positive electrode of diode D2B and the other end of capacitor C2B, the negative electrode of diode D2B is connected to the positive electrode of diode D1B and the other end of capacitor C1B, and the negative electrode of diode D1B is grounded.

[0015] As a further solution of the present invention: the filter circuit includes a diode D0 and a capacitor C0, the positive electrode of the diode D0 is connected to the voltage doubler circuit, the negative electrode of the diode D0 is connected to one end of the capacitor C0, and the other end of the capacitor C0 is connected to the voltage doubler circuit.

[0016] As a further solution of the present invention: the sampling circuit includes resistors R1, R2, and R3, one end of the resistor R1 is connected to the voltage signal Vop, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the voltage signal Von, the two ends of the resistor R2 are respectively connected to the two input ends of the first differential amplifier circuit, the output end of the first differential amplifier circuit and the reference voltage VREF serve as the two input ends of the second differential amplifier circuit, and the output end of the second differential amplifier circuit is connected to the control circuit.

[0017] Compared with the prior art, the present invention has the following advantages: when performing analog and digital characteristic tests on a chip on an integrated circuit test platform, the power supply module usually provides a 12V or 15V power supply. By adopting the high-voltage power management circuit, an adjustable high-voltage DC power supply of 200-300V can be generated for parameter testing of high-voltage chips;

[0018] The output DC power supply of the utility model adopts a floating ground design, that is, the reference ground of the high-voltage output and the high-voltage pin are floating, which is conducive to the isolation of power supply and signal during high-voltage chip testing and reduces the impact of peripheral test circuits on chip performance during chip testing;

[0019] The utility model adopts a modular design. The boost circuit and the voltage doubling circuit can be replaced with different cascade numbers according to different test requirements, thereby obtaining a lower or higher DC voltage range to meet the DC power supply voltage level requirements of different chips.

[0020] The utility model has a compact circuit design, a power efficiency of over 90%, and an output power of up to 100W or even higher, thus meeting the requirements of an integrated circuit test carrier board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The schematic diagram shows a high-voltage power management circuit used in an integrated circuit test substrate.

[0022] Figure 2 This is the circuit diagram of the boost circuit, voltage doubler circuit and filter circuit.

[0023] Figure 3 The switching timing diagram of the boost circuit based on time interleaving.

[0024] Figure 4 This is a state diagram of time-interleaved switching signals.

[0025] Figure 5 This is the current flow diagram of the timing switch Mode 1.

[0026] Figure 6 This is the current flow diagram of the timing switch Mode 2.

[0027] Figure 7 This is the current flow diagram of the timing switch Mode 3.

[0028] Figure 8 This is a three-stage Cockcroft-Walton voltage multiplier circuit diagram.

[0029] Figure 9 This is a voltage gain diagram of the voltage doubler circuit.

[0030] Figure 10 This is the circuit diagram of the sampling circuit.

[0031] Figure 11 Schematic diagram of the control circuit.

[0032] Figure 12 This is a schematic diagram of the output voltage of the high-voltage power management circuit.

[0033] Figure 13 This is a schematic diagram of the output power of the high-voltage power management circuit.

[0034] Figure 14 Schematic diagram of the power efficiency of the high-voltage power management circuit. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 , a high-voltage power management circuit for an integrated circuit test substrate, comprising:

[0037] A boost circuit, configured to boost the voltage by using a two-phase or more-phase time-interleaved boost circuit to obtain a boosted voltage, and output the boosted voltage to a voltage doubling circuit;

[0038] The voltage doubling circuit is used to double and rectify the boosted voltage into a high-voltage DC voltage, obtain the doubled voltage, and output it to the filter circuit;

[0039] The filter circuit is used to smooth the input doubled voltage and generate a stable output voltage to be output to the load and sampling circuit;

[0040] The sampling circuit is used to sample the output voltage, obtain the sampled voltage, and output it to the control circuit;

[0041] A control circuit is used to obtain the magnitude of the output voltage based on the sampled voltage and control the boost amplitude of the boost circuit;

[0042] The boost circuit is connected to the voltage doubling circuit, the voltage doubling circuit is connected to the filter circuit, the filter circuit is connected to the sampling circuit, the sampling circuit is connected to the control circuit, and the control circuit is connected to the boost circuit.

[0043] In this example: See Figure 2The boost circuit includes an inductor L1, an inductor L2, a switch tube S1, and a switch tube S2. One end of the inductor L1 is connected to one end of the inductor L2 and the input voltage VIN, the other end of the inductor L1 is connected to the first end of the switch tube S1 and the voltage doubler circuit, the other end of the inductor L2 is connected to one end of the switch tube S2 and the voltage doubler circuit, the second end of the switch tube S1 is grounded, the second end of the switch tube S2 is grounded, the third end of the switch tube S1 is connected to the control circuit, and the third end of the switch tube S2 is connected to the control circuit.

[0044] The boost circuit consists of two branches ( Figure 2 It is a two-phase time-interleaved boost circuit (actually not limited to two phases), which consists of inductor L1, switch tube S1 and inductor L2, switch tube S2. In order to reduce the load of energy storage components on energy storage, time interleaving is used for control. The switching timing based on time interleaving is as follows Figure 3 shown.

[0045] Time-interleaved switching sequences separate the energy storage and release times of the two inductors, implemented using two switches, S1 and S2, which function as conduction switches. The switching logic of S1 and S2 can be divided into three modes, corresponding to the three different operating states of the boost circuit.

[0046] The switching logic of time interleaving is shown in Table 1.

[0047] Table 1 Switching logic table of time-interleaved boost circuit

[0048] S1 S2 model 1 1 Mode1 0 1 Mode2 1 0 Mode3

[0049] The working status of the switches S1 and S2 is Figure 4 The state diagram shown in Figure 1 shows that there is periodicity.

[0050] The timing of switches S1 and S2 is periodic, and the duty cycle of S1 is defined as:

[0051]

[0052] Among them, t on is the duration of the high level in a single cycle, t pw Is the time of the entire cycle. When the switching signals S1 and S2 are time-interleaved, the duty ratios of S1 and S2 satisfy:

[0053] 0.5 <D<1

[0054] See also Figure 5 In Mode 1, S1 = 1, S2 = 1, both switches are turned on, and the DC input power supply Vin is used to store energy in the inductors L1 and L2. Figure 5At this time, all diodes are reverse-biased and cut off. If there is a voltage on the output capacitor Co, the capacitor Co will discharge through the load resistor Rload.

[0055] See also Figure 6 In Mode 2, S1 = 0, S2 = 1. Switch S2 is on, and inductor L2 continues to store energy. In branch L1, switch S1 is off, diodes D2a and D2b are on, and inductor L1 doubles the voltage through capacitors C1a, C2a, C3a, C1b, C2b, and C3b, boosting the voltage and discharging it to the load through diode Do.

[0056] See also Figure 7 In Mode 3, diodes D2a, D2b, and Do are reverse biased, and the inductor L1 and switch S1 branches are conducting to store energy. Switch S2 is disconnected, and the inductor L2 doubles the voltage through the voltage doubling circuit.

[0057] In this example: See Figure 2 The voltage doubler circuit includes diode D1A, diode D2A, diode D3A, diode D1B, diode D2B, diode D3B, capacitor C1A, capacitor C2A, capacitor C3A, capacitor C1B, capacitor C2B, and capacitor C3B. The positive electrode of diode D1A is connected to the boost circuit, the negative electrode of diode D1A is connected to the positive electrode of diode D2A and one end of capacitor C1A, the negative electrode of diode D2A is connected to the positive electrode of diode D3A and one end of capacitor C2A, and the negative electrode of diode D3A is connected to the positive electrode of capacitor C3A. One end of the capacitor C1A is connected to the boost circuit, one end of the capacitor C2B, and the other end of the capacitor C3A. The other end of the capacitor C2A is connected to one end of the capacitor C1B, one end of the capacitor C3B, and the boost circuit. The other end of the capacitor C3B is connected to the filter circuit and the positive electrode of the diode D3B. The negative electrode of the diode D3B is connected to the positive electrode of the diode D2B and the other end of the capacitor C2B. The negative electrode of the diode D2B is connected to the positive electrode of the diode D1B and the other end of the capacitor C1B. The negative electrode of the diode D1B is grounded.

[0058] Voltage doubler circuits such as Figure 8 As shown, a three-stage Cockcroft-Walton voltage multiplier circuit is used. The voltage gain is:

[0059]

[0060] Where N is the number of stages of the voltage multiplier circuit, D is the duty cycle of the switches S1 and S2, and M is the voltage gain. When N = 3, the relationship between the voltage gain and the duty cycle is as follows: Figure 9 Therefore, by changing the duty cycle of the switching signal, the amplitude of the output voltage can be controlled. The lower the duty cycle, the lower the output voltage, and the higher the duty cycle, the higher the output voltage.

[0061] In this example: See Figure 2 The filtering circuit includes a diode D0 and a capacitor C0. The positive electrode of the diode D0 is connected to the voltage doubler circuit, the negative electrode of the diode D0 is connected to one end of the capacitor C0, and the other end of the capacitor C0 is connected to the voltage doubler circuit.

[0062] After the doubled voltage is filtered by capacitor C0, it becomes smoother and generates a stable output voltage which is output to the subsequent circuit.

[0063] In this example: See Figure 10 The sampling circuit includes a resistor R1, a resistor R2, and a resistor R3. One end of the resistor R1 is connected to the voltage signal Vop, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the voltage signal Von. The two ends of the resistor R2 are respectively connected to the two input ends of the first differential amplifier circuit. The output end of the first differential amplifier circuit and the reference voltage VREF serve as the two input ends of the second differential amplifier circuit. The output end of the second differential amplifier circuit is connected to the control circuit.

[0064] The sampling circuit's function is to collect the circuit's output voltage and output it to the control circuit. Since Vop and Von are in a floating state, the voltage difference between the output voltages Vop and Von is sampled by dividing the voltage using resistors R1, R2, and R3. Resistors R4, R5, R6, and R7 form the first differential amplifier circuit. If R4 = R6, R5 = R7, and the effect of the negative feedback amplifier circuit on the resistor sampling branch is ignored, the output voltage of the sampling circuit is:

[0065]

[0066] Since the range of the output voltage Vop-Von is controlled to 200-300V, the voltage gain of the sampling circuit is controlled to approximately 1 / 200.

[0067] In order to accurately control the output voltage, the voltage Vfb of the voltage sampling circuit is compared with the reference voltage Vref and input into the second differential amplifier circuit. The voltage Vo is:

[0068]

[0069] The output voltage (Vop-Von) is sampled and fed back as Vfb. If the output voltage (Vop-Von) reaches the target value, the voltage Vo approaches 0, and the duty cycle of the switching signals S1 and S2 remains unchanged. If the output voltage (Vop-Von) exceeds the target value, the control circuit reduces the duty cycle of S1 and S2 based on the received voltage Vo. If the output voltage (Vop-Von) falls below the target value, the control circuit increases the duty cycle of S1 and S2.

[0070] Control circuit such as Figure 11 The main modules of the control circuit are digital IO, PID controller, digital-to-analog converter DAC and analog-to-digital converter ADC.

[0071] The digital I / O uses SPI to connect to the integrated circuit tester, acquiring power supply information and sending control commands to the power management circuit. The sampled feedback voltage Vo is sampled by the ADC and then passes through a PID control algorithm (this technique, adjusting the PWM signal duty cycle based on the magnitude of the Vo signal, is a common technique and does not involve innovative methods) to ensure that the output voltage reaches the target set value smoothly. After the control circuit receives the output voltage command, it generates the reference voltage Vref for the output circuit through the DAC.

[0072] The high-voltage power management circuit has been tested and optimized, and the output voltage range is 172V to 305V. Due to circuit losses, the overall value is slightly lower than the theoretical value, which meets the design goals, such as Figure 12 shown.

[0073] The output power of the high voltage power management circuit is 37-110W, which is slightly lower than the theoretical value and meets the power requirements of integrated circuit chip testing, such as Figure 13 shown.

[0074] The overall efficiency of the high voltage power management circuit is as follows Figure 14 When the duty cycle is between 0.55 and 0.75, the power efficiency is in the optimal efficiency range, between 91% and 93%. The optimal power efficiency is achieved when the duty cycle is around 0.65.

[0075] The working principle of the present utility model is as follows: the boost circuit is used to complete the boosting through the time-interleaved boosting circuit of two or more phases to obtain the boosted voltage, and output the boosted voltage to the voltage doubling circuit; the voltage doubling circuit is used to double and rectify the boosted voltage into a high-voltage DC voltage to obtain the doubled voltage, and output it to the filtering circuit; the filtering circuit is used to smooth the input doubled voltage to generate a stable output voltage to output to the load and the sampling circuit; the sampling circuit is used to sample the output voltage, obtain the sampled voltage, and output it to the control circuit; the control circuit is used to obtain the size of the output voltage based on the sampled voltage; and the boost amplitude of the boost circuit is controlled.

[0076] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered in all respects as exemplary and non-restrictive.

[0077] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A high-voltage power management circuit for an integrated circuit test substrate, characterized in that: The high-voltage power management circuit for an integrated circuit test carrier includes: A boost circuit, configured to boost the voltage by using a two-phase or more-phase time-interleaved boost circuit to obtain a boosted voltage, and output the boosted voltage to a voltage doubling circuit; The voltage doubling circuit is used to double and rectify the boosted voltage into a high-voltage DC voltage, obtain the doubled voltage, and output it to the filter circuit; The filter circuit is used to smooth the input doubled voltage and generate a stable output voltage to be output to the load and sampling circuit; The sampling circuit is used to sample the output voltage, obtain the sampled voltage, and output it to the control circuit; A control circuit is used to obtain the magnitude of the output voltage based on the sampled voltage and control the boost amplitude of the boost circuit; The boost circuit is connected to the voltage doubling circuit, the voltage doubling circuit is connected to the filter circuit, the filter circuit is connected to the sampling circuit, the sampling circuit is connected to the control circuit, and the control circuit is connected to the boost circuit.

2. The high-voltage power management circuit for an integrated circuit test carrier according to claim 1, characterized in that: The boost circuit includes an inductor L1, an inductor L2, a switch tube S1, and a switch tube S2. One end of the inductor L1 is connected to one end of the inductor L2 and the input voltage VIN, the other end of the inductor L1 is connected to the first end of the switch tube S1 and the voltage doubler circuit, the other end of the inductor L2 is connected to one end of the switch tube S2 and the voltage doubler circuit, the second end of the switch tube S1 is grounded, the second end of the switch tube S2 is grounded, the third end of the switch tube S1 is connected to the control circuit, and the third end of the switch tube S2 is connected to the control circuit.

3. The high-voltage power management circuit for an integrated circuit test carrier according to claim 1 or 2, characterized in that: The voltage doubler circuit includes diode D1A, diode D2A, diode D3A, diode D1B, diode D2B, diode D3B, capacitor C1A, capacitor C2A, capacitor C3A, capacitor C1B, capacitor C2B, and capacitor C3B. The positive electrode of diode D1A is connected to the boost circuit, the negative electrode of diode D1A is connected to the positive electrode of diode D2A and one end of capacitor C1A, the negative electrode of diode D2A is connected to the positive electrode of diode D3A and one end of capacitor C2A, and the negative electrode of diode D3A is connected to one end of capacitor C3A. End, the filter circuit, the other end of capacitor C1A is connected to the boost circuit, one end of capacitor C2B, and the other end of capacitor C3A, the other end of capacitor C2A is connected to one end of capacitor C1B, one end of capacitor C3B, and the boost circuit, the other end of capacitor C3B is connected to the filter circuit and the anode of diode D3B, the cathode of diode D3B is connected to the anode of diode D2B and the other end of capacitor C2B, the cathode of diode D2B is connected to the anode of diode D1B and the other end of capacitor C1B, and the cathode of diode D1B is grounded.

4. The high-voltage power management circuit for an integrated circuit test carrier according to claim 1, wherein: The filter circuit includes a diode D0 and a capacitor C0. The positive electrode of the diode D0 is connected to the voltage doubler circuit, the negative electrode of the diode D0 is connected to one end of the capacitor C0, and the other end of the capacitor C0 is connected to the voltage doubler circuit.

5. The high-voltage power management circuit for an integrated circuit test carrier according to claim 1, characterized in that: The sampling circuit includes resistors R1, R2, and R3. One end of the resistor R1 is connected to the voltage signal Vop, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the voltage signal Von. The two ends of the resistor R2 are respectively connected to the two input ends of the first differential amplifier circuit. The output end of the first differential amplifier circuit and the reference voltage VREF serve as the two input ends of the second differential amplifier circuit. The output end of the second differential amplifier circuit is connected to the control circuit.

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