Super junction MOSFET device

Abstract

The utility model discloses a super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, relates to the technical field of semiconductor power devices, and can improve the damage of ESD (Electro-Static Discharge) in the super junction MOSFET device. The super junction MOSFET device comprises a first conduction type drain electrode, a column structure located on the drain electrode, and a source electrode structure formed in the column structure, the source electrode structure comprises a source electrode region and a source electrode lead, the source electrode region comprises an oxide layer, and the oxide layer is provided with a gate structure and an ESD protection structure; the gate structure comprises a gate lead and a gate layer, and the ESD protection structure is respectively connected with the gate lead and the source lead.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor power devices, and in particular to a super junction MOSFET device. Background Art

[0002] Superjunction MOSFET, also known as super junction metal oxide semiconductor field effect transistor (SJ-MOSFET), is a rapidly developing and widely used new type of power semiconductor device. It has been widely used in power supplies or adapters for consumer electronic products such as personal computers, laptops, netbooks, mobile phones, high-pressure gas discharge lamps, LCD TVs, plasma TVs, and game consoles.

[0003] Since superjunction MOSFETs have a smaller area than vertical double-diffused metal-oxide-semiconductor (VDMOS) devices with the same voltage specifications, electrostatic discharge (ESD) causes greater damage to SJ MOSFETs. Therefore, it is necessary to reduce the damage of ESD in SJ MOSFETs. Utility Model Content

[0004] The present application provides a super junction MOSFET device, which can improve ESD damage in the super junction MOSFET device.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] An embodiment of the present application provides a super junction MOSFET device, comprising:

[0007] A drain electrode of a first conductive type, a pillar structure located on the drain electrode, and a source electrode structure formed in the pillar structure;

[0008] The source structure includes a source region and a source lead, the source region includes an oxide layer, and the oxide layer is provided with a gate structure and an ESD protection structure;

[0009] The gate structure includes a gate lead and a gate layer, and the ESD protection structure is connected to the gate lead and the source lead respectively.

[0010] As a possible implementation manner, the oxide layer includes a first polysilicon layer, and the ESD protection structure is formed in the first polysilicon layer.

[0011] As a possible implementation manner, the ESD protection structure is an ESD diode.

[0012] As a possible implementation manner, two ends of the ESD diode are respectively connected to the gate lead and the source lead through contact holes.

[0013] As a possible implementation manner, the gate layer is a second polysilicon layer.

[0014] As a possible implementation, the device further includes: a substrate having a first conductivity type, the substrate having a first surface and a second surface opposite to each other;

[0015] The drain is disposed on the second surface of the substrate.

[0016] As a possible implementation manner, the column structure is provided on the first surface of the substrate, and the column structure includes first columns having a first conductivity type and second columns having a second conductivity type, and the first columns and the second columns are arranged alternately.

[0017] As a possible implementation manner, the second pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.

[0018] As a possible implementation manner, the source lead is located on the pillar structure, and the source region is connected to the source lead through a contact hole.

[0019] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0020] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0021] The super junction MOSFET device provided in an embodiment of the present application comprises a drain of a first conductive type, a column structure located on the drain, and a source structure formed in the column structure. The source structure comprises a source region and a source lead, the source region comprises an oxide layer, and a gate structure and an ESD protection structure are provided on the oxide layer. The gate structure comprises a gate lead and a gate layer, and the ESD protection structure is connected to the gate lead and the source lead, respectively. The super junction MOSFET device provided in the present application improves the ESD damage in the super junction MOSFET device by providing an ESD protection structure on the oxide layer above the source region, and connecting the ESD protection structure to the gate lead and the source lead, respectively. Furthermore, providing an ESD protection structure above the source region can avoid the influence of the step difference of the thick oxide layer below the gate layer, and at the same time can make the withstand voltage of the ESD diode easier to adjust, making the device easier to produce and having better device consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural diagram of a super junction MOSFET device provided in an embodiment of the present application.

[0023] Reference numerals:

[0024] 1-substrate, 2-second pillar, 3-first pillar, 4-source region, 5-drain, 6-oxide layer, 7-gate layer, 8-gate lead, 9-contact hole, 10-ESD diode, 11-source lead. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0027] It will be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0028] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0029] The present application provides a super junction MOSFET device, such as Figure 1 As shown, the device includes:

[0030] A first conductive type drain 5, a pillar structure located on the drain 5, and a source structure formed in the pillar structure;

[0031] The source structure includes a source region 4 and a source lead 11. The source region 4 includes an oxide layer 6. The oxide layer 6 is provided with a gate structure and an ESD protection structure.

[0032] The gate structure includes a gate lead 8 and a gate layer 7 , and the ESD protection structure is connected to the gate lead 8 and the source lead 11 respectively.

[0033] It should be noted that Figure 1 This is a longitudinal cross-sectional view of the superjunction MOSFET device at the ESD protection structure location, where Figure 1 The source region 4 in the gate lead 8 and the ESD protection structure are all connected to the corresponding source lead 11 except for the gate lead 8. Figure 1 Not fully shown.

[0034] The super junction MOSFET device provided in the embodiment of the present application includes a first conductive type drain 5, a column structure located on the drain 5, and a source structure formed in the column structure. Wherein, the source structure includes a source region 4 and a source lead 11, the source region 4 includes an oxide layer 6, and the oxide layer 6 is provided with a gate structure and an ESD protection structure. The gate structure includes a gate lead 8 and a gate layer 7, and the ESD protection structure is connected to the gate lead 8 and the source lead 11 respectively. The super junction MOSFET device provided in the present application is provided with an ESD protection structure on the oxide layer 6 above the source region 4, and the ESD protection structure is connected to the gate lead 8 and the source lead 11 respectively, so that the ESD damage in the super junction MOSFET device can be improved. Furthermore, the ESD protection structure is provided above the source region 4, which can avoid the influence of the step difference of the thick oxide layer 6 below the gate layer 7, and at the same time, the withstand voltage of the ESD diode 10 can be made easier to adjust, so that the device is easier to produce and the device consistency is better.

[0035] Optionally, the oxide layer 6 includes a first polysilicon layer, and the ESD protection structure is formed in the first polysilicon layer.

[0036] In the actual preparation process, when etching the gate layer 7 , a piece of polysilicon, ie, a first polysilicon layer, may be reserved above the source region 4 , and an ESD protection structure is prepared in the first polysilicon layer.

[0037] Optionally, the ESD protection structure is an ESD diode 10. Specifically, N-type and P-type implants can be performed in the first polysilicon layer, and two mask layers can be added during the implantation process to form a back-to-back ESD diode 10 structure. The two ends of the ESD diode 10 are connected to the gate lead 8 and the source lead 11 respectively through contact holes 9.

[0038] Optionally, the gate layer 7 is a second polysilicon layer.

[0039] It should be noted that the first polysilicon layer and the second polysilicon layer may be located in the same plane and have the same height. The first polysilicon layer is used to form the ESD diode 10 , and the second polysilicon layer is used to form the gate.

[0040] Optionally, the device further includes: a substrate 1 having a first conductivity type, the substrate 1 having a first surface and a second surface opposite to each other; and the drain 5 is arranged on the second surface of the substrate 1 .

[0041] The substrate 1 has a first conductivity type and has a first surface and a second surface facing each other. The substrate 1 serves as a carrier for the superjunction MOSFET, primarily providing support. The substrate 1 can be made of a silicon substrate 1, a germanium substrate 1, or a germanium-silicon substrate 1. In this embodiment, the substrate 1 is preferably made of a silicon substrate 1, as silicon is the most common, inexpensive, and stable semiconductor material.

[0042] Optionally, the column structure is provided on the first surface of the substrate 1 , and the column structure includes first columns 3 having a first conductivity type and second columns 2 having a second conductivity type, and the first columns 3 and the second columns 2 are arranged alternately.

[0043] The material of the first column 3 can be silicon, and the material of the second column 2 can be SiC. The height of the first column 3 and the second column 2 is the same. Optionally, the doping concentration of the first column 3 and the second column 2 can be 1×10 14 ~8× 10 15 cm -3 In addition, the minority carrier lifetime of the pillar of the superjunction MOSFET may be 0.1 μs to 100 μs, for example, 0.1 μs, 0.5 μs, 1 μs, 5 μs, 10 μs, 20 μs, 30 μs, 40 μs, 50 μs, 60 μs, 70 μs, 80 μs, 90 μs, or 100 μs.

[0044] Minority carriers are the opposite of majority carriers. Semiconductors contain two types of carriers: electrons and holes. When a particular carrier is in the minority and plays a minor role in electrical conduction, it is called a minority carrier. For example, in an N-type semiconductor, holes are the minority carriers, while electrons are the majority carriers. In a P-type semiconductor, holes are the majority carriers, while electrons are the minority carriers.

[0045] The electrodes of the super junction MOSFET device include: a drain 5 , which is arranged on the second surface of the substrate 1 ; and a gate, which is arranged on the first pillar 3 and the second pillar 2 .

[0046] Optionally, the second pillar 2 includes a heavily doped region of the first conductivity type, and the source region 4 is formed in the heavily doped region. The source lead 11 or source metal is located on the pillar structure, and the source region 4 is connected to the source lead 11 through a contact hole 9. The gate lead 8 is connected to the gate lead 8 through the contact hole 9.

[0047] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0049] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and to form distinct embodiments. For example, in the claims above, any of the claimed embodiments may be used in any combination. The information disclosed in this background section is intended solely to enhance understanding of the overall background of this application and should not be construed as an admission or any implication that such information constitutes prior art known to those skilled in the art.

Claims

1. A super junction MOSFET device, characterized in that: The device comprises: A drain electrode of a first conductive type, a pillar structure located on the drain electrode, and a source electrode structure formed in the pillar structure; The source structure includes a source region and a source lead, the source region includes an oxide layer, and the oxide layer is provided with a gate structure and an ESD protection structure; The gate structure includes a gate lead and a gate layer, and the ESD protection structure is connected to the gate lead and the source lead respectively.

2. The device according to claim 1, characterized in that The oxide layer includes a first polysilicon layer, and the ESD protection structure is formed in the first polysilicon layer.

3. The device according to claim 2, characterized in that The ESD protection structure is an ESD diode.

4. The device according to claim 3, characterized in that Two ends of the ESD diode are respectively connected to the gate lead and the source lead through contact holes.

5. The device according to claim 1, wherein The gate layer is a second polysilicon layer.

6. The device according to claim 1, characterized in that The device further includes: a substrate having a first conductivity type, the substrate having a first surface and a second surface opposite to each other; The drain is disposed on the second surface of the substrate.

7. The device according to claim 6, characterized in that The column structure is disposed on the first surface of the substrate. The column structure includes first columns having a first conductivity type and second columns having a second conductivity type. The first columns and the second columns are alternately arranged.

8. The device according to claim 7, characterized in that The second pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.

9. The device according to claim 1, characterized in that The source lead is located on the pillar structure, and the source region is connected to the source lead through a contact hole.

10. The device according to claim 7, characterized in that The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

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