Super junction MOSEFT device

Abstract

The utility model relates to a super junction MOSEFT device, comprising a first conductive type substrate; the first conductive type epitaxial layer is arranged on the front surface of the first conductive type substrate; the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and is positioned in the first conductive type epitaxial layer; the second conductive type columns extend into the first conductive type epitaxial layer from the front surface of the first conductive type epitaxial layer; the trench gate structure is arranged between two adjacent second conductive type columns and extends from the front surface to the back surface of the first conductive type epitaxial layer; the first conduction type source region is arranged on the front face of the second conduction type body region and located in the second conduction type body region, the trench gate structure comprises a first trench formed in the front face of the first conduction type epitaxial layer, at least two gates are arranged in the first trench, and a shielding gate is arranged between the two gates; according to the utility model, the on-resistance is further reduced, so that the on-resistance of the whole structure is small, and the through-current capability is strong.

Description

Technical Field

[0001] The utility model relates to the technical field of microelectronics, in particular to a super junction MOSFET device. Background Art

[0002] MOS is one of the basic components in integrated circuit technology. Its main advantages include high integration, fast switching speed, low power consumption, good electrical isolation and stability, which make it widely used in various applications such as digital circuits, analog circuits, microprocessors, memories and power amplifiers. The key innovation of planar MOS lies in the application of metal, oxide and semiconductor structures to transistor design. By forming a layer of oxide (usually silicon dioxide) on the semiconductor surface and using metal as the gate above it, the gate voltage is used to control the resistance of the conductive channel on the semiconductor surface between the source and drain to control the conductivity of the channel, thereby realizing the switching and amplification functions of the device.

[0003] In modern electronic devices, especially in high-frequency and high-power applications, reducing on-resistance is one of the key factors in improving device performance and power efficiency. Trench gate structure is a commonly used technology. By etching trenches on the semiconductor substrate and forming a gate in the trench, the contact area is increased, and the gate's ability to control the channel current is improved. This not only enables the device to achieve a larger current under the same gate drive voltage, but also greatly reduces the on-resistance. Shielded gate MOS introduces a shielded gate electrode on the basis of traditional trench gate MOS. The introduced shielded gate realizes lateral auxiliary depletion, thereby utilizing lower resistance epitaxy to meet high withstand voltage requirements and reduce on-resistance.

[0004] Although the traditional trench gate structure can reduce the on-resistance to a certain extent, with the continuous advancement of technology, the requirements for on-resistance are becoming increasingly higher. In application scenarios with higher performance requirements, such as high-frequency and high-power devices, the on-resistance of the traditional trench gate structure has not yet reached the ideal level, limiting the performance of the device under extreme conditions. Therefore, there is an urgent need to make further improvements based on the existing trench gate structure to further reduce the on-resistance. Utility Model Content

[0005] In view of this, the purpose of the present invention is to provide a super junction MOSFET device to solve the technical problem in the prior art that the on-resistance of the traditional trench gate structure has not reached an ideal level.

[0006] The utility model provides a super junction MOSFET device, comprising:

[0007] a first conductive type substrate;

[0008] A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate;

[0009] A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer;

[0010] At least two second conductive type columns are provided, extending from the front side to the back side of the first conductive type epitaxial layer;

[0011] a trench gate structure, disposed between two adjacent second-conductivity-type pillars and extending from the front surface to the back surface of the first-conductivity-type epitaxial layer;

[0012] A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region;

[0013] In which, the trench gate structure includes a first trench opened on the front side of the first conductive type epitaxial layer, at least two gates are arranged in the first trench, a shielding gate is arranged between the two gates, and a gate oxide layer is arranged between the shielding gate and the gate, between the gate and the inner wall of the first trench, and between the shielding gate and the bottom wall of the first trench.

[0014] Optionally, a second conductive type shielding region is provided on a side of the first trench facing the first conductive type substrate, and the second conductive type shielding region covers a bottom of the first trench.

[0015] Optionally, the second conductive type ion concentration in the second conductive type shielding region is greater than the second conductive type ion concentration in the second conductive type body region and the second conductive type pillar.

[0016] Optionally, an insulating dielectric layer is provided on the front side of the second conductive type body region, and a plurality of metal contact holes are opened in the insulating dielectric layer. A part of the metal contact holes are provided corresponding to the second conductive type columns and penetrate into the second conductive type columns to be connected with the second conductive type columns and the first conductive type source region, and another part of the metal contact holes are provided corresponding to the shielding grid and are connected with the shielding grid.

[0017] Optionally, it also includes:

[0018] a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled;

[0019] The back metal layer is arranged on the back side of the first conductive type substrate.

[0020] Optionally, the first conductivity type ion concentration in the first conductivity type substrate is greater than the first conductivity type ion concentration in the first conductivity type epitaxial layer.

[0021] Optionally, a plurality of the second conductive type pillars are arranged in parallel, and the depth of the second conductive type pillars is set to 30 μm-60 μm.

[0022] Optionally, the depth of the first groove is set to 1.5 μm-3 μm.

[0023] Optionally, a depth of the shielding gate in the first trench is greater than a depth of the gate in the first trench.

[0024] Optionally, the superjunction MOSFET device includes an N-type superjunction MOSFET device and a P-type superjunction MOSFET device. For the N-type superjunction MOSFET device, the first conductivity type is N-type and the second conductivity type is P-type. For the P-type superjunction MOSFET device, the first conductivity type is P-type and the second conductivity type is N-type.

[0025] The technical solution of the utility model has the following advantages:

[0026] The superjunction MOSFET device provided by the present invention is provided with a second conductive type column. Based on the charge balancing technology, under the same withstand voltage, the thickness of the first conductive type epitaxial layer is reduced, thereby reducing the on-resistance. The shielding grid is used to assist in depleting the first conductive type epitaxial layer, thereby reducing the on-resistance and conduction loss. On this basis, the trench gate structure provided between two adjacent second conductive type columns includes two or more gates, which can increase the conductive current path when the superjunction MOSFET device is turned on, further reducing the on-resistance, so that the on-resistance of the entire structure is small and the current flow capacity is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 It is a cross-sectional view of forming a first conductivity type epitaxial layer in the present invention;

[0029] Figure 2 A cross-sectional view showing the formation of a second conductive type body region in the present invention;

[0030] Figure 3It is a cross-sectional view of forming the first groove and the second groove in the utility model;

[0031] Figure 4 It is a cross-sectional view of forming the second conductive type shielding layer in the present invention;

[0032] Figure 5 A cross-sectional view of a second conductive type column and a trench gate structure formed in the present invention;

[0033] Figure 6 A cross-sectional view of a first conductive type source region formed in the present invention;

[0034] Figure 7 It is a cross-sectional view of forming an insulating dielectric layer in the present invention;

[0035] Figure 8 It is a cross-sectional view of forming the front metal layer and the back metal layer in the present invention;

[0036] Figure 9 This is a step diagram of the method for preparing a superjunction MOSFET device in the present invention.

[0037] Description of reference numerals:

[0038] 1. First conductive type substrate; 2. First conductive type epitaxial layer; 3. Second conductive type body region; 4. First conductive type source region; 5. Second conductive type column; 6. Trench gate structure; 61. Gate; 62. Shielding gate; 63. First trench; 64. Gate oxide layer; 7. Second trench; 8. Insulating dielectric layer; 9. Metal contact via; 10. Front metal layer; 11. Back metal layer; 12. Second conductive type shielding region. DETAILED DESCRIPTION

[0039] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the description of the present invention, all other embodiments derived by persons of ordinary skill in the art without inventive effort are also within the scope of protection of the present invention.

[0040] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0041] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on the utility model.

[0042] The terms "first," "second," "third," etc. are merely used to distinguish between elements of similar nature and do not indicate or imply relative importance or a particular order.

[0043] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0044] Example

[0045] Superjunction MOSFET devices include N-type superjunction MOSFET devices and P-type superjunction MOSFET devices. For N-type superjunction MOSFET devices, the first conductivity type is N-type and the second conductivity type is P-type; for P-type superjunction MOSFET devices, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, N-type superjunction MOSFET devices are taken as an example.

[0046] Reference Figures 1-8As shown, the utility model provides a super junction MOSFET device, including a first conductive type substrate 1, a first conductive type epitaxial layer 2, a second conductive type body region 3, a second conductive type column 5, a trench gate structure 6 and a first conductive type source region 4. In this embodiment, the top surface is set as the front surface and the bottom surface is set as the back surface, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, the first conductive type epitaxial layer 2 is set on the front surface of the first conductive type substrate 1, and the first conductive type epitaxial layer 2 is grown by an epitaxial process. The first conductive type ion concentration in the first conductive type substrate 1 is greater than the first conductive type ion concentration in the first conductive type epitaxial layer 2; the second conductive type body region 3 is set on the front surface of the first conductive type epitaxial layer 2 and is located in the first conductive type epitaxial layer 2, and at least two second conductive type columns 5 are provided, and the second conductive type columns 5 extend from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the first conductive type epitaxial layer 2. The conductive type epitaxial layer 2 extends from the back side thereof until it extends from the second conductive type body region 3 into the first conductive type epitaxial layer 2; at least one trench gate structure 6 is correspondingly provided, and a trench gate structure 6 is provided between two adjacent second conductive type pillars 5. The trench gate structure 6 also extends from the front side thereof having the second conductive type body region 3 to the back side of the first conductive type epitaxial layer 2 until it extends from the second conductive type body region 3 into the first conductive type epitaxial layer 2. The first conductive type source region 4 is provided on the front side thereof and is located within the second conductive type body region 3. In this embodiment, a plurality of first conductive type source regions 4 are provided. There are two corresponding first conductive type source regions 4 at the trench gate structure 6, which are respectively located on both sides of the trench gate structure 6 facing the second conductive type pillar 5, and extend toward the second conductive type pillar 5 until they penetrate into the second conductive type pillar 5 or contact the second conductive type pillar 5.

[0047] The trench gate structure 6 includes a first trench 63 formed on the front surface of the first conductive type epitaxial layer 2. The first trench 63 extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until it extends from the second conductive type body region 3 into the first conductive type epitaxial layer 2. Two gates 61 are provided in the first trench 63, and a shielding gate 62 is provided between the two gates 61. Both the gate 61 and the shielding gate 62 extend from the notch of the first trench 63 to the interior of the first trench 63. Gaps are left between the gate 61 and the inner wall of the first trench 63 and the shielding gate 62. A gate oxide layer 64 is provided between the shielding gate 62 and the gate 61, between the gate 61 and the inner wall of the first trench 63, and between the shielding gate 62 and the bottom wall of the first trench 63, and the gate oxide layer 64 is used to separate the gates. In other embodiments, the number of gates 61 is not limited to a single number and can also be set to multiple.

[0048] By setting up a second conductive type column 5, based on the charge balance technology, under the same withstand voltage, the thickness of the first conductive type epitaxial layer 2 is reduced, thereby reducing the on-resistance, and by adopting the shielding gate 62, the first conductive type epitaxial layer 2 can be assisted in being depleted to reduce the on-resistance and reduce the conduction loss. On this basis, the trench gate structure 6 set between two adjacent second conductive type columns 5 includes two or more gates 61, which can increase the conductive current path when the super junction MOSFET device is turned on, further reducing the on-resistance, so that the on-resistance of the entire structure is small and the current flow capacity is strong.

[0049] As a specific embodiment, multiple second conductive type columns 5 are arranged in parallel, and a trench gate structure 6 is set between each adjacent second conductive type column 5, and the second conductive type column 5 and the trench gate structure 6 are separated by a portion of the first conductive type epitaxial layer 2. The depth of the second conductive type column 5 is set to 30μm-60μm, the depth of the first trench 63 is set to 1.5μm-3μm, and the depth of the shielding gate 62 in the first trench 63 is greater than the depth of the gate 61 in the first trench 63.

[0050] As a specific embodiment, it also includes an insulating dielectric layer 8, a front metal layer 10 and a back metal layer 11, wherein the insulating dielectric layer 8 is arranged on the front of the second conductive type body region 3 and covers the entire second conductive type body region 3, and a plurality of metal contact holes 9 are opened in the insulating dielectric layer 8, a part of the metal contact holes 9 is arranged corresponding to the second conductive type column 5 and penetrates into the second conductive type column 5 and is connected to the second conductive type column 5 and the first conductive type source region 4, and another part of the metal contact holes 9 is arranged corresponding to the shielding grid 62 and is connected to the shielding grid 62; the front metal layer 1 0 is arranged on the front side of the insulating dielectric layer 8, and the front metal layer 10 is located at the metal contact through-hole 9 and partially extends into the metal contact through-hole 9 until the metal contact through-hole 9 is filled. At this time, the part of the front metal layer 10 in the metal contact through-hole 9 corresponding to the second conductive type column 5 will contact the second conductive type column 5 and the first conductive type source region 4, and the part of the front metal layer 10 in the metal contact through-hole 9 corresponding to the shielding gate 62 will contact the shielding gate 62; the back metal layer 11 is arranged on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0051] As another embodiment, a second conductive type shielding region 12 is provided on the side of the first trench 63 facing the first conductive type substrate 1, and the second conductive type shielding region 12 is located in the first conductive type epitaxial layer 2 outside the lower end of the first trench 63, and the second conductive type shielding region 12 covers the bottom of the first trench 63; the second conductive type ion concentration in the second conductive type shielding region 12 is greater than the second conductive type ion concentration in the second conductive type body region 3 and the second conductive type column 5, so that the electric field at the bottom of the shielding gate 62 in the trench gate structure 6 is closer to a rectangle, thereby basically eliminating the neck resistance RJEFT and reducing the resistance RN- of the first conductive type epitaxial layer 2.

[0052] The method for preparing the superjunction MOSFET device includes the following steps:

[0053] like Figure 1 As shown, S1, a first conductive type substrate 1 is selected, and a first conductive type epitaxial layer 2 is grown on the front surface of the first conductive type substrate 1, wherein the first conductive type substrate 1 selects N-type silicon as a substrate, and the first conductive type epitaxial layer 2 is grown using an epitaxial process.

[0054] like Figure 2 As shown, S2, a general injection is performed directly on the front surface of the first conductive type epitaxial layer 2, the second conductive type ions are injected, and the injection is carried out at high temperature, thereby forming a second conductive type body region 3 on the front surface of the first conductive type epitaxial layer 2, and the second conductive type body region 3 covers the entire front surface of the first conductive type epitaxial layer 2.

[0055] As shown in Figure 3, S3, through photolithography blocking, a first trench 63 and a second trench 7 are etched in a partial area of ​​the front surface of the first conductive type epitaxial layer 2. The first trench 63 and the second trench 7 are staggered, and the first trench 63 and the second trench 7 are both extended from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until extending from the second conductive type body region 3 to the first conductive type epitaxial layer 2. The depth of the first trench 63 is set to 1.5μm-3μm, and the depth of the second trench 7 is set to 30μm-60μm.

[0056] like Figure 5As shown, S4, a second conductive type column 5 is formed in the second trench 7, a gate oxide layer 64 is deposited in the first trench 63, and selective etching is performed to etch three side-by-side grooves on the front of the first trench 63, wherein the depth of the middle groove is greater than the depth of the two grooves on both sides, conductive polysilicon is deposited in the grooves on both sides to form a gate 61, and conductive polysilicon is deposited in the middle trench to form a shielding gate 62. Compared with the commonly used thermal growth to form the gate oxide layer 64, the gate oxide layer 64 is prepared by deposition in this embodiment, so that the thickness of the gate oxide layer 64 can be more accurately controlled without being limited by the growth rate and event. At the same time, the deposition technology can be carried out on different substrates and manufacturing conditions, so that it can be suitable for large-scale production, and can be prepared more quickly, thereby improving production efficiency.

[0057] like Figure 6 As shown, S5, through photolithography blocking, first conductive type ions are injected into a partial area on the front side of the second conductive type body region 3, and high temperature is used to advance, thereby forming a first conductive type source region 4 in the second conductive type body region 3. Specifically, through the blocking of the photolithography plate, two unblocked areas are formed in the second conductive type body region 3 on both sides of the trench gate structure 6 facing the second conductive type column 5, and the first conductive type ions are injected into the unblocked areas. At this time, two undiffused first conductive type source regions 4 are formed in the second conductive type body region 3, and then high temperature is used to advance to diffuse and form the first conductive type source region 4. The first conductive type source region 4 is provided on both sides of the trench gate structure 6, and the first conductive type source region 4 will diffuse toward the second conductive type column 5 until it contacts the second conductive type column 5 or extends into the second conductive type column 5.

[0058] like Figure 7 As shown, S6, an insulating dielectric layer 8 is deposited on the surface of one side of the first conductive type epitaxial layer 2 having the second conductive type body region 3, so that the insulating dielectric layer 8 covers the entire front surface of the first conductive type epitaxial layer 2, and then the insulating dielectric layer 8 is etched to etch a plurality of through holes on the insulating dielectric layer 8 to form metal contact holes 9, wherein a portion of the metal contact holes 9 is located directly above the second conductive type column 5, and during etching, an additional 0.3 mm to 0.4 mm is etched into the second conductive type column 5 to ensure that the insulating dielectric layer 8 can be completely removed, so that the metal contact point is exposed, thereby ensuring the stability and reliability of the electrical connection, and another portion of the metal contact holes 9 is located directly above the shielding grid 62.

[0059] like Figure 8 As shown, S7, metal is deposited on the front surface of the insulating dielectric layer 85 and filled with metal contact through-holes 9 to form a front metal layer 10, and metal is deposited on the back surface of the first conductive type substrate 1 to form a back metal layer 11.

[0060] By setting up a second conductive type column 5, based on the charge balance technology, under the same withstand voltage, the thickness of the first conductive type epitaxial layer 2 is reduced, thereby reducing the on-resistance, and by adopting the shielding gate 62, the first conductive type epitaxial layer 2 can be assisted in being depleted to reduce the on-resistance and reduce the conduction loss. On this basis, the trench gate structure 6 set between two adjacent second conductive type columns 5 includes two or more gates 61, which can increase the conductive current path when the super junction MOSFET device is turned on, further reducing the on-resistance, so that the conductive resistance of the entire structure is small and the current flow capacity is strong.

[0061] As another embodiment, Figure 4 As shown, after etching the first trench 63 and the second trench 7 in a partial area on the front surface of the first conductive type epitaxial layer 2, a high concentration of second conductive type ions are injected into the bottom of the first trench 63 and pushed at high temperature to form a second conductive type shielding area 12.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0063] The above is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

Claims

1. A superjunction MOSFET device, characterized in that: include: a first conductive type substrate; A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate; A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer; At least two second conductive type columns are provided, extending from the front side to the back side of the first conductive type epitaxial layer; a trench gate structure, disposed between two adjacent second-conductivity-type pillars and extending from the front surface to the back surface of the first-conductivity-type epitaxial layer; A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region; In which, the trench gate structure includes a first trench opened on the front side of the first conductive type epitaxial layer, at least two gates are arranged in the first trench, a shielding gate is arranged between the two gates, and a gate oxide layer is arranged between the shielding gate and the gate, between the gate and the inner wall of the first trench, and between the shielding gate and the bottom wall of the first trench.

2. The superjunction MOSFET device according to claim 1, wherein: A second conductive type shielding region is provided on a side of the first trench facing the first conductive type substrate, and the second conductive type shielding region covers the bottom of the first trench.

3. The superjunction MOSFET device according to claim 2, wherein: The second conductive type ion concentration in the second conductive type shielding region is greater than the second conductive type ion concentration in the second conductive type body region and the second conductive type pillar.

4. The superjunction MOSFET device according to claim 1, wherein: An insulating dielectric layer is provided on the front side of the second conductive type body region, and a plurality of metal contact holes are opened in the insulating dielectric layer. A part of the metal contact holes are provided corresponding to the second conductive type columns and penetrate into the second conductive type columns and are connected with the second conductive type columns and the first conductive type source region. Another part of the metal contact holes are provided corresponding to the shielding grid and are connected with the shielding grid.

5. The superjunction MOSFET device according to claim 4, wherein: Also includes: a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

6. The superjunction MOSFET device according to claim 1, wherein: The first conductivity type ion concentration in the first conductivity type substrate is greater than the first conductivity type ion concentration in the first conductivity type epitaxial layer.

7. The superjunction MOSFET device according to claim 1, wherein: A plurality of the second conductive type columns are arranged in parallel, and the depth of the second conductive type columns is set to 30 μm-60 μm.

8. The superjunction MOSFET device according to claim 1, wherein: The depth of the first groove is set to 1.5 μm-3 μm.

9. The superjunction MOSFET device according to claim 1, wherein: The depth of the shield gate in the first trench is greater than the depth of the gate in the first trench.

10. The superjunction MOSFET device according to claim 1, wherein: The superjunction MOSFET device includes an N-type superjunction MOSFET device and a P-type superjunction MOSFET device. For the N-type superjunction MOSFET device, the first conductivity type is N-type and the second conductivity type is P-type. For the P-type superjunction MOSFET device, the first conductivity type is P-type and the second conductivity type is N-type.

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