Solar cell epitaxial wafer and solar cell
By introducing a GaInP transition layer between the GaInAs emission layer and the AlInP window layer, the problem of AlInAsP defect formation is solved, and the photogenerated carrier collection efficiency and conversion efficiency of the solar cell are improved.
Patent Information
- Application Number
- CN202422586753.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-25
AI Technical Summary
In the prior art, when growing the window layer of the GaInAs sub-cell, AlInAsP defects are easily formed, which leads to the recombination of photogenerated carriers and affects the conversion efficiency of the solar cell.
An N-type GaInP transition layer is introduced between the GaInAs emitter layer and the AlInP window layer to avoid direct contact between Al atoms, As atoms and P atoms, thereby preventing the formation of AlInAsP defects.
It improves the collection efficiency of photogenerated carriers, enhances the open circuit voltage and short circuit current density of solar cells, and improves conversion efficiency.
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Figure CN223415208U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell epitaxial wafer and a solar cell comprising the epitaxial wafer. Background Art
[0002] Compared to traditional Si and GaAs single-junction solar cells, GaInP / GaInAs / Ge triple-junction solar cells offer advantages such as structural stability, high reliability, long lifespan, compact size and lightweight design, high photoelectric conversion efficiency, and high light absorption coefficient. They have become a core component in space power systems and are widely used in spacecraft power systems. Therefore, to meet the enormous demand for commercial aerospace, further improving the performance of triple-junction solar cells for space applications has become a key research topic for those skilled in the art. Utility Model Content
[0003] In view of this, the present application provides a solar cell epitaxial wafer and a solar cell, the scheme is as follows:
[0004] A solar cell epitaxial wafer, comprising:
[0005] substrate;
[0006] a first sub-cell, the first sub-cell being located on one side of the substrate, the first sub-cell comprising a first emission layer, a transition layer, and a first window layer stacked in sequence, the transition layer being located between the first emission layer and the first window layer;
[0007] The first emission layer is an N-type GaInAs layer, the transition layer is an N-type GaInP layer, and the first window layer is an N-type AlInP layer.
[0008] Optionally, the transition layer thickness ranges from 5 nm to 10 nm, including endpoint values.
[0009] Optionally, the first sub-cell further includes a first back field layer and a first base layer stacked in sequence, the first back field layer is located between the substrate and the first base layer, and the first emitter layer is located on a side of the first base layer away from the first back field layer;
[0010] The first back field layer is a P-type AlGaAs layer, and the first base layer is a Zn-doped P-type GaInAs layer.
[0011] Optionally, the device further comprises: a second sub-cell, the second sub-cell being located between the substrate and the first sub-cell, the second sub-cell comprising a second emission layer and a nucleation layer stacked in sequence, the second emission layer being located between the substrate and the nucleation layer, and the first back field layer being located on a side of the nucleation layer facing away from the second emission layer;
[0012] The second emission layer is an emission layer formed by diffusing phosphine in the substrate, and the nucleation layer is an N-type GaInP layer.
[0013] Optionally, the device further comprises: a third sub-cell, the third sub-cell being located on a side of the first sub-cell facing away from the second sub-cell, the third sub-cell comprising a second back field layer, a second base layer, a third emitter layer, and a second window layer stacked in sequence, the second back field layer being located on a side of the first window layer facing away from the transition layer;
[0014] The second back field layer is a P-type AlGaInP layer, the second base layer is a Zn-doped P-type GaInP layer, the third emitter layer is an N-type GaInP layer, and the second window layer is an N-type AlInP layer.
[0015] Optionally, it also includes:
[0016] a first tunneling junction layer, wherein the first tunneling junction layer is located between the nucleation layer and the first back surface field layer;
[0017] a second tunneling junction layer, wherein the second tunneling junction layer is located between the first window layer and the second back surface field layer;
[0018] The first tunnel junction layer includes Si-doped GaAs and C-doped GaAs, and the second tunnel junction layer includes Si-doped GaAs and C-doped GaAs.
[0019] Optionally, it also includes:
[0020] An ohmic contact layer is located on a side of the second window layer away from the third emission layer, and the ohmic contact layer is an N-type GaAs layer.
[0021] Optionally, the substrate has an electrical conductivity of 2-8x10 18 cm -3 P-type Ge substrate.
[0022] A solar cell comprises the solar cell epitaxial wafer described in any one of the above embodiments.
[0023] Compared with the prior art, the technical solution of this application has the following beneficial effects:
[0024] The solar cell epitaxial wafer includes: a substrate and a first sub-cell located on one side of the substrate. The first sub-cell includes a first emitter layer, a transition layer, and a first window layer stacked in sequence. The first emitter layer is an N-type GaInAs layer, the transition layer is an N-type GaInP layer, and the first window layer is an N-type AlInP layer. It can be seen that the solar cell epitaxial wafer provided in this application first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer, and then grows an N-type AlInP window layer. Compared with related technologies, since the solar cell epitaxial wafer first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer and then grows an N-type AlInP window layer, direct contact between the N-type AlInP window layer and the N-type GaInAs emitter layer is avoided, and the Al atoms in the N-type AlInP window layer are avoided from combining with the As atoms and P atoms in the N-type GaInAs emitter layer at the same time, the formation of AlInAsP defects can be effectively avoided, which helps to improve the collection efficiency of photogenerated carriers of the solar cell, thereby improving the open-circuit voltage and short-circuit current density of the solar cell, and can effectively improve the conversion efficiency of the solar cell with the epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.
[0026] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in this application without affecting the effects and objectives that can be achieved by this application.
[0027] Figure 1 This is a schematic structural diagram of a solar cell epitaxial wafer provided in this application. DETAILED DESCRIPTION
[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0029] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0030] As mentioned in the background technology section, in response to the huge demand for commercial aerospace, how to further improve the performance of triple-junction solar cells for space use has become an important research topic for those skilled in the art.
[0031] When MOCVD is used to grow the aforementioned triple-junction solar cells, the MOCVD growth of the window layer on the emitter layer of the GaInAs subcell is particularly susceptible to the formation of point-like AlInAsP defects due to the strong bonding energy of Al atoms. When numerous defects exist between the emitter and window layer of the GaInAs subcell, photogenerated carriers recombine with the defects, preventing them from being collected. This affects the solar cell's conversion efficiency, leading to a decrease in solar cell performance and hindering the widespread application of these triple-junction solar cells.
[0032] Based on the above, the present application provides a solar cell epitaxial wafer, such as Figure 1 As shown, Figure 1 This is a schematic structural diagram of a solar cell epitaxial wafer provided in this application, which includes:
[0033] substrate 100 .
[0034] The first sub-cell 200 is located on one side of the substrate 100 and includes a first emission layer 201, a transition layer 202, and a first window layer 203, which are stacked in sequence in a direction away from the substrate 100. Specifically, the transition layer 202 is located between the first emission layer 201 and the first window layer 203, that is, the first emission layer 201 is located on one side of the substrate 100, the transition layer 202 is located on the side of the first emission layer 201 facing away from the substrate 100, and the first window layer 203 is located on the side of the transition layer 202 facing away from the first emission layer.
[0035] The first emission layer 201 is an N-type GaInAs layer, the transition layer 202 is an N-type GaInP layer, and the first window layer 203 is an N-type AlInP layer.
[0036] As can be seen from the above, the first sub-cell 200 is a GaInAs sub-cell, and a transition layer 202 is present between the first emitter layer 201 and the first window layer 203 of the first sub-cell 200. Specifically, an N-type GaInP transition layer is present between the N-type GaInAs emitter layer and the N-type AlInP window layer of the first sub-cell. In other words, the solar cell epitaxial wafer provided in this application first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer, and then grows an N-type AlInP window layer. Compared with related technologies, since the solar cell epitaxial wafer first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer and then grows an N-type AlInP window layer, direct contact between the N-type AlInP window layer and the N-type GaInAs emitter layer is avoided, and the Al atoms in the N-type AlInP window layer are avoided from combining with the As atoms and P atoms in the N-type GaInAs emitter layer at the same time, the formation of AlInAsP defects can be effectively avoided, which helps to improve the collection efficiency of photogenerated carriers of the solar cell, thereby improving the open-circuit voltage and short-circuit current density of the solar cell, and can effectively improve the conversion efficiency of the solar cell with the epitaxial wafer.
[0037] Based on the aforementioned embodiment, in one embodiment of the present application, the thickness of the transition layer 202 may be in the range of 5 nm to 10 nm, inclusive. However, the present application is not limited thereto. In other embodiments of the present application, the thickness of the transition layer 202 may be in other values or ranges, depending on the specific circumstances.
[0038] Based on the foregoing embodiments, in one embodiment of the present application, the first sub-cell 200 further includes a first back field layer 204 and a first base layer 205 stacked in sequence, wherein the first back field layer 204 is located between the substrate 100 and the first base layer 205 , and the first emission layer 201 is located on the side of the first base layer 205 away from the first back field layer 204 . Specifically, the first sub-cell 200 includes a first back field layer 204 located on one side of the substrate 100, a first base layer 205 located on the side of the first back field layer 204 away from the substrate 100, a first emission layer 201 located on the side of the first base layer 205 away from the first back field layer 204, a transition layer 202 located on the side of the first emission layer 201 away from the first base layer 205, and a first window layer 203 located on the side of the transition layer 202 away from the first emission layer 201, that is, the first sub-cell 200 includes the first back field layer 204, the first base layer 205, the first emission layer 201, the transition layer 202 and the first window layer 203 arranged in sequence in a direction away from the substrate 100 to complete the arrangement of the first sub-cell 200.
[0039] Based on the above embodiments, in one embodiment of the present application, Figure 1As shown, the solar cell epitaxial wafer further includes: a second sub-cell 300, the second sub-cell 300 being located between the substrate 100 and the first sub-cell 200, the second sub-cell 300 including a second emission layer 301 and a nucleation layer 302 stacked in sequence, the second emission layer 301 being located between the substrate 100 and the nucleation layer 302, and the first back field layer 204 being located on the side of the nucleation layer 302 facing away from the second emission layer. Specifically, the second sub-cell 300 includes the second emission layer 301 located on one side of the substrate 100, the nucleation layer 302 located on the side of the second emission layer 301 facing away from the substrate 100, and the first back field layer 204 of the first sub-cell 200 being located on the side of the nucleation layer 302 facing away from the second emission layer 301, that is, the second sub-cell 300 includes the first back field layer 204 and the nucleation layer 302 stacked in sequence in a direction facing away from the substrate 100 to form the second sub-cell 300.
[0040] Moreover, in this embodiment, the second emission layer 301, i.e., the emission layer of the second sub-cell 300, is an emission layer formed by diffusion of phosphine in the substrate 100, and the nucleation layer 302, i.e., the nucleation layer of the second sub-cell 300, is an N-type GaInP layer, that is, the second sub-cell 300 is a Ge sub-cell.
[0041] Based on the above embodiments, in one embodiment of the present application, Figure 1 As shown, the solar cell epitaxial wafer further includes a third sub-cell 400, which is located on the side of the first sub-cell 200 facing away from the second sub-cell 300. The third sub-cell 400 includes a second back field layer 401, a second base layer 402, a third emitter layer 403, and a second window layer 404 stacked in sequence. The second back field layer 401 is located on the side of the first window layer 203 facing away from the transition layer 202. Specifically, the third sub-cell 400 includes a second back field layer 401 located on the side of the first window layer 203 away from the transition layer 202, a second base layer 402 located on the side of the second back field layer 401 away from the first window layer 203, a third emission layer 403 located on the side of the second base layer 402 away from the second back field layer 401, and a second window layer 404 located on the side of the third emission layer 403 away from the second base layer 402, that is, the third sub-cell 400 includes the second back field layer 401, the second base layer 402, the third emission layer 403 and the second window layer 404 which are stacked in sequence along the direction away from the first window layer 203 to form the third sub-cell 400.
[0042] Among them, the above-mentioned second back field layer 401 is a P-type AlGaInP layer, the second base layer 402 is a Zn-doped P-type GaInP layer, the third emitter layer 403 is an N-type GaInP layer, and the second window layer 404 is an N-type AlInP layer, that is, the third sub-cell 400 is a GaInP sub-cell.
[0043] Based on the above embodiments, in one embodiment of the present application, Figure 1 As shown, the solar cell epitaxial wafer also includes:
[0044] The first tunneling junction layer 500 is located between the nucleation layer 302 and the first back field layer 204, that is, the first tunneling junction layer 500 is located between the nucleation layer 302 of the second sub-cell 300 and the first back field layer 204 of the first sub-cell 200. In other words, the above-mentioned first tunneling junction layer 500 is located between the first sub-cell 200 and the second sub-cell 300, so that electrons can be transmitted between the first sub-cell 200 and the second sub-cell 300 through the first tunneling junction layer 500 when the solar cell is working.
[0045] The second tunneling junction layer 600 is located between the first window layer 203 and the second back field layer 401, that is, the second tunneling junction layer 600 is located between the first window layer 203 of the first sub-cell 200 and the second back field layer 401 of the third sub-cell 400. In other words, the above-mentioned second tunneling junction layer 600 is located between the first sub-cell 200 and the third sub-cell 400, so that electrons can be transmitted between the first sub-cell 200 and the third sub-cell 400 through the second tunneling junction layer 600 when the solar cell is working.
[0046] Among them, the above-mentioned first tunnel junction layer includes Si-doped GaAs and C-doped GaAs, which can be abbreviated as GaAs:Si / GaAs:C, and the second tunnel junction layer includes Si-doped GaAs and C-doped GaAs, which can also be abbreviated as GaAs:Si / GaAs:C.
[0047] Based on the above embodiments, in one embodiment of the present application, Figure 1 As shown, the solar cell epitaxial wafer also includes:
[0048] The ohmic contact layer 700 is located on the side of the second window layer 404 away from the third emission layer 403, that is, the ohmic contact layer 700 is located on the side of the third sub-cell 400 away from the second sub-cell 300. The ohmic contact layer is an N-type GaAs layer, which is used to enable the solar cell epitaxial wafer to be electrically connected to other components.
[0049] Based on the aforementioned embodiment, in one embodiment of the present application, the substrate is a P-type Ge substrate with a conductivity of 2-8x1018cm-3.
[0050] In order to more clearly understand the solar cell epitaxial wafer provided in the present application, the solar cell epitaxial wafer will be introduced in detail below in combination with the preparation process of the solar cell epitaxial wafer.
[0051] In this application, a p-type Ge substrate 100 with a conductivity of 2-8x1018cm-3 was used. This substrate 100 was placed in an Aixtron MOCVD system. The MOCVD system's reaction chamber had an initial pressure of 50 mbar and a growth temperature of 620°C. Using Ar as the carrier gas, source gases such as trimethylindium (TMIn), trimethylgallium (TMGa), trimethylaluminum (TMAl), diethylzinc (DEZn), silane (SiH4), arsine (AsH3), and phosphine (PH3) were introduced into the reaction chamber. First, the second emitter layer 301, or the emitter region of the second sub-cell 300, was formed by diffusion of PH3 into the substrate 100. Subsequently, the nucleation layer 302 of the second sub-cell 300 was grown, along with the first tunneling junction layer 500, the first back field layer 204, the first base layer 205, the first emitter layer 201, and the transition layer 202. Then, a large flow of PH3 gas (900 sccm) is used to purge the reaction chamber cavity to completely remove all AsH3 in the cavity, and the source gases such as SiH4, TMGa and TMIn are turned on to grow the first window layer 203. Then, the second tunnel junction layer 600, the second back field layer 401, the second base layer 402, the third emitter layer 403, the second window layer 404 and the ohmic contact layer 700 are grown in sequence, thereby forming the solar cell epitaxial wafer provided in the present application.
[0052] Correspondingly, the present application also provides a solar cell, which includes the solar cell epitaxial wafer described in any of the above embodiments, and the solar cell epitaxial wafer has been described in detail in the above embodiments and will not be repeated here.
[0053] As can be seen from the above, the present application provides a solar cell epitaxial wafer and a solar cell, the solar cell epitaxial wafer comprising: a substrate and a first sub-cell located on one side of the substrate, the first sub-cell comprising a first emitter layer, a transition layer, and a first window layer stacked in sequence. The first emitter layer is an N-type GaInAs layer, the transition layer is an N-type GaInP layer, and the first window layer is an N-type AlInP layer. It can be seen that the solar cell epitaxial wafer provided by the present application first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer, and then grows an N-type AlInP window layer. Compared with related technologies, since the solar cell epitaxial wafer first grows an N-type GaInP transition layer on its N-type GaInAs emitter layer and then grows an N-type AlInP window layer, direct contact between the N-type AlInP window layer and the N-type GaInAs emitter layer is avoided, and the Al atoms in the N-type AlInP window layer are avoided from combining with the As atoms and P atoms in the N-type GaInAs emitter layer at the same time, the formation of AlInAsP defects can be effectively avoided, which helps to improve the collection efficiency of photogenerated carriers of the solar cell, thereby improving the open-circuit voltage and short-circuit current density of the solar cell, and can effectively improve the conversion efficiency of the solar cell with the epitaxial wafer.
[0054] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant parts, refer to the description of the methods.
[0055] It should be noted that in the description of this application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a centrally located component.
[0056] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.
[0057] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A solar cell epitaxial wafer, characterized in that: include: substrate; a first sub-cell, the first sub-cell being located on one side of the substrate, the first sub-cell comprising a first emission layer, a transition layer, and a first window layer stacked in sequence, the transition layer being located between the first emission layer and the first window layer; The first emission layer is an N-type GaInAs layer, the transition layer is an N-type GaInP layer, and the first window layer is an N-type AlInP layer.
2. The solar cell epitaxial wafer according to claim 1, characterized in that: The transition layer thickness ranges from 5 nm to 10 nm, including the end points.
3. The solar cell epitaxial wafer according to claim 1, characterized in that: The first sub-cell further includes a first back field layer and a first base layer stacked in sequence, the first back field layer is located between the substrate and the first base layer, and the first emitter layer is located on a side of the first base layer away from the first back field layer; The first back field layer is a P-type AlGaAs layer, and the first base layer is a Zn-doped P-type GaInAs layer.
4. The solar cell epitaxial wafer according to claim 3, characterized in that: Also includes: a second sub-cell, the second sub-cell being located between the substrate and the first sub-cell, the second sub-cell comprising a second emission layer and a nucleation layer stacked in sequence, the second emission layer being located between the substrate and the nucleation layer, and the first back field layer being located on a side of the nucleation layer facing away from the second emission layer; The second emission layer is an emission layer formed by diffusing phosphine in the substrate, and the nucleation layer is an N-type GaInP layer.
5. The solar cell epitaxial wafer according to claim 4, characterized in that: Also includes: a third sub-cell, the third sub-cell being located on a side of the first sub-cell facing away from the second sub-cell, the third sub-cell comprising a second back field layer, a second base layer, a third emitter layer, and a second window layer stacked in sequence, the second back field layer being located on a side of the first window layer facing away from the transition layer; The second back field layer is a P-type AlGaInP layer, the second base layer is a Zn-doped P-type GaInP layer, the third emitter layer is an N-type GaInP layer, and the second window layer is an N-type AlInP layer.
6. The solar cell epitaxial wafer according to claim 5, characterized in that: Also includes: a first tunneling junction layer, wherein the first tunneling junction layer is located between the nucleation layer and the first back surface field layer; a second tunneling junction layer, wherein the second tunneling junction layer is located between the first window layer and the second back surface field layer; The first tunnel junction layer includes Si-doped GaAs and C-doped GaAs, and the second tunnel junction layer includes Si-doped GaAs and C-doped GaAs.
7. The solar cell epitaxial wafer according to claim 6, characterized in that: Also includes: An ohmic contact layer is located on a side of the second window layer away from the third emission layer, and the ohmic contact layer is an N-type GaAs layer.
8. The solar cell epitaxial wafer according to any one of claims 1 to 7, characterized in that: The substrate has an electrical conductivity of 2-8x10 18 cm -3 P-type Ge substrate.
9. A solar cell, characterized in that: The invention comprises the solar cell epitaxial wafer according to any one of claims 1 to 8.