Chip board level test board, chip board level test machine and chip board level test system

Abstract

The utility model discloses a chip board level test board, a chip board level test machine and a chip board level test system. The chip board level test board comprises a substrate having a first surface and a second surface, the first surface being configured to set a chip to be tested; the substrate is provided with a via hole array, at least part of via holes in the via hole array correspond to the solder ball array of the chip to be tested, and the via hole array is configured to connect the solder ball array in parallel to the second surface. The design packaging time of the chip can be effectively shortened, and the test efficiency of the chip board-level reliability test is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip board-level testing board, a chip board-level testing machine, and a chip board-level testing system. Background Art

[0002] Board-Level Reliability (BLR) testing simulates the temperature fluctuations (temperature cycling) that a chip experiences during board-level use, including drops and bending. The test examines the solder joints between the chip and the printed circuit board (PCB) for abnormalities (such as solder ball cracking) to verify the long-term reliability of the solder joints. However, solder balls are small and covered by the chip and PCB, making abnormalities difficult to detect visually. Typically, changes in the electrical properties of the solder joint (such as resistance) are used to locate the abnormality.

[0003] In the related art, in order to facilitate BLR testing of chips, a separate packaging substrate needs to be designed, which results in a long design and packaging cycle and low testing efficiency. Utility Model Content

[0004] In order to solve the above technical problems, the present disclosure provides a chip board-level test board, a chip board-level test bench and a chip board-level test system to solve the problems of needing to design a packaging substrate separately, long design and packaging cycles and low testing efficiency.

[0005] In a first aspect of the present disclosure, a chip board-level test board is provided, comprising:

[0006] A substrate having a first surface and a second surface, wherein the first surface is configured to place a chip to be tested;

[0007] A via array is provided on the substrate, at least some of the vias in the via array correspond to the solder ball array of the chip to be tested, and the via array is configured to connect the solder ball array in parallel to the second surface.

[0008] A second aspect of the present disclosure provides a chip board-level test machine, comprising:

[0009] Machine body;

[0010] A plug connector is provided on the machine body, the plug connector having pins configured to be electrically connected to the chip board-level test board provided by the first aspect of the present disclosure;

[0011] The plug connector is located on the second surface of the chip board level test board, and the plug pins are configured to be electrically connected to the via holes in the via hole array of the chip board level test board.

[0012] A third aspect of the present disclosure provides a chip board-level testing system, comprising the chip board-level testing board provided by the first aspect of the present disclosure and the chip board-level testing machine provided by the second aspect of the present disclosure.

[0013] The present disclosure provides a chip board-level test board, a chip board-level test machine, and a chip board-level test system. By providing a via array on the substrate of the chip board-level test board, at least some of the vias in the via array correspond to the solder ball array of the chip to be tested, and the via array is configured to connect the solder ball array in parallel to the second surface. Thus, when performing board-level testing on the chip, the chip can be provided on the first surface of the substrate, and the chip's solder ball array is connected in parallel to the second surface via the via array. The test bench can then perform board-level reliability testing on the chip's solder balls on the second surface; this is equivalent to extending the chip's solder ball array through the vias and extending it to the second surface of the substrate. Compared to related art, when performing board-level reliability testing on the chip's solder ball array, the test bench can perform the test directly on the second surface of the substrate, eliminating the need to connect the solder ball array in series via gold wire within the chip's packaging substrate. Therefore, there is no need to design a separate packaging substrate for the chip's board-level reliability testing. This can effectively shorten the chip's design and packaging time, improving the efficiency of chip board-level reliability testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a structural diagram of a chip board-level test board and a chip to be tested provided by an exemplary embodiment of the present disclosure;

[0015] Figure 2 is a schematic structural diagram of a chip board-level test board provided by another exemplary embodiment of the present disclosure;

[0016] Figure 3 is a structural schematic diagram of a chip board-level test board provided by another exemplary embodiment of the present disclosure;

[0017] Figure 4 is a cross-sectional view of a chip board-level test board provided by an exemplary embodiment of the present disclosure;

[0018] Figure 5 is a cross-sectional view of a chip local test board and a chip provided by an exemplary embodiment of the present disclosure;

[0019] Figure 6 is a cross-sectional view of a chip board-level test board provided by another exemplary embodiment of the present disclosure;

[0020] Figure 7 yes Figure 6 A partial enlarged view of point A in the middle;

[0021] Figure 8is a structural schematic diagram of a chip board level test machine provided by another exemplary embodiment of the present disclosure;

[0022] Figure 9 is a structural schematic diagram of a chip board level test machine provided by another exemplary embodiment of the present disclosure;

[0023] Figure 10 is a structural schematic diagram of a chip board level test machine provided by another exemplary embodiment of the present disclosure;

[0024] Legend of reference signs:

[0025] 120-chip board level test board; 210, 220-chip to be tested; 300-chip board level test machine;

[0026] 121-substrate; 122-first surface; 123-second surface; 124-via array; 211, 221-solder ball; 212-encapsulation substrate; 310-machine body; 320-connector; 321-connector pin;

[0027] 1241-via; 1241a-first hole segment; 1241b-second hole segment; 1241c-third hole segment. DETAILED DESCRIPTION

[0028] In order to explain the present disclosure, the exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. It should be understood that the present disclosure is not limited by the exemplary embodiments.

[0029] In order to make the technical personnel in the art better understand the technical solutions in the present disclosure, the technical solutions in the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present disclosure.

[0030] It should be noted that in the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present disclosure is not limited by the specific embodiments disclosed below.

[0031] In the description of the present disclosure, it should be understood that the terms "upper," "lower," "horizontal," "bottom," "inner," "outer" (if any), etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of the present disclosure and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present disclosure. In the present disclosure, unless otherwise expressly provided or limited, a first feature being "above" or "below" a second feature may be when the first and second features are in direct contact, or when the first and second features are in indirect contact through an intermediate medium.

[0032] In this disclosure, unless otherwise expressly specified or limited, the terms "connected," "connected," "fixed," and the like should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be directly connected, or indirectly connected through an intermediate medium; they can be internally connected between two elements, or they can be an interactive relationship between two elements. However, if it is indicated as being directly connected, it means that the two connected entities are not connected through an intermediate structure, but are only connected to form a whole through a connecting structure. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood according to the specific circumstances.

[0033] In this disclosure, references to "first," "second," and the like are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referenced. Therefore, features specified as "first" or "second" may explicitly or implicitly include at least one of these features.

[0034] Board-Level Reliability (BLR) testing simulates temperature fluctuations (also called temperature cycling in some cases), drops, and bending conditions encountered by chips during board-level use. The test then examines the solder joints between the chip and the PCB for abnormalities (such as solder ball cracking) to verify the long-term reliability of the solder joints between the chip and the PCB.

[0035] Typically, solder balls are small and, after the chip is mounted on the PCB, they are covered by the chip and PCB. Abnormal solder balls can be difficult to detect visually. Typically, changes in the electrical properties of the solder joint (such as resistance) are detected to locate the abnormality.

[0036] Figure 1 It is a structural diagram of the cooperation between a chip board-level test board and a chip to be tested provided by an exemplary embodiment of the present disclosure.

[0037] For some examples, refer to Figure 1As shown, after the chip is mounted on the PCB, the solder ball 211 is located between the chip and the PCB and is blocked by the chip and the PCB, so that the electrical properties of the solder ball 211 cannot be directly tested.

[0038] For some examples, refer to Figure 1 As shown, in order to facilitate BLR testing of the chip, the chip packaging substrate 111 is designed when the chip is packaged, and two adjacent solder balls 211 are connected in pairs through wires (in some examples, gold wires) in the packaging substrate 111.

[0039] In some examples, traces may be designed on the PCB, and the traces may be connected to the solder balls 211 , thereby conducting the chip pads.

[0040] In some examples, traces can connect to some pads of the chip.

[0041] In some examples, traces can connect to all pads on the chip.

[0042] In some examples, after the chip is mounted on a PCB, the traces on the PCB and the wires within the package substrate 111 connect the solder balls 211, whose resistance changes are to be observed, in series to form a series circuit. During the BLR test, the change in resistance across the series circuit can be measured to detect solder joint anomalies.

[0043] However, such BLR testing of the chip requires a separate design of the packaging substrate 111, which results in a long chip design and packaging cycle and low testing efficiency.

[0044] In view of this, in some examples of the present disclosure, a chip board-level test board is provided. A via array is provided on the substrate of the board-level test board, and at least some of the vias in the via array correspond to the solder ball array of the chip to be tested. The chip to be tested can be mounted on the first surface of the substrate; the via array can be configured to connect the solder ball array in parallel to the second surface. In this way, the solder ball array covered by the chip and the substrate can be connected to the second surface through the via array, and the electrical properties of the solder ball array can be tested on the second surface. There is no need to design the chip packaging substrate separately. It can effectively shorten the design and packaging time of the chip and improve the test efficiency of the chip board-level reliability test.

[0045] Figure 2 It is a structural schematic diagram of a chip board-level test board provided by another exemplary embodiment of the present disclosure. Figure 3 3 is a schematic structural diagram of a chip board-level test board provided by another exemplary embodiment of the present disclosure.

[0046] For some examples, refer to Figure 2 and Figure 3As shown, some example embodiments of the present disclosure provide a chip board level test board 120. The chip board level test board 120 can include a substrate 121.

[0047] In some examples, the substrate 121 can be a PCB. It can be appreciated that the type of the substrate 121 is merely shown as an example in some example embodiments of the present disclosure, and is not intended to limit the specific type of the substrate 121. In some examples, the substrate 121 can also be other types of substrates 121.

[0048] In some examples, referring to Figure 2 As shown, the substrate 121 can have a first surface 122. The first surface 122 can be configured to dispose a chip 220 to be tested. That is, the chip can be mounted on the first surface 122 of the substrate 121 when the chip is tested by BLR.

[0049] In some examples, referring to Figure 3 As shown, the substrate 121 can have a second surface 123. The second surface 123 can be disposed opposite to the first surface 122.

[0050] It can be appreciated that in some examples, the chip can be mounted on the second surface 123 of the substrate 121 when the chip is tested by BLR. In some example embodiments of the present disclosure, only the chip mounted on the first surface 122 of the substrate 121 is specifically described as an example.

[0051] Figure 4 FIG. 12 is a cross-sectional view of a chip board level test board provided by an example embodiment of the present disclosure.

[0052] In some examples, referring to Figure 2-Figure 4 As shown, the substrate 121 can be provided with a via array 124. The vias 1241 in the via array 124 can electrically connect the first surface 122 and the second surface 123. For example, the first surface 122 can be provided with first traces, and the second surface 123 can be provided with second traces. The vias 1241 can electrically connect the first traces and the second traces.

[0053] Figure 5 FIG. 13 is a cross-sectional view of a chip native test board cooperating with a chip provided by an example embodiment of the present disclosure.

[0054] In some examples, referring to Figure 5 As shown, at least some of the vias 1241 in the via array 124 can correspond to an array of solder balls 221 of the chip 220 to be tested.

[0055] In some examples, the number of vias 1241 in the via array 124 can be greater than the number of solder balls 221 in the solder ball array 221. That is, when a chip is mounted on the first surface 122 of the substrate 121 for BLR testing, some vias 1241 in the via array 124 can be idle (not paired with solder balls 221 in the solder ball array 221). In this way, the chip board-level test board 120 can perform BLR testing on chips with different numbers of solder balls 221, expanding the applicability of the chip board-level test board 120.

[0056] In some examples, when performing BLR testing on a chip, the chip can be mounted on the second surface 123 of the substrate 121. It is understood that the mounting of the chip on the second surface 123 of the substrate 121 is similar to the mounting on the first surface 122 of the substrate 121 described in detail in the previous embodiments of the present disclosure. For specific mounting methods, reference can be made to the detailed description of the previous embodiments of the present disclosure, and this will not be repeated in some exemplary embodiments of the present disclosure.

[0057] The chip board-level test board 120 provided in the present disclosure is configured by providing a via array 124 on a substrate 121. At least some of the vias 1241 in the via array 124 correspond to the array of solder balls 221 of the chip 220 to be tested. The via array 124 is configured to connect the array of solder balls 221 in parallel to the second surface 123. Thus, when performing board-level testing on a chip, the chip can be placed on the first surface 122 of the substrate 121, and the array of solder balls 221 of the chip can be connected in parallel to the second surface 123 through the via array 124. The test bench can then perform board-level reliability testing on the chip's solder balls 221 on the second surface 123; this is equivalent to extending the array of solder balls 221 of the chip through the vias 1241 and extending it to the second surface 123 of the substrate 121. Compared to related technologies, when performing board-level reliability testing on the chip's solder ball array 221, the test bench can test directly on the second surface 123 of the substrate 121, eliminating the need to connect the solder ball array in series via gold wires within the chip's package substrate. Therefore, there's no need to design a separate package substrate specifically for chip board-level reliability testing. This effectively shortens chip design and packaging time, improving the efficiency of chip board-level reliability testing.

[0058] For some examples, refer to Figure 5 As shown, a via 1241 in the via array 124 is configured to correspond to a solder ball 221 in the solder ball 221 array, and each via 1241 in the via array 124 is configured to correspond to a different solder ball 221 in the solder ball 221 array.

[0059] That is, in some exemplary embodiments of the present disclosure, the number of vias 1241 in the via array 124 can be the same as the number of solder balls 221 in the solder ball array 221. In other words, there can be a one-to-one correspondence between vias 1241 and solder balls 221. Thus, vias 1241 can connect solder balls 221 in parallel to the second surface 123.

[0060] In some examples, when performing BLR testing on a chip, the chip can be mounted on the first surface 122 of the substrate 121. The solder balls 221 in the solder ball array 221 are mounted correspondingly to the vias 1241 in the via array 124, thereby connecting the solder ball array 221 in parallel to the second surface 123.

[0061] In some exemplary embodiments of the present disclosure, one via 1241 in the via array 124 is configured to correspond to one solder ball 221 in the array of solder balls 221, and another via 1241 in the via array 124 is configured to correspond to a different solder ball 221 in the array of solder balls 221. This one-to-one correspondence between vias 1241 and solder balls 221 facilitates chip mounting on substrate 121 during BLR testing, improves chip mounting efficiency, and reduces BLR testing time.

[0062] In some examples, the conductor filled in the via 1241 may include a plated solid filler.

[0063] It can be understood that the filling method of the electroplated solid filler in the via 1241 can be the same as, close to, or similar to the filling method in the PCB via 1241 during the specific application of the chip.

[0064] In this way, the chip board-level test board 120 can be closer to the application board when the chip is actually used, can more fully simulate the actual application scenario of the chip, and improve the accuracy of the BLR test on the chip.

[0065] Figure 6 FIG. 4 is a cross-sectional view of a chip board-level test board provided by another exemplary embodiment of the present disclosure. Figure 7 yes Figure 6 A magnified partial view of point A in the middle.

[0066] For some examples, refer to Figure 6 and Figure 7 As shown, the via 1241 may include a first hole segment 1241 a. The first hole segment 1241 a may be electrically connected to the first surface 122. In other words, the first hole segment 1241 a may pass through the first surface 122 and be electrically connected to the first trace on the first surface 122.

[0067] In some examples, the first hole section 1241 a can be configured to be electrically connected to the solder ball 221 of the chip under test 220 , so that the solder ball 221 can be electrically connected to the second surface 123 through the first hole section 1241 a .

[0068] In some examples, the arrangement of the first hole segment 1241a on the substrate 121 may be the same, similar or similar to the arrangement of the via 1241 on the application board of the chip during specific application, which will not be described in detail in the embodiments of the present disclosure.

[0069] For some examples, refer to Figure 6 and Figure 7 As shown, the via hole 1241 may include a second hole segment 1241b. The second hole segment 1241b may be in electrical communication with the first hole segment 1241a.

[0070] In some examples, the electroplated solid filler in the second hole segment 1241 b can be electrically connected to the electroplated solid filler in the first hole segment 1241 a .

[0071] In some examples, the via 1241 may include a third hole segment 1241 c . The third hole segment 1241 c may be electrically connected to the second hole segment 1241 b . The third hole segment 1241 c may be electrically connected to the second surface 123 .

[0072] It should be noted that, in some exemplary embodiments of the present disclosure, the conduction method between the third hole segment 1241c and the second hole segment 1241b can refer to the conduction method between the first hole segment 1241a and the second hole segment 1241b in the aforementioned embodiments of the present disclosure, and will not be repeated in some exemplary embodiments of the present disclosure.

[0073] In addition, the conduction method between the third hole segment 1241c and the second surface 123 can refer to the conduction method between the first hole segment 1241a and the first surface 122 in the aforementioned embodiments of the present disclosure, and will not be repeated in some exemplary embodiments of the present disclosure.

[0074] In some examples, the type of the via 1241 in the second hole segment 1241 b is different from the type of the via 1241 in the first hole segment 1241 a and the third hole segment 1241 c .

[0075] In some exemplary embodiments of the present disclosure, the type of via 1241 in the second hole segment 1241b is set to be different from the type of via 1241 in the first hole segment 1241a and the third hole segment 1241c. This can simulate the actual conditions of chip board-level applications. That is, the chip board-level test board 120 simulates the actual conditions of the application board, which can improve the accuracy of BLR testing of chips.

[0076] In some examples, the via 1241 of the second hole segment 1241b may include a buried via. It is understood that in some exemplary embodiments of the present disclosure, the arrangement of the buried vias may refer to the arrangement of buried vias in the application board in the specific application scenario of the chip, and this will not be repeated in some exemplary embodiments of the present disclosure.

[0077] Setting the via 1241 type in the second hole segment 1241b to a buried via simulates real-world chip-board-level applications. Furthermore, during BLR testing, any anomalies such as delamination within the PCB can be detected during electrical testing. For example, the PCB can be cut open to observe the condition of the second hole segment 1241b.

[0078] In some examples, the type of via 1241 in at least one of the first hole segment 1241a and the third hole segment 1241c may include a blind hole.

[0079] In some examples, the type of via 1241 in the first hole segment 1241 a may include a blind hole.

[0080] In some examples, the type of via 1241 in the third hole segment 1241 c may include a blind hole.

[0081] In some examples, the via 1241 type of the first hole segment 1241a and the third hole segment 1241c may both include blind holes.

[0082] In some exemplary embodiments of the present disclosure, at least one of the first hole segment 1241a and the third hole segment 1241c is configured as a blind via. This simulates the actual board-level chip application and improves the accuracy of BLR testing of the chip.

[0083] In some examples, the substrate 121 may include a multi-layer board. The first hole segment 1241a may be a via segment between the first layer and the second layer. The side of the first layer facing away from the second layer may be the first surface 122 .

[0084] In some examples, the second hole segment 1241b may be a conductive hole segment between the second layer and the (n-1)th layer.

[0085] In some examples, the third hole segment 1241c may be a via segment between the n-1th layer and the nth layer. The side of the nth layer facing away from the n-1th layer may be the second surface 123. n may be the number of layers of the multilayer board.

[0086] In some examples, a multi-layer board with 12 layers is used as an example. In some exemplary embodiments, the first hole segment 1241a may be a via segment between the first and second layers. The second hole segment 1241b may be a via segment between the second and eleventh layers. The third hole segment 1241c may be a via segment between the eleventh and twelfth layers.

[0087] It is understood that in some exemplary embodiments of the present disclosure, the number of layers of the substrate 121 is shown as a specific example only and does not limit the number of layers of the substrate 121. In some other exemplary embodiments of the present disclosure, the number of layers of the substrate 121 may also be other numbers.

[0088] In some exemplary embodiments of the present disclosure, first via segment 1241a is configured as a via segment between the first and second layers, second via segment 1241b is configured as a via segment between the second and n-1th layers, and third via segment 1241c is configured as a via segment between the n-1th and nth layers. This simulates the real-world conditions of chip board-level applications and improves the accuracy of BLR testing of chips.

[0089] Figure 8 It is a structural schematic diagram of a chip board-level testing machine provided by another exemplary embodiment of the present disclosure. Figure 9 The figure is a schematic structural diagram of a chip board-level test machine provided by an exemplary embodiment of the present disclosure performing board-level testing on a chip.

[0090] For some examples, refer to Figure 8 and Figure 9 As shown, some exemplary embodiments of the present disclosure provide a chip board-level test platform 300 . The chip board-level test platform 300 may include a platform body 310 .

[0091] In some examples, the machine body 310 may adopt the machine body 310 in the related art, which will not be described in detail in some exemplary embodiments of the present disclosure.

[0092] In some examples, the chip board-level test machine 300 may include a plug connector 320. The plug connector 320 may be disposed on the machine body 310. The plug connector 320 may be fixedly connected to the machine. The plug connector 320 may be movably connected to the machine. The plug connector 320 may be detachably connected to the machine.

[0093] For some examples, refer to Figure 8 and Figure 9 As shown, the plug connector 320 may have pins 321. The pins 321 may be configured to be electrically connected to the chip board-level test board 120 provided in the previous embodiment of the present disclosure, so as to perform a BLR test on the chip disposed on the chip board-level test board 120.

[0094] In some examples, the chip is mounted on the first surface 122 of the chip board level test board 120 as an example for detailed description. Figure 9As shown, the plug header 320 may be located on the second surface 123 of the chip board level test board 120 . The plug pin 321 may be configured to be electrically connected to the via 1241 in the via array 124 of the chip board level test board 120 .

[0095] That is, in some exemplary embodiments of the present disclosure, the pin 321 may be a conductor.

[0096] In some examples, the pins 321 may be gold, silver, or copper. In some examples, the pins 321 may also be alloy pins. In some exemplary embodiments of the present disclosure, the specific material of the pins 321 is not limited.

[0097] In some examples, the pin 321 can directly electrically contact the via 1241, thereby achieving electrical continuity with the via 1241. For example, the pin 321 can electrically contact the third hole segment 1241c. Alternatively, in some examples, the pin 321 can be inserted into the third hole segment 1241c and electrically contact the electroplated solid filler filled in the second hole segment 1241b, thereby achieving electrical continuity with the via 1241.

[0098] In some examples, the via 1241 can be electrically connected to the trace on the second surface 123 . The pin 321 can be electrically connected to the trace on the second surface 123 , thereby achieving electrical connection with the via 1241 .

[0099] In some exemplary embodiments of the present disclosure, a plug connector 320 is provided on the machine body 310. The plug connector 320 may have a pin 321. Thus, after the BRL test of the chip is completed, the chip board-level test board 120 on which the chip is mounted can be electrically connected to the pin 321 of the plug connector 320. In other words, the pin 321 is electrically connected to the via 1241 in the via array 124 of the chip board-level test board 120. Thus, since the via 1241 is electrically connected to the solder ball 221 of the chip, the chip board-level test machine can electrically connect the pin 321, the via 1241, and the solder ball 221, thereby performing an electrical test on the solder ball 221.

[0100] For some examples, refer to Figure 8 and Figure 9 As shown, the pins 321 may include a plurality of pins 321 . The plurality of pins 321 may be constructed to form a pin array 321 . The pin array 321 may be configured to be electrically connected to the via array 124 .

[0101] In some examples, the number of pins 321 in the pin array 321 can be less than the number of vias 1241 in the via array 124. For example, the number of vias 1241 in the via array 124 can be 1000, while the number of pins 321 in the pin array 321 can be 500. When performing an electrical test on the solder balls 221, the pin array 321 can first correspond to 500 of the vias 1241, electrically conducting with the vias 1241, thereby testing the electrical properties of the solder balls 221 corresponding to these 500 vias 1241. Then, the pin array 321 can correspond to another 500 vias 1241, electrically conducting with the vias 1241, thereby testing the electrical properties of the solder balls 221 corresponding to the other 500 vias 1241.

[0102] It should be noted that, in some exemplary embodiments of the present disclosure, the number of vias 1241 and the number of pins 321 are merely used as a specific example for illustration, and are not intended to limit the number of vias 1241 and the number of pins 321 .

[0103] In some examples of the disclosed embodiments, multiple pins 321 are provided, forming a pin array. This allows the electrical properties of solder balls 221 to be tested after the chip undergoes a BLR test, by establishing electrical continuity between the pin array 321 and the via array 124. This allows for batch testing of solder balls 221, improving BLR testing efficiency.

[0104] In some examples, the pins 321 may include a first pin 321 . The first pin 321 may be configured to be electrically connected to one of the vias 1241 of the via array 124 .

[0105] For some examples, refer to Figure 9 As shown, the first pin 321 may be an output pin 321 for a current or voltage signal when the chip board-level test machine 300 performs an electrical test on the solder balls 221 of the chip.

[0106] In some examples, the first pin 321 can be fixed to the machine body 310. The via 1241 electrically connected to the first pin 321 can remain unchanged. That is, when the chip board-level test board 120 is connected to the chip board-level test machine 300 for electrical testing, after the first pin 321 is electrically connected to one of the vias 1241 in the via array 124, the via 1241 electrically connected to the first pin 321 remains unchanged.

[0107] In some examples, the first pin 321 may be any pin 321 in the array of pins 321 .

[0108] In some examples, the pin 321 may include a second pin 321 . The second pin 321 may be configured to be electrically connected to another via 1241 in the via array 124 .

[0109] In some examples, the second pin 321 may be any pin 321 in the pin array 321 except the first pin 321 .

[0110] In some examples, the second pin 321 can be movably disposed on the machine body 310. When performing electrical testing on the solder balls 221 of the chip, the second pin 321 can be movable between multiple vias 1241. For example, the first pin 321 can be electrically connected to one of the vias 1241 in the via array 124. The second pin 321 can be movable between other vias 1241 in the via array 124, thereby testing the electrical properties of the solder balls 221 corresponding to each via 1241. In this way, the electrical properties of the solder balls 221 can be tested one by one, and abnormal solder balls 221 can be quickly identified, thereby improving the efficiency of chip BLR testing.

[0111] In some examples, the number of pins 321 in the pin 321 array may be greater than the number of vias 1241 in the via array 124. For example, the number of vias 1241 in the via array 124 may be 1,000, and the number of pins 321 in the pin 321 array may be 2,000. When performing an electrical test on the solder balls 221 of the chip, 1,000 pins 321 in the pin 321 array may correspond to the 1,000 vias 1241 in the via array 124, and the electrical test on the solder balls 221 of the chip may be performed. The other 1,000 pins 321 may not be involved in the test. In this way, tests can be performed on different numbers of solder balls 221, thereby improving the scope of application of the chip board-level test machine 300.

[0112] For some examples, refer to Figure 9 As shown, one pin 321 among the plurality of pins 321 may be configured to correspond to one via 1241 in the via array 124 , and each pin 321 among the plurality of pins 321 may be configured to correspond to a different via 1241 in the via array 124 .

[0113] In other words, the number of pins 321 in the pin array 321 can be equal to the number of vias 1241 in the via array 124. There can be a one-to-one correspondence between pins 321 and vias 1241. For example, the number of vias 1241 in the via array 124 can be 1000, and the number of pins 321 in the pin array 321 can also be 1000. This one-to-one correspondence between pins 321 and vias 1241 allows electrical testing of all solder balls 221 on the chip to be performed simultaneously, improving BLR testing efficiency.

[0114] In some other exemplary embodiments of the present disclosure, a chip board-level test system is provided, which may include the chip board-level test board 120 and the chip board-level test machine 300 described in detail in the previous embodiments of the present disclosure.

[0115] Figure 10 This is an IV curve diagram of an electrical test performed on any pin in a chip by a chip board-level test machine provided by an exemplary embodiment of the present disclosure.

[0116] For some examples, refer to Figure 10 As shown, when performing BLR testing on a chip, the chip under test 220 can first be mounted on the chip board-level test board 120 described in detail in the previous embodiments of this disclosure. For example, the chip can be mounted on the first surface 122 of the substrate 121. The array of solder balls 221 on the chip corresponds to the array of vias 124 on the chip board-level test board 120.

[0117] In some examples, after the chip to be tested 220 is mounted, a board-level test board can be installed on a board-level test machine to perform an initial electrical test on the solder balls 221 .

[0118] For some examples, see Figure 10 As shown in the middle curve a, a voltage can be given to each solder ball 221 of the chip 220 to be tested, and the current is recorded to form an initial IV curve ( Figure 10 Middle curve a).

[0119] In some examples, after completing the initial electrical test and drawing the initial IV curve, the chip board level test board 120 can be removed from the chip board level test machine 300 to perform tests such as drop, temperature cycle, and force bending.

[0120] In some examples, the BLR experiment time may be a preset time length.

[0121] In some examples, the preset time length can be 800 hours, 1000 hours, or 1200 hours. It should be understood that in some exemplary embodiments of the present disclosure, the specific value of the preset time length is provided only as an example and does not limit the duration of the BLR experiment. Those skilled in the art can select a preset time length based on the specific application environment of the chip.

[0122] In some examples, electrical testing can be performed on the solder balls 221 of the chip under test 220 at predetermined time points within a preset time length.

[0123] In some examples, the predetermined time points may be 0h (ie, testing the initial IV curve), 168h, 500h, and 1000h for testing the electrical properties of the solder ball 221 .

[0124] For some examples, refer to Figure 10 As shown in the middle curve b, after the BLR test, if the solder ball 221 has abnormal conditions such as cracks, the impedance will increase, and the current will decrease at the same voltage.

[0125] In some examples, when the change in current is greater than a preset threshold, it can be determined that the solder ball 221 is abnormal.

[0126] It should be noted that in some exemplary embodiments of the present disclosure, the preset threshold may be set according to the specific application environment of the chip, and the embodiments of the present disclosure do not limit this.

[0127] In addition, in some exemplary embodiments of the present disclosure, referring to Figure 10 As shown in FIG, since the current of different power supplies is different, when the current is small, the unit of current may be μA (microampere); and when the current is large, the unit of current may be mA (milliampere). Generally, the unit of voltage may be V (volt). Therefore, the appendix of some exemplary embodiments of the present disclosure Figure 10 The units of current and voltage are not marked.

[0128] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be considered as essential to each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0129] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A chip board-level test board, characterized in that: include: A substrate having a first surface and a second surface, wherein the first surface is configured to place a chip to be tested; A via array is provided on the substrate, at least some of the vias in the via array correspond to the solder ball array of the chip to be tested, and the via array is configured to connect the solder ball array in parallel to the second surface.

2. The chip board level test board according to claim 1, characterized in that: A via in the via array is configured to correspond to a solder ball in the solder ball array, and each of the vias in the via array is configured to correspond to a different solder ball in the solder ball array.

3. The chip board level test board according to claim 1, characterized in that: The conductor filled in the via hole includes an electroplated solid filling piece.

4. The chip board level test board according to claim 1, characterized in that: The first surface and the second surface are located on opposite sides of the substrate; the via hole includes a first hole segment, a second hole segment and a third hole segment; The first hole segment is in electrical communication with the first surface; the second hole segment is in electrical communication with the first hole segment, and the second hole segment is in electrical communication with the third hole segment; the third hole segment is in electrical communication with the second surface; The via type of the second hole segment is different from the via types of the first hole segment and the third hole segment.

5. The chip board level test board according to claim 4, characterized in that: The via type of the second hole segment includes a buried via.

6. The chip board level test board according to claim 4 or 5, characterized in that: The via type of at least one of the first hole segment and the third hole segment includes a blind hole.

7. The chip board level test board according to claim 4 or 5, characterized in that: The substrate includes a multilayer board, the first hole segment is a conductive hole segment between the first layer and the second layer, and the side of the first layer facing away from the second layer is the first surface; the second hole segment is a conductive hole segment between the second layer and the n-1th layer; the third hole segment is a conductive hole segment between the n-1th layer and the nth layer, and the side of the nth layer facing away from the n-1th layer is the second surface; wherein n is the number of layers of the multilayer board.

8. A chip board level test machine, characterized in that: include: Machine body; a plug connector, provided on the machine body, the plug connector having a pin, the pin being configured to be electrically connected to the chip board-level test board according to any one of claims 1 to 7; The plug connector is located on the second surface of the chip board level test board, and the plug pin is configured to be electrically connected to the via holes in the via array of the chip board level test board.

9. The chip board level testing machine according to claim 8, characterized in that: The pins include a plurality of pins, and the plurality of pins form a pin array, and the pin array is configured to be electrically connected to the via array.

10. The chip board level testing machine according to claim 9, characterized in that: The pin includes: A first pin, wherein the first pin is configured to be electrically connected to one of the vias in the via array; The second pin is configured to be electrically connected to another via in the via array.

11. The chip board level testing machine according to claim 10, characterized in that: One of the plurality of pins is configured to correspond to one of the vias in the via array, and each of the plurality of pins is configured to correspond to a different via in the via array.

12. A chip board-level testing system, characterized in that: It comprises the chip board-level test board according to any one of claims 1-7, and the chip board-level test machine according to any one of claims 8-11.

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