Visible light optical fiber driving circuit and optical fiber transmission system
By introducing charge discharge bypass and PMOS/NMOS tube control in the visible light fiber driving circuit, the problem of excess carrier recombination caused by LED junction capacitance is solved, and the data transmission rate of high-speed optical communication is improved.
Patent Information
- Application Number
- CN202422619516.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2034-10-29
AI Technical Summary
In the prior art, the problem of excess carrier recombination and luminescence caused by the junction capacitance of LEDs limits the data transmission rate of visible light communication to no more than 1 Mbps.
A visible light fiber driving circuit is adopted, including an optical signal transmission circuit and a charge discharge bypass. PMOS and NMOS tubes are used to control the on and off of the light-emitting diode, and the charge discharge bypass driving circuit is used to quickly clear carriers, thereby reducing the pulse rise and fall time of the light-emitting diode.
It achieves rapid carrier removal, significantly improves the response speed of the light-emitting diode, and increases the data transmission rate to meet the high-speed optical communication requirements of around 50MHz.
Smart Images
Figure CN223428450U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronic circuits, in particular to a visible light optical fiber driving circuit and an optical fiber transmission system. Background Art
[0002] Visible light fiber optic communication loads the digital signal to be transmitted onto the LED and emits the optical signal through high and low pulse drive voltages. As the transmission data rate increases, the emission rate also increases accordingly. Since the LED is essentially a diode with junction capacitance, at the moment when the pulse voltage at both ends of the LED diode jumps, the junction capacitance still accumulates a large amount of excess carriers, resulting in weak composite luminescence. The LED cannot be completely extinguished, affecting the LED optical communication and preventing it from increasing the data transmission rate. Figure 1 It is the response waveform of the light emitting diode in the prior art. Figure 1 It is clearly seen in the figure that due to the excess carriers, the LED output rises very slowly from a low level to a high level, and it takes 0.8us to turn off. This shows that with traditional LED driving methods, the LED signal modulation rate is no more than 1Mbps. Utility Model Content
[0003] In view of the deficiencies in the prior art, the utility model discloses a visible light optical fiber driving circuit and an optical fiber transmission system.
[0004] The technical solutions adopted in this utility model are as follows:
[0005] A visible light optical fiber driving circuit includes an optical signal transmitting circuit and a charge discharge bypass;
[0006] One end of the optical signal transmitting circuit is connected to a power supply, and the other end is grounded; the optical signal transmitting circuit includes a light-emitting diode and a drive control circuit connected in series; the drive control circuit includes a drive control tube; the drive end of the drive control tube is used to input a drive signal;
[0007] The charge discharge bypass includes a first branch and a second branch; the first branch is connected in parallel to the light-emitting diode, and the second branch is connected in parallel to the drive control circuit; the first branch is turned on for a first predetermined time when the drive signal jumps from a low level to a high level; the second branch is turned on for a second predetermined time when the drive signal jumps from a high level to a low level.
[0008] A further technical solution is that the drive control circuit further includes a constant current source module; and the output end of the drive control tube is connected in series with the constant current source module.
[0009] A further technical solution is that the first branch includes a first switching tube; the second branch includes a second switching tube; the first switching tube and the second switching tube are of different types; the two output ends of the first switching tube are connected in parallel to the light-emitting diode; the two output ends of the second switching tube are connected in parallel to the drive control circuit; the drive end of the first switching tube controls the conduction and disconnection of the first branch; and the drive end of the second switching tube controls the conduction and disconnection of the second branch.
[0010] Its further technical solution is that the visible light fiber driving circuit also includes a charge discharge bypass driving circuit; the driving signal is input into the input end of the charge discharge bypass driving circuit, and the first output end of the charge discharge bypass driving circuit is connected to the driving end of the first switching tube; the second output end of the charge discharge bypass driving circuit is connected to the driving end of the second switching tube; the output signals of the first output end and the second output end of the charge discharge bypass driving circuit are reversed.
[0011] A further technical solution is that the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube.
[0012] A further technical solution is that the visible light fiber driving circuit further includes a charge discharge bypass driving circuit; the charge discharge bypass driving circuit includes a PMOS tube driving circuit and an NMOS tube driving circuit;
[0013] The PMOS transistor drive circuit includes a first NAND gate, a first inverter, a second inverter, and a third inverter connected in series in sequence; the input end of the first inverter is used to input the drive signal; the common end of the first inverter and the second inverter is connected to the first input end of the first NAND gate; the output end of the third inverter is connected to the second input end of the first NAND gate; the common end of the second inverter and the third inverter is grounded via a delay capacitor; and the output end of the first NAND gate outputs the PMOS transistor drive signal;
[0014] The NMOS transistor drive circuit includes a second NAND gate and a fourth inverter; the drive signal is input to the first input terminal of the second NAND gate; the common terminal of the second inverter and the third inverter is connected to the second input terminal of the second NAND gate; the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter; and the output terminal of the fourth inverter outputs the NMOS transistor drive signal.
[0015] A further technical solution is that the value range of the delay capacitor is 0.5pf to 2pf; the pulse width range of the NMOS tube drive signal is 1ns to 10ns, and the pulse width range of the PMOS tube drive signal is 1ns to 10ns.
[0016] An optical fiber transmission system based on the visible light optical fiber driving circuit as described in any one of the above items, the optical fiber transmission system further comprising:
[0017] An optical fiber data transmission device, used to load a driving signal to the driving end of the driving control tube;
[0018] A transmission optical fiber, used for transmitting the optical pulse signal emitted by the light emitting diode;
[0019] The optical signal receiver is used to receive the optical pulse signal and convert the optical pulse signal into an electrical signal.
[0020] The beneficial effects of the utility model are as follows:
[0021] The present invention discloses a low-cost visible light fiber driver circuit that can quickly clear carriers. At the moment a light-emitting diode (LED) turns on or off, it is connected to a conduction loop, thereby rapidly releasing carriers to quickly increase or decrease the voltage at the LED end. This improved circuit can significantly reduce the rise and fall times of the LED pulse. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is the response waveform of the light emitting diode in the prior art.
[0023] Figure 2 Schematic diagram of a visible light fiber driving circuit in an embodiment of the present invention.
[0024] Figure 3 Schematic diagram of a charge discharge bypass driving circuit in an embodiment of the present invention.
[0025] Figure 4 Schematic diagram of the waveforms of the input signal and the output signal of the charge discharge bypass driving circuit in the embodiment of the present invention.
[0026] Figure 5 Response waveform of the light emitting diode in the embodiment of the present utility model. DETAILED DESCRIPTION
[0027] The specific implementation of the present utility model will be described below with reference to the accompanying drawings.
[0028] Figure 2 FIG is a schematic diagram of a visible light fiber driving circuit in an embodiment of the present utility model. Figure 2 As shown, the visible light fiber driving circuit includes an optical signal transmitting circuit and a charge discharge bypass.
[0029] One end of the optical signal transmission circuit is connected to a power supply VCC, and the other end is connected to a ground terminal gnd. The optical signal transmission circuit includes a light-emitting diode (LED) and a drive control circuit connected in series. The drive control circuit includes a drive control transistor M2. The drive terminal of the drive control transistor M2 is used to input a drive signal D.
[0030] In this embodiment, the drive control transistor M2 is an NMOS transistor. The output terminals of the drive control transistor M2 are also the source and drain of the NMOS transistor, and the driving terminal is the gate. When the drive signal D received by the gate of the drive control transistor M2 is at a high level, the source and drain of the NMOS transistor are conductive, and the light-emitting diode LED emits light. When the drive signal D received by the gate of the drive control transistor M2 is at a low level, the light-emitting diode LED is disconnected and does not emit light.
[0031] The drive control circuit also includes a constant current source module I2. The output of the driver control tube M2 is connected in series with the module. This module provides constant current drive for the LED. Optical fiber transmission data is represented by a high-frequency pulse signal, which is applied to the gate of the driver control tube M2. This high-frequency pulse signal controls the on and off of the LED. The LED emits a light pulse signal, which is transmitted via optical fiber to a signal receiver, which converts the light pulse signal into an electrical signal.
[0032] The charge discharge bypass includes a first branch and a second branch. The first branch is connected in parallel to the light-emitting diode (LED), and the second branch is connected in parallel to the drive control circuit. The first branch is turned on for a first predetermined time when the drive signal D jumps from a low level to a high level. The second branch is turned on for a second predetermined time when the drive signal D jumps from a high level to a low level. When the light-emitting diode (LED) is turned on, the first branch is controlled to be instantly connected to a low potential, quickly clearing the residual carriers at the end of the light-emitting diode (LED). After the first predetermined time, the first branch is disconnected to ensure normal driving of the light-emitting diode (LED). Similarly, when the light-emitting diode (LED) is turned off, the second branch is controlled to be instantly connected to a high potential, quickly clearing the residual carriers at the LED end, and then disconnected to ensure normal operation of the light-emitting diode (LED). Generally, if the drive signal D is a pulse signal of approximately 50MHz, the first predetermined time and the second predetermined time are both in the order of nanoseconds.
[0033] Those skilled in the art will appreciate that the disconnection and connection of the first branch and the second branch can be achieved by various types of electronic components, generally a switch tube, or other controllable circuit forms with a switch function.
[0034] In the embodiment, the switch tube is used to realize the function of connection and disconnection of the first branch and the second branch. The first branch comprises a first switch tube. The second branch comprises a second switch tube. Two output ends of the first switch tube are connected in parallel to the light emitting diode. Two output ends of the second switch tube are connected in parallel to the driving control circuit. The driving end of the first switch tube controls the conduction and disconnection of the first branch. The driving end of the second switch tube controls the conduction and disconnection of the second branch. The first switch tube and the second switch tube are different in type.
[0035] Further, as shown in the figure, Figure 2 the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube. The source of the first switch tube is connected to the anode of the light emitting diode LED, and the drain of the first switch tube is connected to the cathode of the light emitting diode LED. The drain of the second switch tube is connected to the drain of the driving control tube M2, and the source of the second switch tube is connected to the ground gnd.
[0036] When the light emitting diode LED is turned on, the second switch tube is controlled, that is, the pull-down NMOS tube is connected to the low potential instantaneously, and the remaining carriers at the light emitting diode LED end are quickly removed. After a very short time, the second switch tube is closed, so that the normal driving of the light emitting diode LED is ensured. Similarly, when the light emitting diode LED is turned off, the first switch tube is controlled, that is, the pull-up PMOS tube is connected to the high potential instantaneously, and the remaining carriers at the light emitting diode LED end are quickly removed. After the second switch tube is closed, the normal work of the light emitting diode LED is ensured.
[0037] Further, the utility model discloses a charge discharge bypass driving circuit. The input end of the charge discharge bypass driving circuit inputs a driving signal, and the first output end of the charge discharge bypass driving circuit is connected to the driving end of the first switch tube. The second output end of the charge discharge bypass driving circuit is connected to the driving end of the second switch tube. The output signals of the first output end and the second output end of the charge discharge bypass driving circuit are opposite. Through such a charge discharge bypass driving circuit, the conduction and disconnection of the first switch tube and the second switch tube can be automatically controlled synchronously according to the driving signal of the light emitting diode LED, so that the remaining carriers of the light emitting diode LED are quickly removed, and the normal work of the light emitting diode LED is ensured.
[0038] Figure 3 It is a schematic view of the charge discharge bypass driving circuit in the utility model embodiment. Figure 3 It is shown that one specific implementation of the charge discharge bypass driving circuit, as shown in the figure, Figure 3 the charge discharge bypass driving circuit comprises a PMOS tube driving circuit and an NMOS tube driving circuit.
[0039] The PMOS transistor drive circuit includes a first NAND gate 137, a first inverter 139, a second inverter 134, and a third inverter 135, which are connected in series. The input of the first inverter 139 is used to input a drive signal D. The common terminal of the first inverter 139 and the second inverter 134 is connected to the first input terminal of the first NAND gate 137. The output of the third inverter 135 is connected to the second input terminal of the first NAND gate 137. The common terminal of the second inverter 134 and the third inverter 135 is grounded via a delay capacitor C0. The output of the first NAND gate 137 outputs the PMOS transistor drive signal P_control.
[0040] The NMOS transistor drive circuit includes a second NAND gate I38 and a fourth inverter I36. A drive signal D is input to the first input of the second NAND gate I38. The common terminal of the second inverter I34 and the third inverter I35 is connected to the second input of the second NAND gate I38. The output of the second NAND gate I38 is connected to the input of the fourth inverter I36. The output of the fourth inverter I36 outputs the NMOS transistor drive signal N_control.
[0041] The PMOS drive signal P_control controls the pull-up PMOS transistor, while the NMOS drive signal N_control controls the pull-down NMOS transistor. Through the design of the PMOS drive signal P_control, when the signal at the drive signal terminal D jumps from a low level to a high level, the PMOS drive signal P_control becomes a low-level momentary pulse. This momentary pulse turns on the pull-up PMOS transistor, pulling the cathode voltage of the light-emitting diode (LED) to a high level, enabling rapid charge discharge. Similarly, when the signal at the drive signal terminal D jumps from a high level to a low level, the NMOS drive signal N_control becomes a high-level momentary pulse. This momentary pulse turns on the pull-down NMOS transistor, pulling the cathode voltage of the light-emitting diode (LED) to a low level, enabling rapid charge discharge.
[0042] like Figure 3 As shown, in Figure 3 In the circuit, the drive signal D is a data pulse signal. After passing through the first inverter I39, the drive signal D generates an inverted signal D_N. After passing through the second inverter I34, the inverted signal D_N has the same phase as the drive signal D. Due to the presence of a delay capacitor C0 connected to the ground terminal in the circuit, the secondary inverted signal D_N_N has a delay time Tdn compared to the drive signal D. After the drive signal D and the secondary inverted signal D_N_N pass through the second NAND gate I38 and the fourth inverter I36, they generate the NMOS tube drive signal N_control. This is a pulse signal with an extremely small pulse width, and the pulse width is determined by the capacitance value of the delay capacitor C0.
[0043] Similarly, the secondary reverse signal D_N_N is inverted by the third inverter I35 to form the tertiary reverse signal D_N_2, which has the same phase as the reverse signal D_N. There is a delay time Tdp between the two signals. After the reverse signal D_N and the tertiary reverse signal D_N_2 pass through the first NAND gate I37, they generate the PMOS transistor drive signal P_control. The PMOS transistor drive signal P_control is a pulse signal with an extremely small pulse width. The pulse width is determined by the capacitance value of the delay capacitor C0 and the gate delay of the second inverter I34.
[0044] In the embodiment of the present invention, the value range of the delay capacitor C0 is 0.5pf to 2pf, the pulse width range of the NMOS transistor driving signal N_control is 1ns to 10ns, and the pulse width range of the PMOS transistor driving signal P_control is 1ns to 10ns.
[0045] Figure 4 Schematic diagram of the waveform of the input signal and output signal of the charge discharge bypass driving circuit in the embodiment of the present utility model. The data rate of the driving signal D is 50Mbps. Figure 4 The first column of the graph is the output signal waveform of the light-emitting diode LED, the second column of the graph is the signal waveform of the NMOS tube drive signal N_control, and the third column is the signal waveform of the PMOS tube drive signal P_control. Figure 1 From the comparison with the prior art shown, it can be seen that the NMOS tube driving signal N_control and the PMOS tube driving signal help to quickly discharge the charge of the cathode of the light emitting diode LED, thereby ensuring high-speed transmission of optical fiber communication.
[0046] Figure 5 is the response waveform of the light emitting diode in the embodiment of the present utility model. Figure 5 As shown, typically, the rise time of the light emitting diode (LED) is 3ns to 10ns, and the fall time is 2ns to 10ns, which is significantly better than the existing technology.
[0047] Furthermore, based on the visible light fiber driver circuit disclosed in the embodiment of the present utility model, this embodiment also discloses a fiber optic transmission system, comprising: a fiber optic data transmission device, a transmission optical fiber, and a light signal receiver. The fiber optic data transmission device is used to load the drive signal to the driver end of the drive control tube. The transmission optical fiber is used to transmit the optical pulse signal emitted by the light-emitting diode. The light signal receiver is used to receive the optical pulse signal and convert it into an electrical signal.
[0048] Of course, those skilled in the art will know that the structure and installation method of the optical fiber data transmission device, the transmission light and the optical signal receiver itself are prior arts and are not within the scope of protection of the present invention, and will not be described in detail. This application significantly accelerates the transmission speed of the entire optical fiber transmission system by improving the structure of the visible light optical fiber driving circuit.
[0049] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.
Claims
1. A visible light fiber driving circuit, characterized in that: including an optical signal transmitting circuit and a charge discharge bypass; One end of the optical signal transmitting circuit is connected to a power supply, and the other end is grounded; the optical signal transmitting circuit includes a light-emitting diode and a drive control circuit connected in series; the drive control circuit includes a drive control tube; the drive end of the drive control tube is used to input a drive signal; The charge discharge bypass includes a first branch and a second branch; the first branch is connected in parallel to the light emitting diode, and the second branch is connected in parallel to the drive control circuit; The first branch is turned on for a first predetermined time when the driving signal jumps from a low level to a high level; the second branch is turned on for a second predetermined time when the driving signal jumps from a high level to a low level.
2. The visible light fiber driving circuit according to claim 1, characterized in that: The drive control circuit further includes a constant current source module; the output end of the drive control tube is connected in series with the constant current source module.
3. The visible light fiber driving circuit according to claim 1, wherein: The first branch includes a first switching tube; the second branch includes a second switching tube; the first switching tube and the second switching tube are of different types; the two output ends of the first switching tube are connected in parallel to the light-emitting diode; the two output ends of the second switching tube are connected in parallel to the drive control circuit; the drive end of the first switching tube controls the conduction and disconnection of the first branch; and the drive end of the second switching tube controls the conduction and disconnection of the second branch.
4. The visible light fiber driving circuit according to claim 3, characterized in that: The visible light fiber driving circuit further includes a charge discharge bypass driving circuit; an input end of the charge discharge bypass driving circuit inputs the driving signal, and a first output end of the charge discharge bypass driving circuit is connected to the driving end of the first switching tube; The second output terminal of the charge discharge bypass driving circuit is connected to the driving terminal of the second switch tube; the output signals of the first output terminal and the second output terminal of the charge discharge bypass driving circuit are in opposite directions.
5. The visible light fiber driving circuit according to claim 3, characterized in that: The first switch tube is a PMOS tube, and the second switch tube is an NMOS tube.
6. The visible light fiber driving circuit according to claim 5, characterized in that: The visible light fiber driving circuit further includes a charge discharge bypass driving circuit; the charge discharge bypass driving circuit includes a PMOS tube driving circuit and an NMOS tube driving circuit; The PMOS transistor drive circuit includes a first NAND gate, a first inverter, a second inverter, and a third inverter connected in series in sequence; the input end of the first inverter is used to input the drive signal; the common end of the first inverter and the second inverter is connected to the first input end of the first NAND gate; the output end of the third inverter is connected to the second input end of the first NAND gate; the common end of the second inverter and the third inverter is grounded via a delay capacitor; and the output end of the first NAND gate outputs the PMOS transistor drive signal; The NMOS transistor drive circuit includes a second NAND gate and a fourth inverter; the drive signal is input to the first input terminal of the second NAND gate; the common terminal of the second inverter and the third inverter is connected to the second input terminal of the second NAND gate; the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter; and the output terminal of the fourth inverter outputs the NMOS transistor drive signal.
7. The visible light fiber driving circuit according to claim 6, characterized in that: The value range of the delay capacitor is 0.5pf to 2pf; the pulse width range of the NMOS tube driving signal is 1ns to 10ns, and the pulse width range of the PMOS tube driving signal is 1ns to 10ns.
8. An optical fiber transmission system based on the visible light optical fiber driving circuit according to any one of claims 1 to 7, characterized in that: The optical fiber transmission system further comprises: An optical fiber data transmission device, used to load a driving signal to the driving end of the driving control tube; The transmission optical fiber is used to transmit the optical pulse signal emitted by the light emitting diode; the optical signal receiver is used to receive the optical pulse signal and convert the optical pulse signal into an electrical signal.