Semiconductor structure

Abstract

A semiconductor structure includes a first source / drain (S / D) epitaxial feature, a second S / D epitaxial feature adjacent to the first S / D epitaxial feature, an insulating structure between the first and second S / D epitaxial features, and a shared S / D contact on top surfaces of the first and second S / D epitaxial features. A central portion of the common S / D contact is located directly between a side surface of the first S / D epitaxial feature and a side surface of the second S / D epitaxial feature. And the central part is positioned right above the insulating structure. The semiconductor structure also includes a backside via passing through the insulating structure to directly fall on a bottom surface of the central portion.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure. Background Art

[0002] Embedded memory devices, such as static random access memory (SRAM), have become popular storage elements for high-speed communications, image processing, and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs continues to increase to meet the performance requirements of each new technology generation. Each new technology generation requires shrinking feature size while optimizing power consumption.

[0003] One advancement in SRAM technology is providing power connections to the backside of the SRAM device. In one case, the front-side power connections are moved to the backside. This provides better spacing management on the front side of the SRAM device. In another case, both front-side and back-side power connections are incorporated into the device structure. This dual-sided power configuration facilitates power optimization and power consumption. In some cases, dual-sided power configurations can reduce power consumption by more than 30%, resulting in better power efficiency.

[0004] To allow for backside power line connections, backside power vias are formed to electrically connect the source / drain components to the backside power lines. These backside power vias can be formed by etching backside trenches through the source / drain regions of the active area, and then forming metal vias in the trenches to land on the source / drain components. However, when the critical dimensions of the source / drain regions become too small, there is a risk of leakage through or failure to penetrate the source / drain regions when etching the trenches. Consequently, there is a risk of open circuits, and the size of the source / drain regions limits the process window.

[0005] Thus, while existing SRAM device structures are generally adequate for their intended purposes, they are not completely satisfactory in every respect. Utility Model Content

[0006] According to one embodiment of the present invention, a semiconductor structure includes a first source / drain (S / D) epitaxial component, a second S / D epitaxial component adjacent to the first S / D epitaxial component, an insulating structure between the first and second S / D epitaxial components, and a shared S / D contact located above the top surfaces of the first and second S / D epitaxial components. A central portion of the shared S / D contact is directly located between a side surface of the first S / D epitaxial component and a side surface of the second S / D epitaxial component. The central portion is directly above the insulating structure. The semiconductor structure also includes a backside via extending through the insulating structure and located directly on the bottom surface of the central portion.

[0007] According to another embodiment of the present invention, a semiconductor structure includes a first S / D epitaxial component over a first active region, a second S / D epitaxial component over a second active region adjacent to the first active region, an insulating structure between the first and second S / D epitaxial components, and a shared S / D contact over the top surfaces of the first and second S / D epitaxial components. A central portion of the shared S / D contact is directly located between a side surface of the first S / D epitaxial component and a side surface of the second S / D epitaxial component, wherein the central portion is directly over the insulating structure. The semiconductor structure also includes a backside via (BVV) having a first portion extending through the insulating structure and directly overlying the bottom surface of the central portion, a second portion extending through the first active region and directly overlying the first S / D epitaxial component, and a third portion extending through the second active region and directly overlying the second S / D epitaxial component.

[0008] According to yet another embodiment of the present invention, a semiconductor structure includes an S / D epitaxial wafer component above an active region, an S / D contact located above a top surface of the S / D epitaxial wafer component, wherein the S / D contact has a longitudinally extending extension extending beyond a sidewall of the S / D epitaxial wafer component. The semiconductor structure also includes an interlayer dielectric (ILD) layer surrounding the active region, the S / D epitaxial wafer component, and the S / D contact, and a backside via extending through the ILD layer and directly onto a bottom surface of the extension. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The details of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the drawings illustrate only typical embodiments of the present invention and, therefore, should not be considered limiting of the scope, as the present invention is equally applicable to other embodiments. Furthermore, the drawings may implicitly depict features that are not explicitly described in the detailed description.

[0010] Figure 1 A circuit diagram of a semiconductor device having an SRAM array according to an embodiment of the present disclosure is shown.

[0011] Figure 2 An embodiment of the present disclosure is shown. Figure 1 Top view of the frontside through-holes of a semiconductor device in the device layout.

[0012] Figure 3 An embodiment of the present disclosure is shown. Figure 1 Top view of backside vias in a semiconductor device device layout. Figure 3A Shown Figure 3 A portion of the device layout in the upper center view. Figure 3B Shown along Figure 3A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0013] Figure 4 Another embodiment of the present disclosure is shown. Figure 1 Top view of backside vias in a semiconductor device device layout. Figure 4A Shown Figure 4 A portion of the device layout in the upper center view. Figure 4B Shown along Figure 4A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0014] Figure 5 Another embodiment of the present disclosure is shown Figure 1 Top view of backside vias in a semiconductor device device layout. Figure 5A Shown Figure 5 A portion of the device layout in the upper center view. Figure 5B Shown along Figure 5A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0015] Figure 6A Shown Figure 5 A portion of a top view of the device layout is shown. Figure 6B Another embodiment according to the present disclosure is shown along Figure 6A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0016] Figure 7 Another embodiment of the present disclosure is shown. Figure 1 Top view of backside vias in a semiconductor device device layout. Figure 7A Shown Figure 7 Upper center view device layout. Figure 7B According to an embodiment of the present disclosure, Figure 7A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0017] Figure 8A Shown in different embodiments Figure 7 A portion of the device layout in the upper center view. Figure 8B According to an embodiment of the present disclosure, Figure 8A A cross-sectional view of the semiconductor device taken along line segment BB' in FIG.

[0018] Figure 9A Shown in different embodiments Figure 7 A portion of the device layout in the upper center view. Figure 9B According to an embodiment of the present disclosure, Figure 9Aa cross-sectional view of the semiconductor device taken along line B-B' in

[0019] Figure 10A different embodiments are shown Figure 7 a portion of an upper view device layout. Figure 10B a cross-sectional view of the semiconductor device taken along line B-B' in Figure 10A a cross-sectional view of the semiconductor device taken along line B-B' in DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and configurations are described herein to facilitate discussion of the present application. It should be understood by those skilled in the art, however, that these specific examples and configurations do not limit the present application. Indeed, any combination of these and / or other components described herein can be used to implement a variety of embodiments of the present application. For example, in the following description, formation of a first feature over or on a second feature can include embodiments where the first feature is formed directly on the second feature, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be directly in contact. In addition, the present application can repeat the use of reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "on", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] Still further, when a numerical value or numerical range is described herein using "about", "approximately", or the like, the term is intended to encompass numbers that are within a reasonable range given the description of the numerical value or numerical range, such as within ±10 of the described numerical value. A % of the described numerical value, or other value understood by one of skill in the art. For example, the term "about 5 nm" can encompass a range of sizes from 4.5 nm to 5.5 nm. Also, when comparing a size or dimension of one component to another component, the phrases "substantially the same", "essentially the same", "similar size", and the like, are to be understood as a difference between the compared components being within + / -10% of each other, or other value understood by one of skill in the art. Moreover, the dimensions of different components of the disclosure can implicitly disclose a ratio of the dimensions between the different components.

[0023] The present disclosure relates to a semiconductor device having a backside via, and more particularly, to a static random access memory (SRAM) semiconductor device having a backside power via located above a source / drain contact.

[0024] An SRAM device is a semiconductor memory that uses a bistable latch circuit (e.g., a flip-flop) to store binary information bits. The semiconductor device may include an SRAM array comprising a plurality of SRAM cells, each cell having a plurality of metal wirings, the metal wirings including power lines connected to a power source or ground. These power lines are electrically connected to the source / drain components, and they provide routing for the power pull-up and pull-down transistors of the SRAM device. In order to locate these power lines on the back side of the SRAM device, back side power vias are formed from the back side to be electrically connected to the source / drain components. However, as the size of the transistor active area continues to decrease, forming a back side power via that falls on the back side of the source / drain components becomes more difficult. Specifically, when the critical dimensions of the active area (particularly the source / drain region of the active area) become too small, there is a risk of leakage through or failure to penetrate the active area from the back side. In addition, even if the back side power via is successfully formed, the width of the back side power via is limited by the width of the active area.

[0025] The present disclosure proposes a backside via solution that is independent of the critical dimension of the active area. The present disclosure contemplates bonding the backside via to the backside of the source / drain contact, rather than bonding the backside via to the backside of the source / drain component. The source / drain contacts are already formed on the front side of the source / drain component. Therefore, the backside via can be electrically connected to the source / drain component by landing on the source / drain contact. In this way, the backside via can be formed to be larger than the critical dimension of the active area, thereby avoiding process window concerns. In addition, by increasing the size of the backside via and by directly contacting the source / drain contact, the contact resistance of the SRAM device can be significantly reduced, thereby improving SRAM speed and performance.

[0026] The embodiments of the present disclosure can be implemented using planar transistors, FinFET transistors, or gate-all-around (GAA) transistors. A GAA transistor refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as a vertically stacked gate wrapped around a horizontal nanowire or nanosheet MOSFET device. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other structures to achieve the same objectives and / or achieve the same advantages as the embodiments described herein.

[0027] Figure 1A circuit diagram of a semiconductor structure 100 having an SRAM array 102 according to an embodiment of the present disclosure is shown. The semiconductor structure 100 has a corresponding semiconductor structure, and the two terms (i.e., device and structure) can be used interchangeably. The SRAM array 102 includes four SRAM cells 104a, 104a', 104b, and 104b'. Each of the four SRAM cells is formed by six transistors (two pull-down transistors, two pull-up transistors, and two pass-gate transistors). Each SRAM cell stores a memory bit through the pull-down and pull-up transistors, and the SRAM cells are addressed by word lines and bit lines through the pass-gate transistors.

[0028] SRAM cell 104a includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass-gate transistors PG1 and PG2. The sources of PU1 and PU2 are coupled together and connected to a high voltage Vdd. The sources of PD1 and PD2 are coupled together and connected to a low voltage Vss or ground. The gates of PU1 and PD1 are coupled together and connected to the common drain of PU2, PD2, and PG2. The gates of PU2 and PD2 are coupled together and connected to the common drain of PU1, PD1, and PG1. PU1, PU2, PD1, and PD2 form a first set of cross-coupled inverters to store data bits. The source of PG1 is connected to a first bit line BL1, and the source of PG2 is connected to a first bit line bar BLB1. The gates of PG1 and PG2 are connected to a first word line WL_A.

[0029] SRAM cell 104b includes pull-up transistors PU3 and PU4, pull-down transistors PD3 and PD4, and pass-gate transistors PG3 and PG4. The sources of PU3 and PU4 are coupled together and connected to a high voltage Vdd. The sources of PD3 and PD4 are coupled together and connected to a low voltage Vss or ground. The gates of PU3 and PD3 are coupled together and connected to the common drain of PU4, PD4, and PG4. The gates of PU4 and PD4 are coupled together and connected to the common drain of PU3, PD3, and PG3. PU3, PU4, PD3, and PD4 form a second set of cross-coupled inverters to store data bits. The source of PG3 is connected to the same first bit line BL1, and the source of PG4 is connected to the same first bit line bar BLB1. The gates of PG3 and PG4 are connected to a second word line WL_B.

[0030] The configuration of SRAM cells 104a' and 104b' is similar to that of corresponding SRAM cells 104a and 104b. SRAM cell 104a' includes pull-up transistors PU1' and PU2', pull-down transistors PD1' and PD2', and pass-gate transistors PG1' and PG2'. SRAM cell 104b' includes pull-up transistors PU3' and PU4', pull-down transistors PD3' and PD4', and pass-gate transistors PG3' and PG4'. For the sake of brevity, similar configurations and connections will not be repeated. SRAM cells 104a' and 104b' include third and fourth groups of cross-coupled inverters, each inverter storing one data bit. The sources of PG1' and PG3' are connected to the second bit line BL2. The sources of PG2' and PG4' are connected to the second bit line bar BLB2. SRAM cell 104a′ shares the same first word line WL_A as SRAM cell 104a, and SRAM cell 104b′ shares the same second word line WL_B as SRAM cell 104b. That is, the gates of pass-gate transistors PG1′ and PG2′ are also connected to the first word line WL_A, and the gates of pass-gate transistors PG3′ and PG4′ are also connected to the second word line WL_B.

[0031] It should be noted that Figure 1 An exemplary embodiment of an SRAM array 102 is shown, but other configurations are also possible. For example, in other embodiments, the source and drain nodes of different pull-up and pull-down transistors can be flipped. In addition, the Vdd and Vss nodes can also be flipped. In other words, in some embodiments, a high voltage Vdd can be connected to the source or drain of any one of the pull-up and pull-down transistors of the SRAM array 102. And in other embodiments, a low voltage Vss or ground can be connected to the source or drain of any one of the pull-up and pull-down transistors of the SRAM array 102. Therefore, the electrical connections to Vdd and to Vss are referred to herein as power lines or power line connections that provide wiring to the power pull-up and pull-down transistors of the SRAM device 100.

[0032] Figure 2A top view device layout 202 showing the front side vias 112 (and other components) of the semiconductor structure 100 is shown. The device layout 202 includes SRAM cells 104a, 104a', 104b, and 104b' defined by dashed cell boundaries. The SRAM cells 104a and 104a' are adjacent to each other in the x-direction and are mirrored across the vertical cell boundary therebetween. The SRAM cells 104b and 104b' are adjacent to each other in the x-direction and are mirrored across the vertical cell boundary therebetween. The SRAM cells 104a and 104b' are adjacent to each other in the y-direction and are mirrored across the horizontal cell boundary therebetween. The SRAM cells 104a' and 104b' are adjacent to each other in the y-direction and are mirrored across the horizontal cell boundary therebetween.

[0033] Figure 2 The location of each transistor PU1, PU1', PU2, PU2', PU3, PU3', PU4, PU4', PD1, PD1', PD2, PD2', PD3, PD3', PD4, PD4', PG1, PG1', PG2, PG2', PG3, PG3', PG4 and PG4' is shown (labeled on the gate 108 of each transistor). How each transistor is connected to each other has been described in detail. Figure 1 , and will not be repeated here for the sake of brevity.

[0034] The device layout 202 includes several active areas 106 extending along the y-direction on the front side of the structure 100. The active area 106 can be configured as a planar, fin-type, or gate-all-around semiconductor structure. In one embodiment, the active area 106 is a fin structure protruding from the base substrate along the positive z-direction. Some of the several active areas 106 can extend longitudinally across the horizontal cell boundary and can share the same active area across SRAM cells. Several gates 108 are arranged above the channel region of the active area 106. The channel region (or transistor channel) refers to the portion of the active area 106 directly below the gate 108. The gate 108 extends longitudinally in the x-direction. Some of the several gates 108 can extend across the vertical cell boundary to span the active areas of different SRAM cells. Several source / drain (S / D) contacts 110 are arranged above the S / D regions of the active area 106, some of which can couple the S / D regions of different transistors together. The S / D regions may refer to the source or drain individually or collectively to the source and drain, depending on the context.

[0035] Several front side vias 112 are each coupled to one of the gate 108, active area 106, or S / D contact 110. These vias 112 allow the gate 108, active area 106, or S / D contact 110 to be electrically coupled to a higher material layer in the z direction. Figure 2 , each via 112 is labeled with the name of the node that it is part of. For example, a front-side via 112 that is part of a low voltage Vss or ground node is labeled "Vss" on its side (also referred to as a Vss front-side via 112), and a front-side via 112 that is part of a high voltage Vdd node is labeled "Vdd" on its side (also referred to as a Vdd front-side via 112). In this embodiment, the front-side vias 112 that are part of WL_A, WL_B, BL1, BL2, BLB1, BLB2, Vss, and Vdd are located on the front side of the semiconductor structure 100.

[0036] In this embodiment, there are also eight gate-to-drain contacts 114 that couple the gate 108 to the S / D contacts 110. The gate-to-drain contacts 114 are also referred to as butted contacts. In one embodiment, the interconnection between the drain (or source) and the gate is achieved using local interconnect (LI) technology. For example, the local interconnect is formed using gate electrode material, such as polysilicon, metal, or other conductive material for the gate electrode. In this case, polysilicon (metal or other conductive material) is used to form not only the gate electrode but also the interconnect. More specifically, the gate electrode extends to and lands directly on the target drain (or source) region. In another example, the butted contacts 114 are elongated contacts oriented along the y-direction and are formed simultaneously with other contacts (e.g., long contacts) during the same process, including dielectric deposition, patterning, and metal deposition.

[0037] Figure 3 Shown is the display Figure 1 A top view of the backside via 113 (and other components) of the semiconductor structure 100 in the device layout 202 is shown. Figure 3 and Figure 2 Correspondingly, for the sake of brevity, similar components will not be repeated. The difference is that, Figure 3 The backside via 113 is shown and filtered out Figure 2 The front side vias 112 and gate to drain contacts 114 in FIG. 1 (for simplicity). Figure 3, each backside via 113 is labeled with the name of the node that the corresponding via is a part of. As shown, the backside via 113 that is part of the low voltage Vss or ground node is labeled "Vss" on its side (also referred to as Vss backside via 113). In this embodiment, the backside via 113 is located on the back side of the semiconductor structure 100 opposite the front side of the semiconductor structure 100. The Vss backside via 113 provides a backside power line connection to the pull-down transistor and can be connected to power or ground. In one embodiment, the semiconductor structure 100 may include a Vss backside via 113 and a Vss frontside via 112 for a dualside power configuration (see Figure 2 ).

[0038] Figure 3 A solid black frame 100 a in the middle region of the four SRAM cells is shown to highlight a portion of the semiconductor structure 100 having the Vss backside vias 113 . Figure 3A Shown Figure 3 The solid black frame 100a in FIG. Figure 3B Shown along Figure 3A The cross-sectional view of the semiconductor device structure corresponding to the solid black frame 100 a is taken along line segment BB′ in FIG.

[0039] Now refer to Figure 3A , a shared S / D contact 110 is disposed above adjacent active regions 106. The adjacent active regions 106 may be fin active regions in separate SRAM cells, and each fin active region 106 extends longitudinally in the y-direction. The gate 108 extends longitudinally in the x-direction and is directly located on the channel region of the fin active region 106. The gate 108 may include a gate spacer on the sidewall of the gate electrode (not shown). The gate spacer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or an appropriate dielectric material. The shared S / D contact 110 extends longitudinally in the x-direction and is directly located on the S / D region of the fin active region 106. The Vss back side via 113 falls directly on the back side of the shared S / D contact 110 and is disposed between two adjacent fin active regions 106. The purpose of the Vss back side via 113 is to electrically connect to the S / D component 106a (see Figure 3B This can be achieved by penetrating the fin active area 106 from the back side (not shown) to directly contact the S / D components 106a, or by penetrating the gate insulating structure 111 from the back side to directly contact the shared S / D contact 110 (e.g. Figure 3B shown).

[0040] refer to Figure 3A, the active area 106 has a width x1 in the x-direction, and the Vss back via 113 has a via length v1 in the x-direction. In the embodiment, the width x1 and the via length v1 have similar dimensions. For example, x1 and v1 are both approximately 10 nm, so that the ratio of v1 to x1 is approximately 1. Although the active area 106 and the Vss back via 113 have similar dimensions along the x-direction, by bonding the Vss back via 113 on the back side of the shared S / D contact 110, overlay control and process window are improved. This is because the Vss back via 113 will no longer be limited to the precise location of the fin active area 106, where any misalignment will result in overlay offset and insufficient landing. In other words, the position of the Vss back via 113 is relocated between the fin active areas 106, rather than having to penetrate the back side of the fin active area 106, thereby achieving overlay improvement.

[0041] Still refer to Figure 3A The gate 108 has a width y1 in the y-direction, the shared S / D contact 110 has a width y2 in the y-direction, and the VSS backside via 113 has a via width v2 in the y-direction. In one embodiment, the ratio of the via width v2 to the width y1 is in a range from approximately 0.3 to approximately 2. In one embodiment, the ratio of the via width v2 to the width y2 is in a range from approximately 0.5 to approximately 2. To improve surface contact, in this embodiment, the via width v2 can be approximately equal to or greater than the width y2. For example, the ratio of the via width v2 to the width y2 is approximately equal to or greater than 1. Two adjacent active areas 106 are separated by a spacing s1, and the spacing s1 is greater than the width x1. The shared S / D contact 110 spans the spacing s1 and extends beyond the outer surfaces of the active areas 106 on either side. In other words, the length of the shared S / D contact 110 in the x-direction is greater than 2 times x1 plus s1. In one embodiment, the ratio of the spacing s1 to the width x1 is in a range from 4 to 5.

[0042] Now refer to Figure 3B , showing Figure 3A Cross-sectional view along the dotted line BB'. Figure 3A The components described in Figure 3B are similarly labeled. Figure 3A The same applies to Figure 3B . Please note that there is also Figure 3B Shown in but not in Figure 3A As previously mentioned, the active area 106 can be a fin-type active area protruding from the substrate (not shown). After processing from the back side, the substrate can be thinned from the back side, leaving only part of the fin-type active area 106. In this way, Figure 3BThe portion of the remaining fin active area 106 surrounded by an isolation structure 107 (such as a shallow isolation structure STI) is shown. In this cross-section, these remaining fin active areas 106 are the S / D regions of the fin active areas 106. The isolation structure 107 provides isolation between the fin active areas 106 and can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In some embodiments, above the isolation structure 107 is a fin spacer 109 having a composition similar to the gate spacer described above.

[0043] Still refer to Figure 3B , S / D features 106a are disposed above the S / D regions of the fin active area 106. The S / D features 106a can be epitaxially grown from the top surface of the S / D regions using a suitable epitaxial growth technique. In the embodiment shown, the S / D features 106a are n-type S / D features for pull-down transistors, and they can be doped with n-type dopants such as phosphorus or arsenic. Each S / D feature 106a can be lined with a front-side silicide layer 116. Respective front-side silicide layers 116 are disposed above respective top surfaces of the S / D features 106a, and they connect between the epitaxial features of the S / D features 106a and the shared S / D contact 110. The front-side silicide layer 116 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0044] Still refer to Figure 3B , an S / D contact 110 (corresponding to the above-mentioned shared S / D contact 110) is provided above the top surface of the first S / D component 106a and the adjacent second S / D component 106a. The S / D contact 110 may fall directly on each of the first and second S / D components 106a or on the front side silicide layer 116 on the first and second S / D components 106a. The central portion of the shared S / D contact 110 is directly located between the side surface of the first S / D component 106a and the side surface of the second S / D component 106a. The central portion is located directly above the gate insulating structure 111 (also referred to as a cut metal gate component), and the central portion extends downward to fall on the gate insulating structure 111. The central portion has a greater depth in the z-direction than the portion of the S / D contact 110 directly above the first and second S / D components 106a. The gate insulating structure 111 is a dielectric component extending in the y-direction that cuts through the metal gate structure to form different gates 108 (see Figure 3AThe gate insulating structure 111 includes a material similar to that of the isolation structure 107 .

[0045] Still refer to Figure 3B , backside vias 113 (corresponding to the aforementioned Vss backside vias 113) directly extend onto the backside of the shared S / D contact 110. As shown, backside vias 113 may extend directly onto the bottom surface of the central portion of the shared S / D contact 110. Backside vias 113 penetrate the gate insulation structure 111 from the backside and are disposed between the S / D components 106a and between the S / D regions of the fin active area 106. Backside vias 113 may also penetrate other components (e.g., the etch stop layer 129 and / or the liner barrier layer 117 described below).

[0046] Still refer to Figure 3B The various components described may be surrounded by one or more interlayer dielectric (ILD) layers 115a and 115b. The ILD layers 115a and 115b include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. In one embodiment, the ILD layers 115a and 115b include silicon oxide or a low-k dielectric material. The ILD layers 115a and 115b may be lined with various liner barrier layers 117 at the interface between the ILD layers and the various components described (e.g., the shared S / D contact 110, the S / D component 106a, the fin spacer 109, the isolation structure 107, the gate insulation structure 111, and the backside via 113). The liner barrier layers 117 may conformally line these components and may include a dielectric material, such as silicon nitride, which may act as an etch stop film. In one embodiment, the liner barrier layer 117 comprises a different dielectric material than the ILD layers 115 a and 115 b for etchant selectivity. After the backside thinning process, an additional etch stop layer 129 may be deposited on the backside of the semiconductor device. The etch stop layer 129 is a dielectric layer and may be a planar silicon nitride layer that is in direct contact with the ILD layer 115 a, the liner barrier layer 117, the isolation structure 107, the fin active area 106, and the backside via 113. In one embodiment, the ILD layers 115 a and 115 b comprise a different material composition than the isolation structure 107 and the gate insulation structure 111 for etchant selectivity.

[0047] Still refer to Figure 3B, backside vias 113 land directly on backside via rails 130 for further electrical routing on the backside of the semiconductor device. If used in a dual-sided power configuration, frontside vias 112 can directly bond to the front side of shared S / D contacts 110, and frontside via rails 120 directly bond to frontside vias 112 for further electrical routing on the front side of the semiconductor device. In this case, frontside vias 112 and backside vias 113 are located on opposite sides of shared S / D contacts 110. Frontside vias 112 can be surrounded by an ILD layer 115c, frontside via rails 120 can be surrounded by an ILD layer 115d, and backside via rails 130 can be surrounded by an ILD layer 115e. ILD layers 115c, 115d, and 115e can have similar material compositions as ILD layers 115a and 115b. Although not shown, the ILD layers 115 c , 115 d , and 115 e may also be lined with a liner barrier layer 117 .

[0048] Figure 4 Another embodiment showing a backside via 113 in a top view device layout 202 of the semiconductor structure 100 is shown. Figure 4 and Figure 3 Similarly, similar components will not be repeated for the sake of brevity. The difference is that the size of the back through hole 113 is larger in the x direction. Figure 4 A solid black frame 100 b in the middle region of the four SRAM cells is shown to highlight a portion of the semiconductor structure 100 having the Vss backside vias 113 . Figure 4A Shown Figure 4 The solid black box 100b in FIG. Figure 4B Shown along Figure 4A The cross-sectional view of the semiconductor device structure corresponding to the solid black frame 100 b is taken along line segment BB′ in FIG.

[0049] refer to Figure 4A , the active area 106 has a width x1 in the x-direction, and the Vss back via 113 has a via length v1 in the x-direction. In the embodiment, the via length v1 is greater than the width x1. For example, the ratio between the via length v1 and the width x1 is in the range of 1.5 to 4. In this embodiment, the via length v1 is not limited by the width x1 of the active area 106, but is limited by the gate spacing spacing between the gates 108 along the x-direction (for example, the spacing between the gate 108 for PD1 and the gate 108 for PD1'). In one embodiment, the width x1 is about 10 nm and the via length v1 is about 15 nm to about 40 nm. Similar to Figure 3A By bonding the Vss backside via 113 to the backside of the shared S / D contact 110, the overlap control and process window are improved. Figure 4A Additional benefits are demonstrated because a longer via length v1 can achieve better via penetration and reduce contact resistance. For example, by increasing the via length v1 to be longer than the width x1, the contact resistance can be reduced by more than 50%, depending on the amount of via length increase.

[0050] Still refer to Figure 4A , the gate 108 has a width y1 in the y direction, the shared S / D contact 110 has a width y2 in the y direction, and the Vss backside via 113 has a via width v2 in the y direction. Two adjacent active areas 106 are separated by a spacing s1, and the spacing s1 is greater than the width x1. These dimensions and other related components are similar to Figure 3A The description is similar. For the sake of brevity, similar components will not be repeated. Note that although the length v1 is now greater than the width x1, in one embodiment, the length v1 is still less than the spacing s1. This is because the gate separation spacing along the x-direction between the gates 108 (which may limit the length v1) can be less than the spacing s1 between two adjacent active regions 106.

[0051] Now refer to Figure 4B , showing Figure 4A Cross-sectional view along the dotted line BB'. Figure 4A The components described in Figure 4B are similarly labeled. Figure 4A The same applies to Figure 4B . Please note that there is also Figure 4B Shown but not in Figure 4A Additional components shown in .

[0052] Figure 4B and Figure 3B Similarly, for the sake of brevity, similar parts will not be repeated. The difference is that the back through hole 113 is Figure 3BIn contrast, it is larger in the x-direction. As previously described, the backside via 113 is located directly behind the shared S / D contact 110. The backside via 113 penetrates the gate insulation structure 111 from the back side and is disposed between the S / D components 106a and the S / D regions of the fin active area 106. In one embodiment, the length of the backside via 113 (i.e., v1) is limited by the width of the gate insulation structure 111 along the x-direction. As described above, the width of the gate insulation structure 111 can define the gate separation spacing between the gates 108. In some embodiments, more than 70% of the gate insulation structure 111 is etched away along the x-direction and between the S / D components 106a as part of forming the backside via 113. As such, the backside via 113 can substantially span the width of the gate insulation structure 111, such that the ratio of the via length v1 to the width of the gate insulation structure 111 along the x-direction can be greater than 0.7 (e.g., 0.9).

[0053] Figure 5 Another embodiment of a backside via 113 in a top view device layout 202 of the semiconductor structure 100 is shown. Figure 5 and Figure 3 Similarly, similar components will not be repeated for the sake of brevity. The difference is that the backside vias 113 are slot vias extending between and above the fin active areas 106. Therefore, the backside vias 113 are even larger than the backside vias 113 in the x-direction. Figure 4 、 Figure 4A and Figure 4B The embodiment shown is larger. Figure 5 A solid black frame 100 c in the middle region of the four SRAM cells is shown to highlight a portion of the semiconductor structure 100 having the Vss backside vias 113 . Figure 5A Shown Figure 5 The solid black frame 100c in FIG. 1 and Figure 5B Shown along Figure 5A The cross-sectional view of the semiconductor device structure corresponding to the solid black frame 100 c is taken along line segment BB′ in FIG.

[0054] refer to Figure 5A , the active areas 106 have a width x1 and are spaced apart from each other by a spacing s1. The width x1 and the spacing s1 are in the x-direction. In this embodiment, the Vss backside via 113 has a via length v1 that is approximately equal to the spacing s1 plus twice the width x1. In other words, the Vss backside via 113 spans between the outer sides of two adjacent active areas 106. The dimensions of x1 and s1 have been described previously and are also applicable. Figure 5AIn one embodiment, the ratio between the via length v1 and the width x1 may be in the range of about 6 to 7. In one embodiment, the width x1 is about 10 nm, the spacing s1 is about 45 nm, and the via length v1 is about 65 nm. Figure 3A By bonding the Vss backside via 113 to the backside of the shared S / D contact 110, the overlap control and process window are improved. Figure 5A shows additional benefits because the via length v1 is even greater than Figure 3A and Figure 4A In the embodiment. Figure 5A The embodiments further reduce the contact resistance while providing a greater margin for error. In one embodiment, forming the Vss backside via 113 as a slit via (as shown) can reduce the contact resistance by up to 90% compared to when the via length v1 is approximately equal to the width x1.

[0055] Still refer to Figure 5A , the gate 108 has a width y1 in the y direction, the shared S / D contact 110 has a width y2 in the y direction, and the Vss backside via 113 has a via width v2 in the y direction. These dimensions and other related components are consistent with those of reference Figure 3A For the sake of brevity, similar parts will not be repeated.

[0056] Now refer to Figure 5B , showing Figure 5A Cross-sectional view along the dotted line BB'. Figure 5A The components described in Figure 5B are similarly labeled. Figure 5A The same applies to Figure 5B . Please note that there is also Figure 5B Shown but not in Figure 5A Additional components shown in .

[0057] Figure 5B and Figure 4B Similarly, for the sake of brevity, similar components will not be repeated. The difference lies in the backside via 113, which has a trident shape and includes three penetrating portions 113a, 113b, and 113c. As shown in the figure, the backside via 113 has a first portion 113a that penetrates the gate insulating structure 111 from the back side. The first portion 113a falls on the back side of the shared S / D contact 110. This corresponds to Figure 4B However, in Figure 5BIn the embodiment, the backside via 113 further includes a second portion 113b extending through the first active region 106 from the back side, and a third portion 113c extending through the second active region 106 from the back side. The second portion 113a and the third portion 113c penetrate the source / drain regions of the active region 106 and directly land on the corresponding S / D features 106a. Because the second and third portions 113a and 113c land on the S / D features 106a, each S / D feature 106a may also be lined with a backside silicide layer 216. The respective backside silicide layers 216 are disposed above the respective bottom surfaces of the S / D features 106a. The backside silicide layers 216 may comprise a material similar to that of the frontside silicide layer 116 and form an interface between the epitaxial features of the S / D features 106a and the backside via 113. The width of the first portion 113a along the x-direction may be greater than the widths of the second portion 113b and the third portion 113c. This is because the widths of the second portion 113b and the third portion 113c are limited by the width x1 of the active region 106, while the width of the first portion 113a is limited by the spacing between adjacent S / D components 106a (e.g., the width x1 of the gate insulation structure 111), and the spacing between adjacent S / D components 106a is greater than the width x1 of the active region 106.

[0058] Still refer to Figure 5B The back through hole 113 further includes a horizontal fourth portion 113d connecting the first portion 113a, the second portion 113b and the third portion 113c. The horizontal fourth portion 113d spans a length v1 (see Figure 5A ) and penetrates the etch stop layer 129. The horizontal fourth portion 113d penetrates to a depth less than the depths of the first, second, and third portions 113a, 113b, and 113c. As such, the first portion 113a, the second portion 113b, and the third portion 113c are laterally spaced apart from one another in the x-direction. For example, as shown, the first portion 113a, the second portion 113b, and the third portion 113c are interposed by various dielectric components (e.g., the isolation structure 107, the liner barrier layer 117, and the ILD layer 115a).

[0059] Figures 6A-6B Another embodiment of the present disclosure is shown, which shows a backside through hole 113, wherein the backside through hole 113 is a slot. Figure 6A and Figure 5A The same, because from the top view, each back through hole 113 looks the same. Therefore, the features described will not be repeated. Figure 6B , showing Figure 6A Cross-sectional view along the dotted line BB'. Figure 6A The components in Figure 6B are similarly labeled. Figure 6A The same applies to Figure 6B Note that additional components are also present in Figure 6B but not shown in Figure 6A .

[0060] Figure 6B Similar to Figure 5B , for brevity, similar components will not be repeated. The difference is the backside via 113, which does not have a trifurcated shape as in Figure 5B . This is because in Figure 6B , the backside via 113 penetrates various intervening dielectric components (e.g., isolation structure 107, spacer barrier 117, and ILD layer 115a) such that there is no lateral distance between the portion of the backside via 113 that penetrates the active region 106 and the portion of the backside via 113 that penetrates the gate insulating structure 111. In the illustrated embodiment, the backside via 113 includes an upwardly extending ramp. The ramp extends upwardly along a sidewall surface of the S / D component 106a to a top surface of the backside via 113, where the top surface directly contacts the shared S / D contact 110. Described in another way, with reference to Figure 5B , Figure 6B , the ramp can extend from the top surfaces of the second and third portions 113b, 113c to the top surface of the first portion 113a. Since the ramp can also directly contact a sidewall surface of the S / D component 106a, a corresponding backside silicide layer 216 can further extend along the ramp. In the illustrated embodiment, all portions of the backside via 113 minimally penetrate the depth of the active region 106.

[0061] Figure 7 An upper view device layout 202 showing the backside via 113 (and other components) of the semiconductor structure 100 in Figure 1 is shown in accordance with another embodiment of the present disclosure. Figure 7 An upper view device layout 202 similar to that shown in Figure 3 , Figure 4 , and Figure 5 is shown, and for brevity, similar components will not be repeated.

[0062] Figure 7 Multiple S / D contacts 110 are shown falling on source / drain regions of the active region 106. Some of these S / D contacts 110 fall on the active region 106 for various pull-up transistors (i.e., pull-up transistors PU1-PU4 and PU1'-PU4'). Similar to Figure 3 , Figure 4 , and Figure 5Compared to the corresponding S / D contacts 110 in FIG. 1 , these S / D contacts 110 extend longer in the x-direction to prepare for backside bonding of backside vias 113 (i.e., Vdd backside vias 113). These S / D contacts 110 (now referred to as extended S / D contacts 110) can span the distance between two adjacent active regions 106 along the x-direction and the space therebetween.

[0063] Still refer to Figure 7 , the device layout 202 includes a Vss back side via 113 and a Vdd back side via 113. The Vss back side via 113 provides a back side power line connection to the pull-down transistor, and the Vdd back side via 113 provides a back side power line connection to the pull-up transistor. In one embodiment, the Vss back side via 113 is electrically connected to ground and the Vdd back side via 113 is electrically connected to power. In another embodiment, the Vss back side via 113 is electrically connected to power and the Vdd back side via 113 is electrically connected to ground. The semiconductor structure 100 may include Vss and Vdd back side vias 113 and Vss and Vdd front side vias 112 for a dual side power configuration (see Figure 2 ). It should be noted that in Figure 7 In the embodiment shown, Figure 3 、 Figure 4 and Figure 5 Unlike the illustrated embodiment, the Vss backside vias 113 do not land on the S / D contacts 110. Instead, they are located directly below the corresponding active regions 106, and they penetrate the active regions 106 from the backside to land on the S / D features 106a.

[0064] Figure 7 A solid black frame 500 a in the middle region of the four SRAM cells is shown to highlight a portion of the semiconductor structure 100 having the Vss and Vdd backside vias 113 . Figure 7A Shown Figure 7 The solid black frame 500a in FIG. 1 and Figure 7B Shown along Figure 7A The cross-sectional view of the semiconductor device structure corresponding to the solid black frame 500a is taken along line segment BB′ in FIG.

[0065] refer to Figure 7A , showing a plurality of Vdd backside vias 113. The purpose of the Vdd backside vias 113 is to electrically connect to the S / D components 106b from the backside of the semiconductor structure 100 (see Figure 7B This can be achieved by penetrating the fin active area 106 from the back side (not shown) to directly contact the S / D component 106b, or by penetrating the ILD layer 115a from the back side to directly contact the extended S / D contact 110 (e.g., Figure 7BIn the embodiment shown, the Vdd backside via 113 lands directly on the backside of the extended S / D contact 110 while being spaced apart from the adjacent fin active area 106 .

[0066] Still refer to Figure 7A , the active regions 106 have a width x1 and they are separated from each other by a spacing s1. Figure 7A The spacing s1 is shown to have different lengths between different groups of adjacent active areas 106. However, in other embodiments, the spacing s1 can be constant across all active areas 106. For example, the spacing s1 between any two adjacent active areas 106 is approximately 45 nm. The width x1 and the spacing s1 are in the x-direction. As shown, a shared S / D contact 110 routed to Vss is sandwiched between two extended S / D contacts 110 routed to Vdd. The shared S / D contacts 110 have been described previously and will not be repeated. Although not shown or drawn to scale, the extended S / D contacts 110 can span a similar length as the shared S / D contacts 110. As shown, the extended S / D contacts 110 can span the spacing s1 and extend beyond the outer surfaces of the adjacent active areas 106 on both sides. In other words, the length of the extended S / D contacts 110 in the x-direction is greater than twice x1 plus s1. In one embodiment, the lengths of both the shared S / D contacts 110 and the extended S / D contacts 110 in the x-direction are greater than 60 nm.

[0067] Still refer to Figure 7A Each extended S / D contact 110 has an extended portion that extends in the x-direction across the separation distance in the y-direction. The separation distance is the gap between two active areas 106 in the y-direction. As shown, each extended portion can extend beyond the outer surface of the corresponding two active areas 106. In other words, each extended S / D contact 110 is directly located between the two active areas 106 along the y-direction. As shown, the Vdd backside via 113 can then be located on the extended portion of the extended S / D contact 110.

[0068] In the embodiment shown, the Vss backside via 113 has a via length v1 in the x-direction and a via width v2 in the y-direction. In this embodiment, the via length v1 is limited by the width x1 of the active area. As such, the via length v1 can be approximately the same as the width x1. The via width v2 has been previously described and is equally applicable here. Figure 7A , the Vdd backside via 113 has a via length v3 in the x-direction and a via width v4 in the y-direction. In the embodiment shown, the via length v3 is equal to or greater than the width x1. For example, the ratio between the via length v3 and the width x1 is in a range of 1 to 4. The via width v4 can be similar to the via width v2 described previously.

[0069] Still refer to Figure 7A , by having the Vdd backside via 113 bonded to the backside of the extended S / D contact 110, overlap control and process window are improved. This is because the Vdd backside via 113 will no longer be limited to the precise location of the fin active area 106, where any misalignment will result in overlap shift and insufficient landing. In other words, the position of the Vdd backside via 113 is repositioned adjacent to and away from the fin active area 106, rather than having to penetrate the backside of the fin active area 106, thereby achieving overlap improvement. In addition, this configuration demonstrates additional benefits by allowing a larger via length v3 for better via penetration and reduced contact resistance. For example, by increasing the via length v3 to be longer than the width x1, the contact resistance can be reduced by more than 50%, depending on the amount of via length increase.

[0070] Now refer to Figure 7B , showing Figure 7A Cross-section through the dashed line BB'. Figure 7A The components described in Figure 7B are similarly labeled. Figure 7A The same applies to Figure 7B . Please note that there is also Figure 7B Shown in but not in Figure 7A Additional components shown in . Figure 7B Including previous Figure 3B 、 Figure 4B 、 Figure 5B and Figure 6B For the sake of brevity, identical components will not be described again. For the purpose of distinction, the backside via 113 connected to the Vdd power line is referred to as the Vdd backside via 513, and the backside via 113 connected to the Vss power line is referred to as the Vss backside via 713a. The Vdd backside via 513 corresponds to Figure 7A The Vdd backside via 113 in the embodiment and the Vss backside via 713a correspond to Figure 7A Vss backside via 113 in.

[0071] Still refer to Figure 7B, Vdd backside vias 513 penetrate the ILD layer 115a from the back side of the semiconductor structure to land on the extended S / D contact 110. The Vdd backside vias 513 may also penetrate other components (e.g., the etch stop layer 129 and / or the liner barrier layer 117). Each extended S / D contact 110 includes an extended portion and a non-extended portion. The extended portion may be thicker than the non-extended portion in the z-direction, and the extended portion is where the Vdd backside via 513 lands. As shown, each extended portion extends beyond the sidewalls of the S / D component 106b and has a lower portion directly adjacent to the S / D component 106b. As shown, the bottom surface of the lower portion is lower than the top surface of the S / D component 106b. The non-extended portion of the extended S / D contact 110 is located directly above the top surface of the S / D component 106b and can directly contact the top surface of the S / D component 106b. In this embodiment, S / D components 106 b are similar to S / D components 106 a, except that S / D components 106 b are p-type S / D components for pull-up transistors and can be doped with p-type dopants, such as boron. Similar to S / D components 106 a, each S / D component 106 b can be epitaxially grown from the source / drain region of active area 106 , and S / D components 106 b and the corresponding active area 106 can be surrounded by various isolation structures 107 , fin spacers 109 , and liner barrier layers 117 . Similarly, S / D components 106 b can be lined with front-side silicide layers 116 . Respective front-side silicide layers 116 are disposed above respective top surfaces of S / D components 106 b and connect between the epitaxial components of S / D components 106 b and extended S / D contacts 110 .

[0072] Still refer to Figure 7B , the Vdd backside via 513 lands directly on the backside via rail 130 for further electrical routing on the backside of the semiconductor device. And for a double-sided power configuration, the corresponding frontside vias 112 land directly on the front side of the extended S / D contact 110, and the frontside via rail 120 lands directly on the corresponding frontside vias 112 for further electrical routing on the front side of the semiconductor device. In this case, these corresponding frontside vias 112 and the Vdd backside via 113 are located on opposite sides of the extended S / D contact 110. These frontside vias 112 (along with other frontside vias 112) can be surrounded by an ILD layer 115c, the frontside via rail 120 can be surrounded by an ILD layer 115d, and the backside via rail 130 can be surrounded by an ILD layer 115e. As previously described, the ILD layers 115c, 115d, and 115e can have similar material compositions as the ILD layers 115a and 115b. Although not shown, the ILD layers 115 c , 115 d , and 115 e may also be lined with a liner barrier layer 117 .

[0073] Still refer to Figure 7BThe Vss backside vias 713a penetrate the source / drain regions of the active area 106 to directly land on the corresponding S / D components 106a. Because the Vss backside vias 713a land on the S / D components 106a, each S / D component 106a can also be lined with a backside silicide layer 216. The corresponding backside silicide layer 216 is disposed above the corresponding bottom surface of the S / D components 106a. The backside silicide layer 216 can include a material similar to the frontside silicide layer 116, and they form an interface between the epitaxial components of the S / D components 106a and the Vss backside vias 713a. Note that because the size of the Vss backside vias 713a is limited by the active area 106, the Vss backside vias 713a can have a width in the x-direction that is smaller than the width of the Vdd backside via 513.

[0074] Figures 8A-8B 、 Figures 9A-9B and Figures 10A-10B An additional embodiment of the present disclosure is shown highlighting a portion of the semiconductor structure 100 having Vss and Vdd backside vias 113 . Figure 8A 、 Figure 9A and Figure 10A Solid black frames 500b, 500c and 500d are shown respectively, each of which is similar to Figure 7A The solid black frame 500a in FIG. Figure 8B 、 Figure 9B and Figure 10B Displays the corresponding edges Figure 8A 、 Figure 9A and Figure 10A FIG. 5 is a cross-sectional view of the semiconductor device structure shown in FIG. 5 , which is taken along line segment BB′ in FIG. 5 . Figures 8A-8B 、 Figures 9A-9B and Figures 10A-10B Each of these is similar to Figures 7A-7B For the sake of brevity, similar features will not be repeated in the labeling and description. The difference lies in the configuration of the Vss backside via 113. Specifically, the various embodiments of the Vss backside via 113 described previously can be used with Figures 7A-7B The Vdd backside via 113 described in the embodiment is incorporated into the Figures 8A-8B In the figure, Vss backside via 113 / 713b corresponds to Figures 4A-4B Vss backside via 113 shown and described. Figures 9A-9B In the figure, Vss backside via 113 / 713c corresponds to Figures 5A-5B Vss backside via 113 shown and described. Figures 10A-10B In the figure, Vss backside via 113 / 713d corresponds to Figures 6A-6B Vss backside via 113 shown and described.

[0075] The semiconductor structure 100 described herein is formed through a suitable fabrication process. In one embodiment, the fabrication process includes front-side and back-side processes. The front-side process includes forming a fin-shaped active area 106 protruding above an isolation structure 107 above a substrate, forming an S / D feature 106a above the S / D region of the fin-shaped active area 106, forming a gate structure above the channel region of the fin-shaped active area 106, forming a gate insulation structure 111 that cuts through the gate structure to form a separate gate 108, forming an S / D contact 110 above the S / D feature 106a, and forming a front-side via 112 above the S / D contact 110. The front-side process may also include forming an interconnect above the front-side via 112, where the interconnect may include a front-side metal line, such as a front-side via rail 120, which may connect to additional higher-level metal lines for front-side power connections. The back-side process includes flipping the semiconductor structure 100 to thin the substrate from the back side. After thinning, only portions of the fin-shaped active area 106 and the isolation structure 107 remain. The backside processing also includes a planarization process and the deposition of a dielectric layer (e.g., an etch stop layer 129) on the backside of the thinned fin active area 106 and the isolation structure 107. The backside processing includes etching from the backside to form a backside via trench that exposes the bottom surface of the S / D contact 110. The backside via trench can pass through the gate insulation structure 111 and / or other dielectric layers (e.g., the etch stop layer 129, the ILD layer 115a, or the barrier liner layer 117). Then, a backside via 113 is formed in the backside via trench. The backside processing can also include forming a backside metal line, such as a backside via rail 130, which can be connected to additional underlying metal lines for backside power connections.

[0076] Although not limiting, the present disclosure provides advantages for semiconductor devices and structures (e.g., SRAM devices) having backside vias for backside power connections. One example advantage is repositioning the backside vias to land on metal contacts rather than S / D components. This provides overlap improvements because the metal contacts provide a larger bonding space than the S / D components. Another example advantage is that the backside vias are formed to be larger than the critical dimensions of the active area, thereby reducing contact resistance while providing benefits to the process window. Another example advantage is providing the backside vias of the present disclosure for Vdd and Vss power connections, thereby improving SRAM performance.

[0077] One concept disclosed herein relates to a semiconductor structure. The semiconductor structure includes a first source / drain (S / D) epitaxial component, a second S / D epitaxial component adjacent to the first S / D epitaxial component, an insulating structure between the first and second S / D epitaxial components, and a shared S / D contact above the top surfaces of the first and second S / D epitaxial components. A central portion of the shared S / D contact is directly between a side surface of the first S / D epitaxial component and a side surface of the second S / D epitaxial component. The central portion is directly above the insulating structure. The semiconductor structure also includes a backside via extending through the insulating structure and directly onto the bottom surface of the central portion.

[0078] In one embodiment, the first and second S / D epitaxial components are S / D components of a pull-down transistor in a static random access memory (SRAM) structure. In one embodiment, the backside via is electrically connected to a power supply or a ground.

[0079] In one embodiment, the semiconductor structure further includes a front side via directly landing on a top surface of the shared S / D contact, wherein the front side via and the back side via are located on opposite sides of the shared S / D contact.

[0080] In one embodiment, the semiconductor structure further comprises a fin-type active region located below the first and second S / D epitaxial components, the fin-type active region extending longitudinally along a first direction, and each fin-type active region having a fin width along a second direction perpendicular to the first direction. The backside via has a via length along the second direction, and the via length is greater than the fin width. In a further embodiment, a ratio of the via length to the fin width is in a range between about 1.5 and about 4. In a further embodiment, the shared S / D contact extends longitudinally along the second direction, and the shared S / D contact has an S / D contact width along the first direction, wherein the backside via has a via width along the first direction, and the ratio of the via width to the S / D contact width is approximately equal to or greater than 1. In a further embodiment, the semiconductor structure further comprises a dielectric layer located below the fin-type active region, wherein the backside via also passes through the dielectric layer to the bottom surface of the central portion.

[0081] In one embodiment, the semiconductor structure further includes a first gate structure located above the first S / D epitaxial component and a second gate structure located above the second S / D epitaxial component, wherein the backside via substantially spans between the gate spacers between the first gate structure and the second gate structure along a length direction of the first gate structure and the second gate structure.

[0082] Another concept disclosed herein relates to a semiconductor structure. The semiconductor structure includes a first source / drain (S / D) epitaxial component over a first active region, a second S / D epitaxial component over a second active region adjacent to the first active region, an insulating structure between the first and second S / D epitaxial components, and a shared S / D contact over the top surfaces of the first and second S / D epitaxial components. A central portion of the shared S / D contact is directly between a side surface of the first S / D epitaxial component and a side surface of the second S / D epitaxial component, wherein the central portion is directly over the insulating structure. The semiconductor structure also includes a backside via having a first portion extending through the insulating structure to directly land on a bottom surface of the central portion, a second portion extending through the first active region to directly land on the first S / D epitaxial component, and a third portion extending through the second active region to directly land on the second S / D epitaxial component.

[0083] In one embodiment, the semiconductor structure further comprises a front-side silicide layer located between the first S / D epitaxial component and the shared S / D contact and between the second S / D epitaxial component and the shared S / D contact; and a back-side silicide layer located between the first S / D epitaxial component and the second portion of the back-side via and between the second S / D epitaxial component and the third portion of the back-side via.

[0084] In one embodiment, the first portion of the backside via has a first width along the first direction, the second portion of the backside via has a second width along the first direction, and the third portion of the backside via has a third width along the first direction, and the first width is greater than the second width and greater than the third width. In a further embodiment, the backside via further includes a horizontal fourth portion connecting the first portion, the second portion, and the third portion, and the first portion, the second portion, and the third portion are laterally spaced apart from each other. In a further embodiment, the first active area and the second active area have a fin width along the first direction, and the first active area is spaced apart from the second active area along the first direction by a fin pitch, wherein the horizontal fourth portion has a backside via length approximately equal to twice the fin width plus the fin pitch.

[0085] In one embodiment, the back through hole has an inclined surface extending upward from the top surface of the second portion to the top surface of the first portion.

[0086] Yet another concept disclosed herein relates to a semiconductor structure comprising a source / drain (S / D) epitaxial component over an active region, an S / D contact over a top surface of the S / D epitaxial component, wherein the S / D contact has a longitudinally extending extension extending beyond a sidewall of the S / D epitaxial component. The semiconductor structure further comprises an interlayer dielectric (ILD) layer surrounding the active region, the S / D epitaxial component, and the S / D contact, and a backside via extending through the ILD layer and directly onto a bottom surface of the extension.

[0087] In one embodiment, the active area has a first width along a first direction, the backside via has a second width along the first direction, and the second width is greater than the first width.

[0088] In one embodiment, the S / D contact has a non-extended portion directly above the top surface of the S / D epitaxial component, and the non-extended portion has a first thickness in the vertical direction, and the extended portion has a second thickness in the vertical direction, and the second thickness is greater than the first thickness.

[0089] In one embodiment, the active region is a first active region, and the semiconductor structure further includes a second active region located adjacent to the first active region on a first side, and a third active region located adjacent to the first active region on the first side, wherein the third active region is separated from the second active region by a gap along a first direction. In a top view, the extension portion extends beyond the second active region and the third active region along a second direction perpendicular to the first direction, and the extension portion extends through the gap between the second active region and the third active region.

[0090] In one embodiment, the S / D epitaxial component is a first S / D epitaxial component, the active region is a first active region, the S / D contact is a first S / D contact, and the backside via is a first backside via. The semiconductor structure further includes a second S / D epitaxial component located above a second active region, a third S / D epitaxial component located above a third active region adjacent to the second active region, a shared S / D contact located above top surfaces of the second and third S / D epitaxial components, and a backside via located directly on a bottom surface of the shared S / D contact.

[0091] The foregoing overview of the features of several embodiments enables a person of ordinary skill in the art to better understand the nature of the disclosure. Those of ordinary skill in the art will readily understand that they can freely utilize the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor structure, characterized in that include: a first source / drain epitaxial component; a second source / drain epitaxial component adjacent to the first source / drain epitaxial component; an insulating structure located between the first and second source / drain epitaxial components; a shared source / drain contact positioned above the top surfaces of the first and second source / drain epitaxial features, wherein a central portion of the shared source / drain contact is positioned directly between a side surface of the first source / drain epitaxial feature and a side surface of the second source / drain epitaxial feature, wherein the central portion is positioned directly above the insulating structure; as well as The back through hole passes through the insulating structure and directly lands on the bottom surface of the central portion.

2. The semiconductor structure according to claim 1, wherein: The first and second source / drain epitaxial features are source / drain features of a pull-down transistor in a static random access memory structure.

3. The semiconductor structure according to claim 1, wherein: The backside vias are electrically connected to power or ground.

4. The semiconductor structure according to claim 1, wherein: Also includes: A frontside via lands directly on a top surface of the shared source / drain contact, wherein the frontside via and the backside via are located on opposite sides of the shared source / drain contact.

5. The semiconductor structure according to claim 1, wherein: Also includes: a fin-type active region located below the first and second source / drain epitaxial components, the fin-type active region extending longitudinally along a first direction, and each of the fin-type active regions having a fin width along a second direction perpendicular to the first direction, The back through hole has a through hole length along the second direction, and the through hole length is greater than the fin width.

6. A semiconductor structure, characterized in that include: a first source / drain epitaxial component located above the first active area; a second source / drain epitaxial component located above a second active region adjacent to the first active region; an insulating structure located between the first and second source / drain epitaxial components; a shared source / drain contact positioned above the top surfaces of the first and second source / drain epitaxial features, wherein a central portion of the shared source / drain contact is positioned directly between a side surface of the first source / drain epitaxial feature and a side surface of the second source / drain epitaxial feature, wherein the central portion is positioned directly above the insulating structure; as well as A backside via has a first portion passing through the insulating structure to directly land on the bottom surface of the central portion, a second portion passing through the first active area to directly land on the first source / drain epitaxial component, and a third portion passing through the second active area to directly land on the second source / drain epitaxial component.

7. The semiconductor structure according to claim 6, wherein: Also includes: a front-side silicide layer located between the first source / drain epitaxial component and the shared source / drain contact and between the second source / drain epitaxial component and the shared source / drain contact; as well as A backside silicide layer is located between the first source / drain epitaxial feature and the second portion of the backside via and between the second source / drain epitaxial feature and the third portion of the backside via.

8. The semiconductor structure according to claim 6, wherein: The back through hole has an inclined surface extending upward from a top surface of the second portion to a top surface of the first portion.

9. A semiconductor structure, characterized in that include: source / drain epitaxial components located above the active area; a source / drain contact positioned above a top surface of the source / drain epitaxial feature, wherein the source / drain contact has an extension portion extending longitudinally beyond a sidewall of the source / drain epitaxial feature; an interlayer dielectric layer surrounding the active region, the source / drain epitaxial features, and the source / drain contacts; as well as A backside via hole passes through the interlayer dielectric layer and directly lands on the bottom surface of the extension portion.

10. The semiconductor structure according to claim 9, wherein: The active area is a first active area, and further includes: a second active region located on a first side adjacent to the first active region; and a third active region located on the first side and adjacent to the first active region; The third active region and the second active region are separated by a gap along the first direction. In the top view, the extension portion extends beyond the second active region and the third active region along a second direction perpendicular to the first direction, and the extension portion extends through the gap between the second active region and the third active region.

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