Solar cell and photovoltaic module

Abstract

The utility model provides a solar cell and a photovoltaic assembly, and belongs to the photovoltaic field. The solar cell comprises a silicon substrate, the back surface of the silicon substrate is provided with tunneling oxide layers which are distributed discontinuously, and the tunneling oxide layers are divided into a plurality of P regions and a plurality of N regions which are alternately arranged at intervals; a p + doped polycrystalline silicon carbide layer and a p + doped polycrystalline silicon layer are arranged on the P region along the direction far away from the tunneling oxide layer; an n + doped polycrystalline silicon carbide layer is arranged on the N region; a back passivation layer and a back anti-reflection layer are laminated on the outer surface of the p + doped polycrystalline silicon layer, a spacer region between the P region and the N region and the outer surface of the n + doped polycrystalline silicon carbide layer along the direction far away from the silicon substrate; a first back metal electrode is arranged on the P region, and one end of the first back metal electrode is in ohmic contact with the p + doped polycrystalline silicon layer; a second back metal electrode is arranged on the N region, and one end of the second back metal electrode is in ohmic contact with the n + doped polycrystalline silicon carbide layer.

Description

Technical Field

[0001] The utility model belongs to the technical field of photovoltaic component production and manufacturing, and specifically relates to a solar cell and a photovoltaic component. Background Art

[0002] PERC (passivated emitter and rear surface contact) cell technology is currently the mainstream cell technology in the market. Currently, mass-produced PERC cells can achieve efficiencies of ~23.5%, but increasing them to over 24% is challenging. Interdigitated back-contact (IBC) cells (interdigitated back contact) can easily achieve efficiencies exceeding 24.5% due to the lack of front-side light shielding. With the addition of a passivated contact structure, efficiencies can reach over 26%. However, the complex manufacturing process for IBC cells has prevented them from becoming a mainstream route for large-scale production. It is generally believed that the next generation of PERC cell technology will be N-type TOPCon (tunneling oxide passivated contact) cells or heterojunction cells combined with IBC technology. IBC cell technology can be combined with TOPCon or heterojunction structures, such as in TBC back-contact solar cells (TOPCon-IBC cells). This combination of the tunneling oxide passivation of TOPCon technology and the interdigitated back contact structure of IBC technology can further improve cell efficiency. Current TBC battery technology is mostly prepared by deposition or printing mask + wet etching or printing slurry diffusion. However, the wet etching process is complicated, the printing slurry will more or less have contamination problems and the process is also complicated, making it difficult to improve battery efficiency.

[0003] Therefore, how to further improve the photoelectric conversion efficiency of solar cells is a technical problem that needs to be solved urgently. Utility Model Content

[0004] In response to the shortcomings of the prior art, the present invention aims to provide a solar cell and photovoltaic module. This invention provides a novel solar cell structure that addresses the issues of low efficiency caused by interface recombination between the metal electrode and the silicon substrate, as well as leakage between the PN junctions, resulting in excellent photoelectric conversion efficiency. Furthermore, this solar cell has a wide process window and is highly manufacturable.

[0005] In order to achieve the purpose of this utility model, the utility model adopts the following technical solutions:

[0006] In a first aspect, the present invention provides a solar cell, comprising a silicon substrate, wherein a discontinuously distributed tunneling oxide layer is provided on the back side of the silicon substrate, wherein the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, wherein the P regions and the N regions are alternately arranged in sequence;

[0007] A p+ doped layer is provided on the P region, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunnel oxide layer; an n+ doped polycrystalline silicon carbide layer is provided on the N region;

[0008] A back passivation layer and a back anti-reflection layer are stacked on the outer surface of the p+ doped polycrystalline silicon layer, the spacing region between the P region and the N region, and the outer surface of the n+ doped polycrystalline silicon carbide layer in a direction away from the silicon substrate;

[0009] A first back metal electrode is provided on the P region, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer on the P region; a second back metal electrode is provided on the N region, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer on the N region.

[0010] This utility model provides a novel solar cell structure that solves the problems of low efficiency caused by interface recombination between metal electrodes and silicon substrates, as well as leakage between PN junctions, and has excellent photoelectric conversion efficiency. Furthermore, the solar cell has a wide process window and strong mass production capabilities.

[0011] It should be noted that the outer surface of the p+ doped polysilicon layer refers to the surface that does not contact the p+ doped polycrystalline silicon carbide layer, and the outer surface of the n+ doped polycrystalline silicon carbide layer refers to the surface that does not contact the N region of the tunnel oxide layer.

[0012] Preferably, the silicon substrate is an n-type silicon wafer.

[0013] Preferably, the resistivity of the n-type silicon wafer is 0.3-7Ω·cm, for example, it can be 0.3Ω·cm, 0.5Ω·cm, 1Ω·cm, 2Ω·cm, 3Ω·cm, 4Ω·cm, 5Ω·cm, 6Ω·cm or 7Ω·cm, etc., preferably 0.5-3.5Ω·cm.

[0014] Preferably, the tunnel oxide layer comprises a silicon oxide layer.

[0015] Preferably, the thickness of the tunnel oxide layer is 0.5-3 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm, and preferably 1-2.5 nm.

[0016] Preferably, the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer.

[0017] Preferably, the doping concentration of the doping element in the p+ doped polycrystalline silicon carbide layer is 3×10 19 -5×1020 cm -3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 3×10 20 cm -3 or 5×10 20 cm -3 wait.

[0018] Preferably, the thickness of the p+ doped polycrystalline silicon carbide layer is 30-100 nm, for example, 30 nm, 50 nm, 70 nm or 90 nm.

[0019] Preferably, the p+ doped polysilicon layer is a p+ boron doped polysilicon layer.

[0020] Preferably, the doping concentration of the doping element in the p+ doped polysilicon layer is 3×10 19 -5×10 20 cm -3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 3×10 20 cm -3 or 5×10 20 cm -3 wait.

[0021] Preferably, the thickness of the p+ doped polysilicon layer is 50-200 nm, for example, 50 nm, 100 nm, 150 nm or 200 nm.

[0022] Preferably, the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer.

[0023] Preferably, the doping concentration of the doping element in the n+ doped polycrystalline silicon carbide layer is 4×10 20 -2×10 21 cm -3 , for example, it can be 4×10 20 cm -3 , 6×10 20 cm -3 , 8×10 20 cm -3 , 1×10 21 cm -3 or 2×10 21 cm-3 wait.

[0024] Preferably, the thickness of the n+ doped polycrystalline silicon carbide layer is 30-100 nm, for example, 30 nm, 50 nm, 70 nm or 90 nm.

[0025] Preferably, the width of the discontinuity between adjacent P regions and N regions is 10-60 μm, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm or 60 μm.

[0026] Preferably, the front surface of the silicon substrate is a suede structure, and a phosphorus-diffused lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially provided on the front surface in a direction away from the silicon substrate.

[0027] Preferably, the back passivation layer and the front passivation layer each independently include a silicon oxide layer and / or an aluminum oxide layer.

[0028] Preferably, the thickness of the back passivation layer and the front passivation layer is independently 2-10 nm, for example, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.

[0029] Preferably, the back anti-reflection layer and the front anti-reflection layer each independently include any one of a silicon nitride layer, a silicon oxynitride layer or a silicon oxide layer, or a combination of at least two of them.

[0030] Preferably, the thickness of the back anti-reflection layer and the front anti-reflection layer is independently 60-150 nm, for example, 60 nm, 80 nm, 100 nm, 110 nm, 130 nm or 150 nm, etc., preferably 60-100 nm.

[0031] Preferably, the first back metal electrode and the second back metal electrode each independently include a silver electrode and / or an aluminum electrode.

[0032] Preferably, the surface phosphorus concentration of the phosphorus lightly doped layer is 5×10 17 -5×10 20 cm -3 , for example, it can be 5×10 17 cm -3 , 5×10 18 cm -3 , 5×10 19 cm -3 or 5×10 20 cm -3 etc., preferably 1×10 18 -1×10 20 cm -3 .

[0033] Preferably, the diffusion sheet resistance of the phosphorus lightly doped layer is 200-500Ω / sq, for example, 200Ω / sq, 300Ω / sq, 400Ω / sq or 500Ω / sq.

[0034] Preferably, the junction depth of the phosphorus-diffused lightly doped layer is 0.3-1.5 μm, for example, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1.2 μm or 1.5 μm.

[0035] In a second aspect, the present invention provides a method for preparing a solar cell according to the first aspect, the method comprising the following steps:

[0036] (1) growing a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer, and a first mask layer on the back side of the silicon substrate in sequence, and then performing patterned laser windowing and etching processing to remove the first mask layer and the p+ doped amorphous silicon layer in the laser windowing area to form spaced grooves;

[0037] (2) sequentially growing an n+ doped amorphous silicon layer and a second mask layer on the first mask layer processed in step (1) and on the p+ doped amorphous silicon carbide layer in the groove, then performing laser windowing and etching at the junction of the P / N regions to form a channel to isolate the P / N regions, and simultaneously performing a texturing process on the front side of the silicon substrate and cleaning to remove the second mask layer; the channel penetrates the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the n+ doped amorphous silicon layer and the second mask layer at the junction of the P / N regions;

[0038] (3) performing phosphorus diffusion on the silicon substrate after texturing in step (2), and then performing oxidation annealing treatment, so that the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ doped amorphous silicon layer on the back are converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer respectively, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer, and then the PSG layer and the first mask layer are removed;

[0039] (4) A passivation layer and an anti-reflection layer are grown on the front and back sides of the silicon substrate after treatment in step (3), respectively, and then metallization treatment and sintering treatment are performed, so that the N region and the P region on the back side form a first back metal electrode and a second back metal electrode, respectively, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, thereby obtaining the solar cell.

[0040] The preparation method provided by the present invention has a simple process, a large process window, and strong mass production capability. The P / N regions are isolated by forming a channel, which can prevent the P / N regions from becoming conductive in subsequent processes. Furthermore, a front and back passivation layer is formed for the spaced non-diffused regions, effectively reducing interface recombination and ensuring the passivation effect. Furthermore, during the oxidation annealing treatment, the P-type amorphous silicon carbide in contact with the n+-doped amorphous silicon layer can be directly converted into an n+-doped polycrystalline silicon carbide layer, thereby forming an n-type and p-type tunneling passivation contact structure in one step, reducing the impact of the primary environment on the tunneling oxide layer.

[0041] Preferably, the silicon substrate in step (1) is a double-sided polished n-type silicon wafer.

[0042] Preferably, the p+ doped amorphous silicon carbide layer in step (1) is a single layer film or a multilayer film.

[0043] Preferably, the multilayer film includes any one layer of an intrinsic layer, a lightly doped layer or a heavily doped layer, or a combination of at least two layers.

[0044] Preferably, the material of the first mask layer includes silicon oxide.

[0045] Preferably, the thickness of the first mask layer is 20-100 nm, for example, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm.

[0046] Preferably, the growth methods of the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the first mask layer in step (1) each independently include PECVD (plasma enhanced chemical vapor deposition).

[0047] Preferably, in the process of patterned laser windowing in step (1), the laser used includes ultraviolet nanosecond laser or picosecond laser.

[0048] Preferably, during the etching process in step (1), the etchant used includes any one of KOH, NaOH or TMAH, or a combination of at least two of them.

[0049] Preferably, the thickness of the n+ doped amorphous silicon layer in step (2) is 30-100 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0050] Preferably, the n+ doped amorphous silicon layer in step (2) is a single layer film or a multilayer film.

[0051] Preferably, when the n+ doped amorphous silicon layer in step (2) is a multilayer film, the multilayer film includes a lightly doped layer and a heavily doped layer.

[0052] Preferably, in step (2), the material of the second mask layer includes silicon oxide.

[0053] Preferably, the thickness of the second mask layer in step (2) is 10-50 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0054] Preferably, the growth methods of the n+ doped amorphous silicon layer and the second mask layer in step (2) each independently include PECVD method.

[0055] Preferably, in the laser windowing process of step (2), the laser used includes green light or infrared band laser.

[0056] Preferably, the etching method in step (2) includes wet etching.

[0057] Preferably, in the phosphorus diffusion process of step (3), the phosphorus source used includes phosphorus oxychloride.

[0058] Preferably, the temperature of the phosphorus diffusion in step (3) is 800-900°C, for example, it can be 800°C, 820°C, 840°C, 860°C, 880°C or 900°C.

[0059] Preferably, the atmosphere of the oxidation annealing treatment in step (3) is an oxygen-containing atmosphere.

[0060] Preferably, the gas in the oxygen-containing atmosphere includes oxygen and an inert gas. For example, the inert gas may be nitrogen.

[0061] Preferably, the temperature of the oxidation annealing treatment in step (3) is 900-1000°C, for example, it can be 900°C, 920°C, 940°C, 960°C, 980°C or 1000°C.

[0062] Preferably, the growth method of the passivation layer in step (4) includes thermal oxidation or ALD (atomic layer deposition).

[0063] Preferably, the growth method of the anti-reflection layer in step (4) includes a PECVD method.

[0064] Preferably, the metallization treatment in step (4) includes any one of screen printing, laser transfer or electroplating.

[0065] Preferably, the peak temperature of the sintering treatment in step (4) is 650-750°C, for example, 650°C, 700°C or 750°C.

[0066] Preferably, after the sintering treatment in step (4), post-treatment is further performed, and the post-treatment includes light injection annealing.

[0067] In the present invention, the light injection annealing step can further improve the photoelectric conversion efficiency of the solar cell.

[0068] In a third aspect, the present invention provides a photovoltaic assembly, which includes the solar cell as described in the first aspect.

[0069] The numerical range described in the present invention includes not only the point values ​​listed above, but also any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0070] Compared with the prior art, the present invention has the following beneficial effects:

[0071] The utility model provides a solar cell with a novel structure, which solves the problem of low efficiency caused by interface compounding of metal electrodes and silicon substrates and the problem of conduction leakage between PNs, and has excellent photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 This is a schematic structural diagram of the solar cell provided in Example 1 of the utility model.

[0073] Among them, 1-n-type silicon wafer; 2-phosphorus-diffused lightly doped layer; 3-front passivation layer; 4-front anti-reflection layer; 5-tunneling oxide layer; 6-p+ doped polycrystalline silicon carbide layer; 7-p+ doped polycrystalline silicon layer; 8-n+ doped polycrystalline silicon carbide layer; 9-back passivation layer; 10-back anti-reflection layer; 11-first back metal electrode; 12-second back metal electrode. DETAILED DESCRIPTION

[0074] The technical solution of the present invention is further described below through specific embodiments. Those skilled in the art should understand that the embodiments are only for helping to understand the present invention and should not be regarded as specific limitations of the present invention.

[0075] Example 1

[0076] This embodiment provides a solar cell, the structural diagram of which is shown in FIG. Figure 1 As shown, the solar cell includes an n-type silicon wafer 1 with a resistivity of 1.5 Ω·cm. A discontinuously distributed tunneling oxide layer 5 is provided on the back side of the n-type silicon wafer 1. The tunneling oxide layer 5 is divided into a plurality of P regions and a plurality of N regions, and the P regions and N regions are alternately arranged in sequence. A p+ doped layer is provided on the P region. The p+ doped layer includes a p+ doped polycrystalline silicon carbide layer 6 and a p+ doped polycrystalline silicon layer 7 along a direction away from the tunneling oxide layer 5. An n+ doped polycrystalline silicon carbide layer 8 is provided on the N region.

[0077] The tunneling oxide layer 5 is a silicon oxide layer with a thickness of 1.5 nm; the p+ doped polycrystalline silicon carbide layer 6 is a p+ boron doped polycrystalline silicon carbide layer with a doping concentration of 1×10 20 cm -3 , with a thickness of 60nm; the p+ doped polysilicon layer 7 is a p+ boron doped polysilicon layer with a doping concentration of 1×10 20 cm -3 , with a thickness of 120 nm; the n+ doped polycrystalline silicon carbide layer 8 is an n+ phosphorus doped polycrystalline silicon carbide layer with a doping concentration of 1×10 21 cm -3 , with a thickness of 60 nm, the thickness of the n+ doped polycrystalline silicon carbide layer 8 is the same as that of the p+ doped polycrystalline silicon carbide layer 6 .

[0078] A back passivation layer 9 and a back anti-reflection layer 10 are stacked on the outer surface of the p+ doped polycrystalline silicon layer 7, the spacing region between the P region and the N region (with a width of 30 μm), and the outer surface of the n+ doped polycrystalline silicon carbide layer in a direction away from the n-type silicon wafer 1.

[0079] The back passivation layer 9 is a silicon oxide layer with a thickness of 3.5 nm; the back anti-reflection layer 10 includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 100 nm.

[0080] A first groove is partially opened in the back passivation layer 9 and the back anti-reflection layer 10 arranged on the p+ doped polycrystalline silicon layer 7, and a first back metal electrode 11 is arranged in the first groove, and one end of the first back metal electrode 11 forms an ohmic contact with the p+ doped polycrystalline silicon layer 7, and the other end extends out of the back anti-reflection layer 10; a second groove is partially opened in the back passivation layer 9 and the back anti-reflection layer 10 arranged on the n+ doped polycrystalline silicon carbide layer 8, and a second back metal electrode 12 is arranged in the second groove, and one end of the second back metal electrode 12 forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer 8, and the other end extends out of the back anti-reflection layer 10; wherein, the first back metal electrode 11 is a silver electrode, and the second back metal electrode 12 is a silver electrode.

[0081] The front surface of the n-type silicon wafer 1 has a suede structure. A phosphorus-diffused lightly doped layer 2, a front passivation layer 3, and a front anti-reflection layer 4 are sequentially provided on the front surface in a direction away from the n-type silicon wafer 1. The surface phosphorus concentration of the phosphorus-diffused lightly doped layer 2 is 1×10 19 cm -3 , the diffusion square resistance is 400Ω / sq, and the junction depth is 1μm; the front passivation layer 3 is a silicon oxide layer with a thickness of 3.5nm; the front anti-reflection layer 4 includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 80nm.

[0082] This embodiment also provides a method for preparing the above-mentioned TBC back contact solar cell, the preparation method comprising the following steps:

[0083] (1) The n-type silicon wafer is alkaline polished to remove the mechanical damage layer on the front and back sides, and then cleaned by RCA cleaning method. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer are grown on the back side of the n-type silicon wafer by PECVD method. Then, a patterned laser window is opened by ultraviolet picosecond laser, and the laser window area is etched by KOH to remove the first mask layer and the p+ doped amorphous silicon layer in the laser window area, forming spaced grooves with a width of 600 μm.

[0084] The p+ doped amorphous silicon carbide layer includes an intrinsic amorphous silicon carbide layer with a thickness of 20 nm and a p+ lightly doped amorphous silicon carbide layer with a thickness of 40 nm along a direction away from the tunnel oxide layer; the material of the first mask layer is silicon oxide with a thickness of 40 nm.

[0085] (2) A PECVD method is used to sequentially grow an n+ phosphorus-doped amorphous silicon layer with a thickness of 50 nm and a second mask layer with a thickness of 20 nm on the first mask layer treated in step (1) and the p+ doped amorphous silicon carbide layer in the first groove, and then a laser window is opened at the intersection of the P / N region using a 532 nm wavelength ultraviolet nanosecond laser, and the second mask layer, the n+ phosphorus-doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser window are wet-etched to form a channel with a width of 30 μm to disconnect and isolate the P / N region, and at the same time, the front side of the n-type silicon wafer is textured and cleaned to remove the second mask layer.

[0086] The second mask layer is made of silicon oxide; the channel penetrates the tunneling oxide layer at the junction of the P / N regions, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer.

[0087] (3) At 840°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after the texturing in step (2), and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a first annealing at a temperature of 910°C and a second annealing at a temperature of 940°C, so that a phosphorus-diffused lightly doped layer is formed on the front side of the n-type silicon wafer, and the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ phosphorus-doped amorphous silicon layer on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ phosphorus-doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

[0088] (4) The PSG layer is removed using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer.

[0089] (5) A passivation layer is grown on the front and back sides of the n-type silicon wafer after being treated in step (4) by a thermal oxygen oxidation method, and a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layer on the front and back sides of the n-type silicon wafer by a PECVD method as an anti-reflection layer.

[0090] (6) printing silver paste on the N region and the P region of the back side of the n-type silicon wafer processed in step (5) by screen printing to form patterned metal electrodes respectively, and then performing contact treatment on the metal electrodes at 750° C. to obtain a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and then performing post-processing by light injection annealing to finally obtain the solar cell.

[0091] Example 2

[0092] This embodiment provides a solar cell, comprising an n-type silicon wafer having a resistivity of 1 Ω·cm. A discontinuously distributed tunneling oxide layer is provided on the back surface of the n-type silicon wafer. The tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, the P regions and the N regions being alternately arranged in sequence. A p+ doped layer is provided on the P region, the p+ doped layer including a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunneling oxide layer; and an n+ doped polycrystalline silicon carbide layer is provided on the N region.

[0093] The tunneling oxide layer is a silicon oxide layer with a thickness of 0.5 nm; the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer with a doping concentration of 3×10 19 cm -3 , with a thickness of 30nm; the p+ doped polysilicon layer is a p+ boron doped polysilicon layer with a doping concentration of 3×10 19 cm -3 , with a thickness of 50nm; the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer with a doping concentration of 4×10 20 cm -3 , with a thickness of 30 nm; the thickness of the n+ doped polycrystalline silicon carbide layer is the same as that of the p+ doped polycrystalline silicon carbide layer.

[0094] A back passivation layer and a back anti-reflection layer are stacked on the outer surface of the p+ doped polysilicon layer, the spacing region between the P region and the N region (with a width of 10 μm), and the outer surface of the n+ doped polycrystalline silicon carbide layer in a direction away from the n-type silicon wafer.

[0095] Among them, the back passivation layer is an aluminum oxide layer with a thickness of 2nm; the back anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 60nm.

[0096] A first groove is partially opened in the back passivation layer and the back anti-reflection layer arranged on the p+ doped polycrystalline silicon layer, and a first back metal electrode is arranged in the first groove, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer; a second groove is partially opened in the back passivation layer and the back anti-reflection layer arranged on the n+ doped polycrystalline silicon carbide layer, and a second back metal electrode is arranged in the second groove, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer; wherein, the first back metal electrode is a silver electrode, and the second back metal electrode is a silver electrode.

[0097] The front side of the n-type silicon wafer has a suede structure. On the front side, a phosphorus diffusion lightly doped layer, a front passivation layer, and a front anti-reflection layer are sequentially arranged in the direction away from the n-type silicon wafer. The surface phosphorus concentration of the phosphorus diffusion lightly doped layer is 5×10 17 cm -3 The diffusion square resistance is 500Ω / sq and the junction depth is 0.5μm; the front passivation layer is an aluminum oxide layer with a thickness of 2nm; the front anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 60nm.

[0098] This embodiment also provides a method for preparing the above-mentioned TBC back contact solar cell, the preparation method comprising the following steps:

[0099] (1) The n-type silicon wafer is alkaline polished to remove the mechanical damage layer on the front and back sides, and then cleaned by RCA cleaning method. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer are grown on the back side of the n-type silicon wafer by PECVD method. Then, a patterned laser window is opened by ultraviolet picosecond laser, and the laser window area is etched by KOH to remove the first mask layer and the p+ doped amorphous silicon layer in the laser window area, forming spaced grooves with a width of 100 μm.

[0100] The material of the first mask layer is silicon oxide, and the thickness is 20 nm.

[0101] (2) A PECVD method is used to sequentially grow an n+ phosphorus-doped amorphous silicon layer with a thickness of 30 nm and a second mask layer with a thickness of 10 nm on the first mask layer treated in step (1) and the p+ doped amorphous silicon carbide layer in the first groove, and then a laser window is opened at the intersection of the P / N region using a 532 nm wavelength ultraviolet nanosecond laser, and the second mask layer, the n+ phosphorus-doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser window are wet-etched to form a channel with a width of 10 μm to disconnect and isolate the P / N region, and at the same time, the front side of the n-type silicon wafer is textured and cleaned to remove the second mask layer.

[0102] The second mask layer is made of silicon oxide; the channel penetrates the tunneling oxide layer at the junction of the P / N regions, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer.

[0103] (3) At 800°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after the texturing in step (2), and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a first annealing at a temperature of 900°C and a second annealing at a temperature of 970°C, so that a phosphorus-diffused lightly doped layer is formed on the front side of the n-type silicon wafer, and the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ phosphorus-doped amorphous silicon layer on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ phosphorus-doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

[0104] (4) The PSG layer is removed using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer.

[0105] (5) A passivation layer is grown on the front and back sides of the n-type silicon wafer after being treated in step (4) by a thermal oxygen oxidation method, and a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layer on the front and back sides of the n-type silicon wafer by a PECVD method as an anti-reflection layer.

[0106] (6) printing silver paste on the N region and silver-aluminum paste on the P region of the back side of the n-type silicon wafer processed in step (5) by screen printing to form patterned metal electrodes respectively, and then performing contact treatment on the metal electrodes at 730° C. to obtain a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and then performing post-processing by light injection annealing to finally obtain the solar cell.

[0107] Example 3

[0108] This embodiment provides a solar cell, comprising an n-type silicon wafer having a resistivity of 2 Ω·cm. A discontinuously distributed tunneling oxide layer is provided on the back side of the n-type silicon wafer. The tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions are alternately arranged in sequence. A p+ doped layer is provided on the P region, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunneling oxide layer. An n+ doped polycrystalline silicon carbide layer is provided on the N region.

[0109] The tunneling oxide layer is a silicon oxide layer with a thickness of 3 nm; the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer with a doping concentration of 5×10 20 cm -3 and a thickness of 100 nm; the p+ doped polycrystalline silicon layer is a p+ boron doped polycrystalline silicon layer with a doping concentration of 5×10 20 cm -3 and a thickness of 200 nm; and the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer with a doping concentration of 2×10 21 cm -3 and a thickness of 100 nm.

[0110] The outer surface of the p+ doped polycrystalline silicon layer, the interval region (with a width of 60 μm) between the P region and the N region, and the outer surface of the n+ doped polycrystalline silicon carbide layer are sequentially provided with a back surface passivation layer and a back surface anti-reflection layer in a direction away from the n-type silicon wafer.

[0111] The back surface passivation layer is a silicon oxide layer with a thickness of 10 nm; and the back surface anti-reflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 90 nm.

[0112] The back surface passivation layer and the back surface anti-reflection layer provided on the p+ doped polycrystalline silicon layer are partially provided with a first slot, and a first back metal electrode is arranged in the first slot, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end of the first back metal electrode extends out of the back surface anti-reflection layer; the back surface passivation layer and the back surface anti-reflection layer provided on the n+ doped polycrystalline silicon carbide layer are partially provided with a second slot, and a second back metal electrode is arranged in the second slot, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end of the second back metal electrode extends out of the back surface anti-reflection layer; the first back metal electrode is a silver electrode, and the second back metal electrode is a silver electrode.

[0113] The front surface of the n-type silicon wafer is provided with a phosphorus extended light doping layer, a front surface passivation layer and a front surface anti-reflection layer in a direction away from the n-type silicon wafer; the surface phosphorus element concentration of the phosphorus extended light doping layer is 5×10 20 cm -3 , the diffusion sheet resistance is 200 Ω / sq, and the junction depth is 1.5 μm; the material of the front surface passivation layer is silicon oxide with a thickness of 10 nm; and the front surface anti-reflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 90 nm.

[0114] The embodiment also provides a preparation method of the TBC back contact solar cell, and the preparation method comprises the following steps:

[0115] (1) The n-type silicon wafer is alkaline polished to remove the mechanical damage layer on the front and back sides, and then cleaned by RCA cleaning method. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer are grown on the back side of the n-type silicon wafer by PECVD method. Then, a patterned laser window is opened by ultraviolet picosecond laser, and the laser window area is etched by KOH to remove the first mask layer and the p+ doped amorphous silicon layer in the laser window area, forming spaced grooves with a width of 1000 μm.

[0116] The material of the first mask layer is silicon oxide, and the thickness is 100 nm.

[0117] (2) A PECVD method is used to sequentially grow an n+ phosphorus-doped amorphous silicon layer with a thickness of 100 nm and a second mask layer with a thickness of 50 nm on the first mask layer treated in step (1) and the p+ doped amorphous silicon carbide layer in the first groove, and then a laser window is opened at the intersection of the P / N region using a 532 nm wavelength ultraviolet nanosecond laser, and the second mask layer, the n+ phosphorus-doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser window are wet-etched to form a channel with a width of 60 μm to disconnect and isolate the P / N region, and at the same time, the front side of the n-type silicon wafer is textured and cleaned to remove the second mask layer.

[0118] The second mask layer is made of silicon oxide; the channel penetrates the tunneling oxide layer at the junction of the P / N regions, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer.

[0119] (3) At 900°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after the texturing in step (2), and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a first annealing at a temperature of 930°C and a second annealing at a temperature of 1000°C, so that a phosphorus-diffused lightly doped layer is formed on the front side of the n-type silicon wafer, and the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ phosphorus-doped amorphous silicon layer on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ phosphorus-doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

[0120] (4) The PSG layer is removed using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer.

[0121] (5) A passivation layer is grown on the front and back sides of the n-type silicon wafer after being treated in step (4) by a thermal oxygen oxidation method, and a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layer on the front and back sides of the n-type silicon wafer by a PECVD method as an anti-reflection layer.

[0122] (6) printing silver paste on the N region and printing silver-aluminum paste on the P region on the back surface of the n-type silicon wafer treated in step (5) by a screen printing method to form patterned metal electrodes, respectively, then performing contact treatment on the metal electrodes at 520°C to obtain first back metal electrodes and second back metal electrodes, and one end of the first back metal electrodes forms ohmic contact with the p+ doped polysilicon layer, and one end of the second back metal electrodes forms ohmic contact with the n+ doped polysilicon carbide layer, and then performing post-treatment by a photo-injection annealing method, and finally obtaining the solar cell.

[0123] Example 4

[0124] The difference between this example and Example 1 is that the thickness of the tunneling oxide layer is 5 nm.

[0125] The rest of the product structure and parameters remain the same as in Example 1.

[0126] Example 5

[0127] The difference between this example and Example 1 is that the total thickness of the p+ doped polysilicon carbide layer is 20 nm.

[0128] The rest of the product structure and parameters remain the same as in Example 1.

[0129] Example 6

[0130] The difference between this example and Example 1 is that the total thickness of the p+ doped polysilicon carbide layer is 120 nm.

[0131] The rest of the product structure and parameters remain the same as in Example 1.

[0132] Example 7

[0133] The difference between this example and Example 1 is that the thickness of the p+ doped polysilicon layer is 30 nm.

[0134] The rest of the product structure and parameters remain the same as in Example 1.

[0135] Example 8

[0136] The difference between this example and Example 1 is that the thickness of the p+ doped polysilicon layer is 220 nm.

[0137] The rest of the product structure and parameters remain the same as in Example 1.

[0138] Comparative Example 1

[0139] The difference between this example and Example 1 is that no p+ doped polysilicon layer is provided, i.e. the growth of the p+ doped amorphous silicon layer in step (1) is not performed.

[0140] The rest of the product structure and parameters remain the same as in Example 1.

[0141] Comparative Example 2

[0142] The difference between this comparative example and Example 1 is that no p+ doped polycrystalline silicon carbide layer is provided, that is, no p+ doped amorphous silicon carbide layer is grown in step (1).

[0143] The rest of the product structure and parameters remain the same as in Example 1.

[0144] Comparative Example 3

[0145] The difference between this comparative example and Example 1 is that the p+ doped polycrystalline silicon carbide layer is replaced by a p+ doped polycrystalline silicon layer.

[0146] The rest of the product structure and parameters remain the same as in Example 1.

[0147] Comparative Example 4

[0148] The difference between this comparative example and Example 1 is that the P region and the N region are closely attached, that is, the tunneling oxide layer is a continuous layer.

[0149] The rest of the product structure and parameters remain the same as in Example 1.

[0150] Performance Testing

[0151] The photoelectric performance of the TBC back contact solar cells prepared in the above examples and comparative examples was tested under the following conditions: light intensity 1000 W / m 2 , test temperature 25±2℃.

[0152] The test results are shown in Table 1.

[0153] Table 1

[0154]

[0155]

[0156] analyze:

[0157] As can be seen from the above, the TBC back-contact solar cell provided by the present invention solves the problem of low efficiency caused by interface recombination between the metal electrode and the silicon substrate and the problem of conduction leakage between PNs, and has excellent photoelectric conversion efficiency.

[0158] It can be seen from Examples 1 and 4 that if the thickness of the tunnel oxide layer is too thick, the doping concentration of the P region and the N region into the silicon substrate will be too low, resulting in high string resistance and poor contact.

[0159] It can be seen from Example 1 and Examples 5-6 that if the thickness of the p+ doped polycrystalline silicon carbide layer is too small, the metal electrodes in the P region and the N region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting the passivation and contact; if the thickness of the p+ doped polycrystalline silicon carbide layer is too large, the parasitic absorption is high and the current is low.

[0160] It can be seen from Example 1 and Examples 7-8 that if the thickness of the p+ doped polysilicon layer is too small, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting passivation and contact; if the thickness of the p+ doped polysilicon layer is too large, the parasitic absorption is high and the current is low.

[0161] It can be seen from Example 1 and Comparative Example 1 that if the p+ doped polysilicon layer is not provided, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, damaging the tunneling layer, and affecting passivation and contact.

[0162] It can be seen from Example 1 and Comparative Example 2 that if the p+ doped polycrystalline silicon carbide layer is not provided, the metal electrodes in the P region and the N region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting passivation and contact.

[0163] It can be seen from Example 1 and Comparative Example 3 that if the p+ doped polycrystalline silicon carbide layer is replaced by a p+ doped polycrystalline silicon layer, that is, the p+ doped amorphous silicon carbide layer in step (1) is replaced by a p+ doped amorphous silicon layer, then due to the etching treatment in step (1), the p+ doped amorphous silicon layer reacts with the alkali, so that only the residual p+ doped polycrystalline silicon layer exists in the N region, which is subsequently converted into a small amount of n+ doped polycrystalline silicon layer, resulting in the N region slurry directly burning through the contact silicon substrate, the dark current density J0 is extremely large, and the contact is extremely large.

[0164] It can be seen from Example 1 and Comparative Example 4 that if the P region and the N region are tightly attached, the P region and the N region are directly connected, and electrons and holes recombine directly, which results in extremely low efficiency.

[0165] The applicant declares that while the above-described embodiments illustrate the process of the present invention, the present invention is not limited to the above-described process steps, nor does it imply that the present invention must rely on the above-described process steps for implementation. Persons skilled in the art should understand that any improvements to the present invention, equivalent substitutions for the raw materials used, additions of auxiliary ingredients, and selection of specific methods, etc., fall within the scope of protection and disclosure of the present invention.

Claims

1. A solar cell, characterized in that: The solar cell comprises a silicon substrate, a discontinuously distributed tunnel oxide layer is provided on the back of the silicon substrate, the tunnel oxide layer is divided into a plurality of P regions and a plurality of N regions, and the P regions and N regions are alternately arranged in sequence; A p+ doped layer is provided on the P region, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunnel oxide layer; an n+ doped polycrystalline silicon carbide layer is provided on the N region; A back passivation layer and a back anti-reflection layer are stacked on the outer surface of the p+ doped polycrystalline silicon layer, the spacing region between the P region and the N region, and the outer surface of the n+ doped polycrystalline silicon carbide layer in a direction away from the silicon substrate; A first back metal electrode is provided on the P region, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer on the P region; a second back metal electrode is provided on the N region, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer on the N region.

2. The solar cell according to claim 1, wherein The silicon substrate is an n-type silicon wafer; The resistivity of the n-type silicon wafer is 0.3-7Ω·cm.

3. The solar cell according to claim 1, wherein The tunneling oxide layer includes a silicon oxide layer; The thickness of the tunnel oxide layer is 0.5-3 nm.

4. The solar cell according to claim 1, wherein The p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer; The thickness of the p+ doped polycrystalline silicon carbide layer is 30-100 nm.

5. The solar cell according to claim 1, wherein The p+ doped polysilicon layer is a p+ boron doped polysilicon layer; The thickness of the p+ doped polysilicon layer is 50-200 nm.

6. The solar cell according to claim 1, wherein The n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer; The thickness of the n+ doped polycrystalline silicon carbide layer is 30-100 nm; The width of the discontinuity between adjacent P regions and N regions is 10-60 μm.

7. The solar cell according to claim 1, wherein The front surface of the silicon substrate is a suede structure, and a phosphorus-doped lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially arranged on the front surface in a direction away from the silicon substrate; The back passivation layer and the front passivation layer each independently comprise a silicon oxide layer and / or an aluminum oxide layer; The thickness of the back passivation layer and the front passivation layer are independently 2-10 nm.

8. The solar cell according to claim 7, characterized in that The back anti-reflection layer and the front anti-reflection layer each independently include any one of a silicon nitride layer, a silicon oxynitride layer or a silicon oxide layer, or a combination of at least two thereof; The thickness of the back anti-reflection layer and the front anti-reflection layer are independently 60-150 nm; The first back metal electrode and the second back metal electrode each independently include a silver electrode and / or an aluminum electrode.

9. The solar cell according to claim 7, wherein: The diffusion sheet resistance of the phosphorus-doped lightly doped layer is 200-500Ω / sq; The junction depth of the phosphorus-diffused lightly doped layer is 0.3-1.5 μm.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 9.

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