Semiconductor package

Abstract

The embodiment of the utility model provides a semiconductor packaging piece, which comprises a semiconductor tube core, an intermediary arranged below the semiconductor tube core, and a first contact for electrically coupling the semiconductor tube core to the intermediary, at least one second contact coupling the semiconductor die to the interposer; and a first underfill disposed between the semiconductor die and the interposer to surround the active and second contacts. The semiconductor die includes a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge. The first contacts are located within the first region, and the second contacts are disposed at die corners within the second region and are electrically floating in the semiconductor package. The second contact may anchor the underfill and protect the underfill at the edge of the die from rupture / delamination.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor package, and more particularly, to a semiconductor package including dummy structures. BACKGROUND

[0002] Semiconductor devices and integrated circuits for various electronic applications are typically fabricated from semiconductor wafers. Semiconductor dies of the semiconductor wafers are processed and packaged at the wafer level along with other electronic devices, and a variety of techniques have been developed for wafer level packaging. While existing semiconductor packages and methods of fabricating the same are generally adequate for their intended purposes, they are not in all respects satisfactory. SUMMARY

[0003] Embodiments of the present application provide a semiconductor package including a semiconductor die, an interposer disposed below the semiconductor die, a plurality of first contacts electrically coupling the semiconductor die to the interposer, at least one second contact coupling the semiconductor die to the interposer, and a first underfill disposed between the semiconductor die and the interposer to surround the first contacts and the at least one second contact. The semiconductor die includes a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge of the semiconductor die. The first contacts are located within the first region, the at least one second contact is disposed within a die corner of the second region, and the at least one second contact is electrically floating in the semiconductor package.

[0004] Embodiments of the present application provide a semiconductor package including a first package member, a second package member disposed below the first package member, a plurality of second contacts, and an underfill disposed between the first package member and the second package member. The first package member includes a plurality of active pads and a dummy pad structure including a plurality of first dummy pads disposed at a die corner and a plurality of second dummy pads disposed alongside the first dummy pads and between the active pads and a die edge. The second package member is electrically coupled to the first package member by a plurality of first contacts coupled to the active pads. The second contacts are coupled to the first dummy pads and anchor the second package member. The underfill laterally covers the first contacts and the second contacts, and the underfill contacts at least a portion of the second dummy pads.

[0005] Based on the above, the configuration of the semiconductor package of embodiments of the present application allows for reducing stress on the underfill at the die edge / corner, reducing or eliminating defects in the underfill due to stress, and improving the reliability of the semiconductor package.

[0006] In order to make the above features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments are described in detail below, and the detailed description is made with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A A schematic cross-sectional view of a semiconductor die is shown in accordance with some embodiments.

[0008] FIG. 1B A schematic plan view of a semiconductor die is shown in accordance with some embodiments.

[0009] FIGS. 2A-2D A schematic cross-sectional view of an intermediate step during a process of forming a semiconductor package is shown in accordance with some embodiments.

[0010] FIGS. 3A-3C A schematic enlarged view of some other embodiments of the structure in dashed box B is shown. FIG. 2D

[0011] REFERENCE NUMERALS

[0012] ​10: semiconductor package; 10': package; 22, 22A, 22B, 22C: dummy contact; 22A1, 22B1, 22C1: first end; 22A2, 22B2, 22C2: second end; 51: first underfill; 52: insulative encapsulant; 52t: surface; 53: second underfill; 66: contact; 88: second conductive contact; 100: semiconductor die; 100E: die edge; 100t, 101b: back surface; 101, 201: semiconductor substrate; 101a: active surface; 102: device layer; 103: interconnect structure; 104, 302: contact pad; 105: passivation layer; 105p: opening; 105t, 205t: outer surface; 106: conductive bump; 111: seal ring structure; 111t: surface; 113: test line structure; 113m: bump / probe mark; 113t, 120t: top surface; 120: first dummy pad; 121: second dummy pad; 122, 222: dummy bump; 200: interposer; 200E: edge; 201a, 300a: first side; 201b, 300b: second side; 203: substrate through via (TSV); 204: first contact pad; 205: first dielectric layer; 206: first conductive bump / second contact pad; 207: second dielectric layer; 208: second conductive bump; 221: dummy pad; 300: circuit substrate; 304: conductive terminal; 1031: conductive pattern; 1032: dielectric layer; 1111, 1131: conductive pad; 1111T: topmost conductive pad; 1112, 1132: via; 1131T: test pad; B: dashed box; D1, D2: dummy region; F1: forbidden zone; R1: first region; R2: second region; X, Y: axis. DETAILED DESCRIPTION

[0013] The following disclosure provides different embodiments or examples, for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented in order to provide a thorough description of the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of this disclosure. For example, in the following description, a first feature is formed "on" a second feature or is formed "on" a second feature, which can include embodiments where the first feature is formed directly on the second feature, or where the first feature is formed indirectly on the second feature with intervening features located therebetween. Additionally, the present disclosure can refer to, where appropriate, "one" or "another" embodiment(es) in the singular sense. Such references simply mean that the feature(s) can exist in at least one embodiment.

[0014] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0015] Flip chip assemblies include direct electrical connections of a die to a circuit carrier (e.g., interposer) using conductive bumps (e.g., solder bumps). For example, a flip chip assembly is fabricated by attaching conductive bumps of a die to a circuit carrier and applying an underfill between the die and the circuit carrier. The underfill between the die and the circuit carrier serves to increase the reliability of the resulting structure by reducing stress on the conductive bumps. During various processes, the die is subjected to many mechanical and / or thermal stresses. Unfortunately, particularly for large scale packages, the underfill at the edges of the die is susceptible to cracking / delamination due to stress. Such defects (e.g., cracking / delamination) can affect the reliability of the resulting structure. These and other problems are addressed and technical advantages are attained by embodiments of the present disclosure, including dummy pad (or defect prevention) structures of dummy bumps / pads formed near the corners / edges of the die outside of the encapsulation ring structure.

[0016] Embodiments will be described with respect to embodiments in the context of semiconductor packages, dummy pad structures thereof, and methods of forming the same. Aspects of the embodiments can be applied to dummy pad structures that can advantageously anchor underfill, thereby protecting the underfill at the edges of the die from cracking / delamination and also providing improved stress relief without significant impact on manufacturing processes, time, and cost. Moreover, roughening portions of the passivation layer near the edges / corners of the die will enhance adhesion between the die and the underfill. Various embodiments presented herein allow for reduced stress on the underfill at the edges / corners of the die, reduced or eliminated defects in the underfill due to stress, and improved reliability of the semiconductor package.

[0017] According to some embodiments, FIG. 1A A schematic cross-sectional view of a semiconductor die 100 is shown, FIG. 1B A schematic plan view of the semiconductor die 100 is shown. It should be noted that, for clarity, FIG. 1B are simplified and FIG. 1B All components of the semiconductor die 100 can not be shown. For example, FIG. 1B Active bumps in the first region and a passivation layer on the semiconductor die are not shown in FIG. 1.

[0018] Referring to FIG. 1A A semiconductor die 100 is provided. The semiconductor die 100 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), the like, or a combination thereof.

[0019] The semiconductor die 100 can be formed in a semiconductor wafer that can include different die regions that are singulated in subsequent steps to form a plurality of semiconductor dies 100. The semiconductor die 100 can be processed according to applicable fabrication processes to form an integrated circuit. In some embodiments, the semiconductor die 100 includes a semiconductor substrate 101, such as a doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 101 can include other semiconductor materials (e.g., germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof. According to some other embodiments, other substrates can be used, such as a multilayer or graded substrate. The semiconductor substrate 101 can have an active surface (or front side) 101a and a back surface (or back side) 101b opposite the active surface 101a.

[0020] In some embodiments, the semiconductor die 100 includes a device layer 102 formed in / on an active surface 101a of the semiconductor substrate 101. The device layer 102 can include a plurality of active / passive devices (not shown individually; e.g., transistors, diodes, capacitors, resistors, and / or the like). The device layer 102 can be formed by a front-end-of-line (FEOL) process and can be referred to as a FEOL layer. The device layer 102 can include an inter-layer dielectric (ILD) layer (not shown) formed on the active surface 101a of the semiconductor substrate 101 and surrounding the devices. The ILD layer can include one or more dielectric materials, such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), the like, or combinations thereof. The device layer 102 can include conductive plugs (not shown) extending through the ILD layer to electrically and physically couple to the devices. In some embodiments where the devices are transistors, the conductive plugs can be coupled to the gate and source / drain regions of the transistors.

[0021] With continued reference to FIG. 1A , the semiconductor die 100 can include an interconnect structure 103 formed on the device layer 102. The interconnect structure 103 can interconnect with the devices in the device layer 102 to form an integrated circuit. The interconnect structure 103 can be formed by a back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 103 is formed by alternating layers of dielectric (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias interconnecting the layers of conductive material and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). For example, the interconnect structure 103 includes conductive patterns 1031 and dielectric layers 1032 covering the conductive patterns 1031. The conductive patterns 1031 can include wires, conductive pads, and vias, among others, and can be formed in one or more dielectric layers 1032. The conductive patterns 1031 are electrically coupled to the devices in the device layer 102 by, for example, conductive plugs (not shown individually).

[0022] In some embodiments, the semiconductor die 100 includes contact pads 104 (e.g., aluminum pads, aluminum-copper pads, or the like) that are connected to the outside. The contact pads 104 are formed over the active side of the semiconductor die 100, e.g., in and / or on the interconnect structure 103. In some embodiments, the semiconductor die 100 includes a passivation layer 105 formed on the interconnect structure 103 and partially covering the contact pads 104, with openings 105p extending through the passivation layer 105 to the contact pads 104. In some embodiments, the passivation layer 105 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the semiconductor die 100 includes conductive bumps 106 extending through the passivation layer 105 to physically and electrically couple to a corresponding one of the contact pads 104. The conductive bumps 106 are electrically coupled to respective integrated circuits of the semiconductor die 100 and can be referred to as active (or functional) bumps. The conductive bumps 106 can be or include ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. In some embodiments, a solder material is deposited over the contact pads 104 and then heated by a reflow process to form the conductive bumps 106 that are generally spherical in shape. In some embodiments, the conductive bumps 106 are used to establish electrical contact between the semiconductor die 100 and an interposer, as will be described later in connection with FIG. 1C. FIGS. 2A-2B

[0023] Continuing to refer to FIG. 1A and to FIG. 1B , the semiconductor die 100 includes a first region Rl (or active / functional region) and a second region (or inactive / non-functional region) R2 surrounding the first region Rl. In some embodiments, in a top view, the first region Rl is a central region of the semiconductor die 100, while the second region R2 is a peripheral region of the semiconductor die 100. For example, the device layer 102 and structures above (e.g., the interconnect structure 103, the contact pads 104, and the conductive bumps 106) are disposed within the first region Rl. It should be noted that, for simplicity, FIG. 1B the conductive bumps 106 within the first region Rl are not shown in FIG. 1A, and the present disclosure is not limited to the number and configuration of the conductive bumps 106.

[0024] ​In some embodiments, the semiconductor die 100 includes one or more seal ring structures 111 that surround a perimeter of the first region Rl and are located between the first region Rl and the second region R2. For example, in a plan view, an inner boundary of the seal ring structure 111 defines an outer boundary of the first region Rl, and an area outside of an outer boundary of the seal ring structure 111 defines the second region R2. The seal ring structure 111 can be a closed loop around the perimeter of the first region Rl and act as a barrier to prevent moisture and chemicals from penetrating into the first region Rl. For example, the seal ring structure 111 protects devices in the device layer 102 and the interconnect structure 103 from contamination and prevents a stack of the conductive pattern 1031 and the dielectric layer 1032 from cracking or delaminating, for example, by providing stress relief.

[0025] The seal ring structure 111 can include multiple metal layers. In some embodiments, the seal ring structure 111 is formed simultaneously with the conductive pattern 1031 and can be substantially similar to the conductive pattern 1031 in composition and fabrication. For example, the seal ring structure 111 includes conductive pads 1111 and vias 1112 that land on a respective one of the conductive pads 1111 and substantially span a height of the seal ring structure 111, where the conductive pads 1111 and the vias 1112 are embedded in one or more dielectric layers 1032. In some embodiments, a topmost conductive pad 1111T in the seal ring structure 111 is at a same level as the contact pad 104 and can be covered at least laterally by the passivation layer 105. In some embodiments, a top surface of the topmost conductive pad 1111T is substantially flush (or coplanar) with a top surface of the passivation layer 105 within a process variation range. Alternatively, the topmost conductive pad 1111T is completely (or partially) covered by the passivation layer 105.

[0026] With continued reference to FIGS. 1A-1B , the semiconductor die 100 can include one or more test line structures 113 disposed within the second region R2 and outside of the seal ring structure 111. In a plan view, the test line structure 113 can be disposed between the seal ring structure 111 and the die edge 100E. The test line structure 113 can be used to verify characteristics of the semiconductor die 100, such as characteristics used for wafer acceptance testing (WAT). For example, upon initial formation, the test line structure 113 is electrically coupled to functional circuitry in the first region Rl; once the semiconductor die 100 is separated from a semiconductor wafer by a singulation process, the test line structure 113 can no longer be electrically coupled to functional circuitry in the first region Rl and can be electrically floating.

[0027] In some embodiments, the test line structures 113 include conductive pads 1131 and vias 1132 landing on corresponding ones of the conductive pads 1131, where the conductive pads 1131 and the vias 1132 are embedded in the dielectric layer 1032. The conductive pads 1131 and the vias 1132 can be fabricated simultaneously using methods such as a dual damascene process with the multi-layer interconnects in the interconnect structure 103. The topmost conductive pads, referred to as test pads 1131T or WAT pads, can be formed simultaneously and are at the same level as the contact pads 104. The test pads 1131T can be arranged in an array within the second region R2. The conductive pads 1131 and the vias 1132 can be substantially similar in composition and fabrication to the conductive patterns 1031, and the test pads 1131T can be substantially similar in composition and fabrication to the contact pads 104. The test pads 1131T can be partially covered by the passivation layer 105. For example, at least a portion of the top surface 113t of a respective test pad 1131T can be exposed in a touchable manner by an opening 105p of the passivation layer 105. In some embodiments, as a result of the probe test, bumps 113m (e.g., probe marks, as shown in the magnified view of FIG. 1A

[0028] In some embodiments, the test line structures 113 can be located in a scribe lane region of a semiconductor wafer, however, once the semiconductor dies 100 have been singulated from the semiconductor wafer, they are not necessary for the functionality of the semiconductor dies 100. As described above, the semiconductor dies 100 are formed in a semiconductor wafer that includes different die regions, for example, the semiconductor wafer can include a plurality of scribe lane regions between adjacent die regions, and the test line structures 113 can be placed in the scribe lane regions and used for testing or other functions. The scribe lane regions are formed by not placing functional structures (structures that are used by the semiconductor dies 100 once singulated from the semiconductor wafer) into regions that are intended for scribe lane regions. A probe card including a plurality of probe pins (not shown) can apply test signals to the test line structures 113 through the probe pins and receive responses from the test line structures 113. The probing can result in bumps 113m (e.g., probe marks) being created. In BEOL testing, the test line structures 113 can ensure process stability of various parameters. After the testing is completed, failed dies are identified and only known good dies are used in subsequent processes. The semiconductor wafer is then singulated by cutting along the scribe lane regions, resulting in individual semiconductor dies 100. In some embodiments, at least one of the test pads 1131T and underlying structures can remain in the resulting semiconductor dies 100 after the singulation process.

[0029] Continuing with reference to FIGS. 1A-1B ​In some embodiments, the semiconductor die 100 can include one or more dummy regions (e.g., Dl and D2) disposed within the second region R2 and outside the seal ring structure 111. The dummy regions (e.g., Dl and D2) can be blank regions that do not have functional structures used by the semiconductor die 100 or can be regions other than the distributed regions of the test line structures 113 within the second region R2. In some embodiments, in a plan view, the dummy regions (e.g., Dl or D2) are alongside the test line structures 113 along a length direction (e.g., Y-axis) of the respective test pads 1131T. For example, the dummy regions (e.g., Dl or D2) are disposed between the array of test pads 1131T and the die edge 100E. Alternatively, the dummy regions are alongside the test line structures along the X-axis or can be L-shaped extending along both the X-axis and the Y-axis.

[0030] Exemplary shapes of the dummy regions (e.g., Dl and D2) can be designed to substantially occupy a rectangular region or a square region, but other shapes can be employed in accordance with various embodiments. In the illustrated embodiments, in a plan view, two of the dummy regions Dl and D2 are disposed in the upper left and upper right portions of the semiconductor die 100. In some embodiments, the dummy regions (e.g., Dl and D2) have different sizes and can have an asymmetric configuration. The configuration of the dummy regions can depend on the distribution of the test line structures 113 within the second region R2. Alternatively, one or more than two dummy regions can also be configured within the second region R2. The dummy regions can have the same size and can have a symmetric configuration. It is noted that the disclosure is not limited to the number, shape, and configuration of the dummy regions.

[0031] The semiconductor die 100 can include one or more forbidden zones Fl outside the seal ring structure 111 and within the second region R2. The forbidden zones Fl can be considered as die corner zones and can be included in the dummy areas (e.g., Dl and / or D2). Since the forbidden zones Fl are regions that can sustain greater stress during / after processing (e.g., die sawing and packaging), the functional circuitry of the semiconductor die 100 can be excluded from the forbidden zones Fl. The forbidden zones Fl can be located in one or more corners of the semiconductor die 100. It should be noted that two forbidden zones Fl are shown at the corners of the die as an example, the forbidden zones can be arranged on each die corner according to other embodiments, thus the number of forbidden zones Fl can be modified according to product requirements. The exemplary shape of the forbidden zones Fl can be designed to substantially occupy a rectangular area or a square area at the corners of the die, but other shapes can also be employed. The exemplary size of the forbidden zones Fl can have a profile (e.g., LXl (measured along the X-axis) and LYl (measured along the Y-axis)) ranging from about 60 pm to about 250 pm (e.g., about 155 pm). But other values can also be employed depending on design rules and specifications. In some embodiments, the forbidden zones Fl at each die corner can have the same size. Alternatively, the sizes of the forbidden zones Fl at different die corners can be different, that is, the forbidden zones Fl at the corners of the die can have an asymmetric configuration.

[0032] Still referring to FIGS. 1A-1B One or more first dummy pads 120 can be disposed within the dummy areas (e.g., Dl and / or D2) outside the forbidden zones Fl. The first dummy pads 120 can be electrically floating in the semiconductor die 100. In some embodiments, the first dummy pads 120 have the same size and can be arranged in an array. Depending on the size of the free space in the dummy areas, the first dummy pads 120 can or can not be disposed within the dummy areas. In the illustrated embodiment, the first dummy pads 120 are disposed within the dummy area Dl, while the dummy area D2 does not have first dummy pads. For example, since the size of the dummy area D2 substantially matches the size of the forbidden zones Fl, there is not enough space in the dummy area D2 to configure the first dummy pads. Alternatively, the first dummy pads 120 can be disposed within each dummy area when the corresponding dummy area is large enough to accommodate the first dummy pads 120. In some embodiments, the total area of the first dummy pads 120 is greater than 15% of the total area of the dummy area (e.g., Dl) in which the first dummy pads 120 are located. It should be noted that the number, size, and configuration of the first dummy pads 120 shown here are examples only and do not constitute a limitation on the disclosure.

[0033] The first dummy pads 120 can be formed concurrently with the contact pads 104 in the first region Rl and can be substantially similar to the contact pads 104 in terms of composition. In some embodiments, the first dummy pads 120 are formed directly on the topmost layer of the dielectric layer 1032. Alternatively, the first dummy pads 120 and the contact pads 104 can have different materials, where the material of the first dummy pads 120 can be conductive or non-conductive. The passivation layer 105 can partially cover the respective first dummy pads 120, and at least a portion of the top surface 120t of the respective first dummy pads 120 can be exposed in an accessible manner by the openings 105p of the passivation layer 105. Since the respective test pads 1131T can have the probe marks 113m after the probe test, the top surface 120t of the first dummy pads 120 can be smoother than the top surface 113t of the test pads 1131T. The openings 105p of the passivation layer 105 that expose the first dummy pads 120 arranged in the one or more dummy regions can provide a rough topography that facilitates adhesion between the underfill at the corners of the semiconductor die 100 and the semiconductor die 100 in subsequent processes, which will be described later in conjunction with FIGS. 6A-6C. FIG. 2B Details thereof are described.

[0034] In some embodiments, the second dummy pads 121 and the dummy bumps 122 formed in a one-to-one correspondence manner on the second dummy pads 121 can be disposed within the respective forbidden regions Fl, where the second dummy pads 121 and the dummy bumps 122 are electrically floating in the semiconductor die 100. In some embodiments, the second dummy pads 121 are formed directly on the topmost layer of the dielectric layer 1032 and can be partially covered by the passivation layer 105. The dummy bumps 122 can extend through the openings 105p of the passivation layer 105 to land on the second dummy pads 121. In some embodiments, the second dummy pads 121 and the dummy bumps 122 are the conductive features closest to the die edge 100E. In plan view, the dummy bumps 122 can be arranged in an array within the forbidden regions Fl. In some embodiments, the dummy bumps 122 have a distribution area that is smaller than the distribution area of the first dummy pads 120 in the respective dummy region (Dl or D2). For example, the total area of the dummy bumps 122 can be greater than 1.64% of the total area of the dummy region (e.g., Dl or D2) in which the dummy bumps 122 are disposed.

[0035] The second dummy pad 121 can be formed at the same time as the first dummy pad 120, and the composition of the second dummy pad 121 can be substantially similar to the first dummy pad 120. The first dummy pad 120, the second dummy pad 121, and the contact pad 104 can have the same size. Alternatively, the first and second dummy pads (120 and 121) have different sizes from the contact pad 104. In an embodiment, the first dummy pad 120 has a different size from the second dummy pad 121. In some embodiments, the second dummy pad 121 and the dummy bump 122 are formed at the same time as the contact pad 104 and the active bump 106, respectively. The active bump 106 and the dummy bump 122 can have the same size or can have different sizes. The second dummy pad 121 and the dummy bump 122 can be substantially similar to the contact pad 104 and the active bump 106, respectively, in composition and fabrication. For example, the dummy bump 122 is a solder bump. Alternatively, the dummy bump is made of a different material from the active bump 106.

[0036] In some embodiments, the dummy bump 122 is omitted, and only the second dummy pad 121 is located within the forbidden zone Fl, thus, FIG. 1A One of the dummy bumps 122 in the dummy region D2 is shown in dashed line to indicate that it can or can not be present. In some embodiments, at least one dummy bump 122 is disposed on the first dummy pad 120 outside the forbidden zone Fl and within a dummy region (e.g., Dl), thus, FIG. 1A The dummy bump 122 outside the forbidden zone Fl and within the dummy region Dl is shown in dashed line to indicate that it can or can not be present. In some other embodiments, the dummy bump 122 lands on all of the first and second dummy pads 120 and 121. The number and configuration of the dummy bumps 122 shown here are merely examples and do not constitute a limitation on the disclosure. The above examples are provided for illustrative purposes only and the semiconductor die 100 can use fewer or additional components in other embodiments.

[0037] FIGS. 2A-2D Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor package are shown, in accordance with some embodiments. Although the method embodiments are discussed as being performed in a particular order, other embodiments can be performed in any logical order.

[0038] Referring to FIG. 2A and referring to FIG. 1A The semiconductor die 100 and the interposer 200 can be provided, respectively. The semiconductor die 100 is attached to the interposer 200, and the semiconductor die 100 and the interposer 200 are encapsulated in a mold compound 202. FIG. 1AThe semiconductor die 100 described in the Background section is substantially the same, and therefore its details are not repeated for the sake of brevity. The intermediary 200 described below is exemplary and can be replaced by a semiconductor device, an integrated circuit die structure, an integrated circuit package, or any type of packaging member. The intermediary 200 can be formed in a semiconductor wafer that is singulated in subsequent steps to form a plurality of intermediaries 200. The intermediary 200 can be processed according to applicable manufacturing processes. For example, the intermediary 200 includes a semiconductor substrate 201. In some embodiments, the semiconductor substrate 201 is similar to the semiconductor substrate 101 described above with reference to the Background section. FIG. 1A The semiconductor substrate 101 of the semiconductor die 100 described above is similar, and therefore its description is not repeated here. The intermediary 200 can or can not include active and / or passive devices formed in / on the semiconductor substrate 201. In some embodiments, the intermediary 200 includes a through substrate via (TSV) 203 extending through the semiconductor substrate 201. The TSV 203 can include a conductive material, such as copper, an alloy, or the like.

[0039] The intermediary 200 can include first contact pads 204 formed on the first side 201a of the semiconductor substrate 201 and electrically coupled to the TSVs 203. In the illustrated embodiment, each first contact pad 204 is in physical and electrical contact with one of the TSVs 203. In some embodiments, the intermediary 200 includes interconnect structures (not shown) formed on the first side 201a of the semiconductor substrate 201 and interposed between the first contact pads 204 and the TSVs 203. The intermediary 200 can include a first dielectric layer 205 overlying the first side 201a of the semiconductor substrate 201 and partially covering the first contact pads 204, where an opening of the first dielectric layer 205 exposes at least a portion of each first contact pad 204 in an accessible manner. The first dielectric layer 205 can be a passivation film or can include any suitable dielectric material(s), such as an oxide, a nitride, a polymer (e.g., polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or the like), or the like. In some embodiments, the intermediary 200 includes first conductive bumps (or first active bumps) 206 formed on the first contact pads 204. The first conductive bumps 206 can be similar to the conductive bumps 106 described above with reference to the Background section. FIG. 1A The conductive bumps 106 of the semiconductor die 100 described above are similar, and therefore their description is not repeated here. In some embodiments, not every first contact pad 204 has a first conductive bump 206 formed thereon, e.g., a portion of the first contact pads 204 do not have a first conductive bump 206 formed thereon.

[0040] Continuing with reference to FIG. 2A andFIG. 1A , the interposer 200 may include a dummy pad 221 and a dummy bump 222 formed on the dummy pad 221. For example, the dummy pad 221 is partially covered by the first dielectric layer 205, the opening of the first dielectric layer 205 may expose at least a portion of the dummy pad 221 in an accessible manner, and the dummy bump 222 may extend into the opening of the first dielectric layer 205 to land on the dummy pad 221. In some embodiments, the dummy pad 221 and the dummy bump 222 are arranged near the edge 200E of the interposer 200. The position of the dummy bump 222 may correspond to the position of the dummy bump 122 of the semiconductor die 100. It should be noted that not every one of the dummy bumps of the semiconductor die corresponds to any one of the dummy bumps of the interposer, and vice versa, the details of which will be discussed later in conjunction with FIGS. 3A-3C Provide a description.

[0041] The dummy pad 221 and the dummy bump 222 can be electrically floating in the interposer 200. In some embodiments, the dummy pad 221 is formed directly on the first side 201a of the semiconductor substrate 201. In some embodiments where the interconnect structure is formed between the semiconductor substrate 201 and the first dielectric layer 205, the dummy pad 221 is formed directly on top of the interconnect dielectric layer. In some embodiments, no conductive features are formed directly below the dummy pad 221. The dummy pad 221 and the dummy bump 222 can be respectively formed as described above with reference to FIG. FIG. 1A The dummy pad (121) and the dummy bump (122) are similar and will not be described again here.

[0042] Reference FIG. 2B And refer to FIG. 2A , the semiconductor die 100 may be coupled to the interposer 200. It should be noted that although FIG. 2B A single semiconductor die 100 is shown bonded to interposer 200, but more than one semiconductor die may be bonded to interposer 200 according to some embodiments. For example, semiconductor die 100 is first aligned with interposer 200, with conductive bumps 106 of semiconductor die 100 in contact with first conductive bumps 206 and dummy bumps 122 of semiconductor die 100 in contact with dummy bumps 222. One or more reflow operations may be performed to reflow the bumps to form first conductive (or active) contacts 66 and dummy contacts (e.g., second contacts) 22, respectively. For example, a thermal operation is performed to melt the solder material and produce generally circular solder contacts, with some solder contacts in a first region coupled to contact pads (104 and 204) and other solder contacts in a second region coupled to dummy pads (121 and 221).

[0043] In some embodiments, a first underfill 51 is formed between the semiconductor die 100 and the interposer 200 to surround the first conductive contacts 66 and the dummy contacts 22. The first underfill 51 can be formed by a capillary flow process after the semiconductor die 100 is attached to the interposer 200 or can be formed by an appropriate deposition method prior to attaching the semiconductor die 100. In some embodiments, the first underfill 51 extends upward to cover at least a lower portion of the die edge 100E. In some embodiments, the first underfill 51 is in direct contact with an outer surface of the passivation layer 105 of the semiconductor die 100 and the first dielectric layer 205 of the interposer 200. The first underfill 51 can extend into openings of the passivation layer 105 and the first dielectric layer 205 to be in direct contact with surfaces of the contact pads and dummy pads (e.g., 120 and 204) that are exposed in an accessible manner prior to the formation of the first underfill 51. In some embodiments, the first underfill 51 is in direct contact with surfaces (e.g., 111t and 113t) of the seal ring structure 111 and the test line structure 113 that are exposed in an accessible manner prior to the formation of the first underfill 51.

[0044] The dummy contacts 22 formed at the peripheral region of the semiconductor die 100 can anchor the first underfill 51, thereby protecting the first underfill 51 at the die edge 100E from cracking / delamination and also providing improved stress relief without significant impact on manufacturing process, time and cost. Since the passivation layer 105 of the semiconductor die 100 has a rough topography by forming openings (e.g., 105p as labeled in FIG. 1) of the passivation layer 105 that expose the first dummy pads 120, the adhesion between the first underfill 51 at the peripheral region of the die and the semiconductor die 100 can be enhanced, thereby preventing cracks from reaching the first region of the semiconductor die 100. FIG. 1A The first dummy pads 120, the dummy contacts 22, and / or the dummy pads (121 and 221) coupled to the dummy contacts 22 can be considered as dummy pad structures, respectively or collectively. It should be appreciated that defects (e.g., cracking and delamination) caused by stress are most likely to occur near the corners of the die, which are most sensitive to die failure. The dummy pad structures can protect the semiconductor die 100 from potential damage caused by defects resulting from stress.

[0045] Referring to FIG. 2C and referring to FIG. 2BAn insulative encapsulant 52 can be formed on the interposer 200 to cover the semiconductor die 100 and the first underfill 51. The insulative encapsulant 52 can be a molding compound, a molded underfill, an epoxy, or the like, and can be applied by compression molding, transfer molding, or the like. In some embodiments, the insulative encapsulant 52 is formed by forming a layer of encapsulation material on the interposer 200 to bury the semiconductor die 100 and the first underfill 51, curing the encapsulation material, and selectively performing a planarization process (e.g., chemical mechanical polishing (CMP), lapping, etching, combinations thereof, or the like) on the encapsulation material to level the encapsulation material with the semiconductor die 100. For example, a surface 52t of the insulative encapsulant 52 is substantially level (or coplanar) with a back surface 100t of the semiconductor die 100 within a process variation range. Alternatively, the insulative encapsulant 52 can be omitted.

[0046] In some embodiments, a second contact pad 206 is formed on a second side 201b of the semiconductor substrate 201 and electrically coupled to the TSV 203, where the second side 201b is opposite to the first side 201a. In some embodiments, a planarization process (e.g., CMP, lapping, etching, combinations thereof, or the like) is performed on the semiconductor substrate 201 to expose the TSV 203 prior to forming the second contact pad 206. In some embodiments, an interconnect structure (not shown) is formed on the second side 201b of the semiconductor substrate 201 and interposed between the second contact pad 206 and the TSV 203. In some embodiments, a second dielectric layer 207 is formed on the second side 201b of the semiconductor substrate 201 and partially covers the second contact pad 206. In some embodiments, a second conductive bump (or second active bump) 208 is formed on the second contact pad 206. A size of a respective second conductive bump 208 can be larger than a size of a respective first conductive bump 206. The second conductive bump 208 can be a BGA connection, a solder ball, a metal stud, a C4 bump, a micro bump, a bump formed by ENEPIG, or the like. In some embodiments, a singulation process is performed to sever the insulative encapsulant 52 (if present) and the interposer 200, and the resulting structure can be considered as a chip-on-wafer (CoW) package 10'.

[0047] Referring to FIG. 2D and referring to FIG. 2C , FIG. 2CThe structures shown are selectively bonded to a circuit substrate 300 through the second conductive bumps 208. The circuit substrate 300 can be any suitable packaging substrate, such as a printed circuit board (PCB), an organic substrate, a ceramic substrate, a motherboard, etc. The circuit substrate 300 can be used to interconnect the CoW package 10’ with other packages / devices to form a functional circuit. The circuit substrate 300 has a first side 300a that is bonded to the CoW package 10’ and a second side 300b opposite the first side 300a. In some embodiments, the circuit substrate 300 includes contact pads 302 formed on the first side 300a and can (or can not) include conductive terminals 304 formed on the second side 300b. The conductive terminals 304 can be BGA connections, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG-formed bumps, etc. The respective conductive terminals 304 can be larger in size than the respective second conductive bumps 208.

[0048] In some embodiments, the second conductive bumps 208 of the CoW package 10’ are placed on the contact pads 302 and a reflow process can be performed to reflow the second conductive bumps 208 to form second conductive joints (e.g., solder joints) 88 that couple the second contact pads 206 of the interposer 200 to the contact pads 302 of the circuit substrate 300. In some embodiments, a second underfill 53 is formed in the void between the circuit substrate 300 and the interposer 200 to surround the second conductive joints 88. In some embodiments, the second underfill 53 extends upward to cover at least a lower portion of the edge 200E of the interposer 200. Alternatively, the second underfill 53 can be omitted. FIG. 2D The structures shown can be semiconductor packages 10 that can be considered three-dimensional integrated circuit (3DIC) packages or chip-on-wafer-on-substrate (CoWoS) packages. CoWoS packages can be used for a variety of applications including artificial intelligence, machine learning, 5G networks, etc. The conductive terminals 304 of the semiconductor packages 10 can be used to electrically connect the semiconductor packages 10 to a motherboard (not shown) or another device component of an electrical system.

[0049] FIGS. 3A-3C Some other embodiments of the structures in dashed box B are shown in enlarged schematic views. Unless otherwise noted, the materials and formation methods of the components in these embodiments are substantially the same as those in the embodiments shown in FIGS. 1-3, and the components are indicated by like reference numerals. FIG. 2D Some other embodiments of the structures in dashed box B are shown in enlarged schematic views. Unless otherwise noted, the materials and formation methods of the components in these embodiments are substantially the same as those in the embodiments shown in FIGS. 1-3, and the components are indicated by like reference numerals. FIGS. 1A-2D Some other embodiments of the structures in dashed box B are shown in enlarged schematic views. Unless otherwise noted, the materials and formation methods of the components in these embodiments are substantially the same as those in the embodiments shown in FIGS. 1-3, and the components are indicated by like reference numerals.

[0050] Reference is made to FIG. 3A and FIG. 2D , FIG. 3AThe structure shown is FIG. 2D The structure depicted in dashed box B of FIG. 1 differs in that dummy contact 22A has one end directly landed on passivation layer 105 of semiconductor die 100. For example, dummy contact 22A has a first end 22A1 directly coupled to outer surface 105t of passivation layer 105 of semiconductor die 100, and a second end 22A2, opposite first end 22A1, directly landed on dummy pad 221 of interposer 200. Substantially the entire surface of first end 22A1 may be in physical contact with passivation layer 105. Second end 22A2 of dummy contact 22A may pass through an opening in first dielectric layer 205 to land on dummy pad 221, allowing dummy contact 22A to directly contact the inner sidewalls and top surface of first dielectric layer 205. The area of ​​first end 22A1 directly connected to passivation layer 105 may be larger than the area of ​​second end 22A2 directly connected to dummy pad 221. In some embodiments, dummy contact 22A is one of the dummy contacts closest to die edge 100E.

[0051] Reference FIG. 3B And refer to FIG. 3A , FIG. 3B The structure shown is FIG. 3A The differences in the illustrated structure include dummy contact 22B having one end directly landed on first dielectric layer 205 of interposer 200. For example, dummy contact 22B has a first end 22B1 that lands directly on second dummy pad 121 of semiconductor die 100, and a second end 22B2 that is opposite first end 22B1 and directly coupled to outer surface 205t of first dielectric layer 205 of interposer 200. Substantially the entire surface of second end 22B2 can be in physical contact with first dielectric layer 205. The area of ​​second end 22B2 directly connected to first dielectric layer 205 can be larger than the area of ​​first end 22B1 directly connected to second dummy pad 121. In some embodiments, dummy contact 22B is the one of the dummy contacts closest to die edge 100E.

[0052] Reference FIG. 3C And refer to FIG. 3A , FIG. 3C The structure shown is FIG. 3AThe differences between the structures shown include dummy contacts 22C having opposite ends that land directly on first dielectric layer 205 of interposer 200 and passivation layer 105 of semiconductor die 100, respectively. For example, dummy contact 22C has a first end 22C1 that is directly coupled to an outer surface 105t of passivation layer 105 and a second end 22C2 that is opposite first end 22C1 and is directly coupled to an outer surface 205t of first dielectric layer 205. Substantially the entire surface of first end 22C1 can be in physical contact with passivation layer 105 and substantially the entire surface of second end 22C2 can be in physical contact with first dielectric layer 205. The area of second end 22C2 can be substantially equal to the area of first end 22C1. In some embodiments, dummy contact 22C is one of the dummy contacts closest to die edge 100E.

[0053] Semiconductor die 100 can include any combination of dummy contacts (e.g., 22, 22A, 22B, and / or 22C) disposed in the peripheral region of semiconductor die 100. By configuring dummy contacts at the die corners, the resulting structure that anchors first underfill 51 can better mitigate stresses accumulated during thermal cycling and die separation processes. That is, dummy contacts (e.g., 22, 22A, 22B, and / or 22C) can anchor first underfill 51, which can protect first underfill 51 at die edge 100E from cracking / delamination and also can provide improved stress relief without significant impact on manufacturing processes, time, and cost. Embodiments presented herein allow for reducing or eliminating defects (e.g., cracks and / or delamination) generated in semiconductor package 10, particularly around the die corners, and improving the reliability of semiconductor package 10.

[0054] Other features and processes can also be included. For example, test structures can be included to assist in verifying testing of 3D packages or 3DIC devices. Test structures can include, for example, test pads formed on a redistribution layer or substrate that allow for testing of 3D packages or 3DICs, using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0055] According to some embodiments, a semiconductor package includes a semiconductor die, an interposer disposed below the semiconductor die, a first contact electrically coupling the semiconductor die to the interposer, at least one dummy contact coupling the semiconductor die to the interposer, and a first underfill disposed between the semiconductor die and the interposer around the active and dummy contacts. The semiconductor die includes a first region, a seal ring region around the first region, and a second region between the seal ring region and a die edge. The first contact is located within the first region, and the dummy contact is disposed in a corner of the die within the second region and is electrically floating in the semiconductor package.

[0056] In some embodiments, the semiconductor die further includes a plurality of first dummy pads and a plurality of second dummy pads disposed within the second region and a passivation layer extending across the first region, the sealing ring region, and the second region, the at least one second contact lands on one of the second dummy pads, and the passivation layer partially covers the first dummy pads and the second dummy pads. In some embodiments, the first underfill extends into a plurality of openings of the passivation layer to be in direct contact with the first dummy pads. In some embodiments, the semiconductor die further includes a semiconductor substrate and an interconnect structure disposed between the semiconductor substrate and the passivation layer, and the first dummy pads and the second dummy pads are in direct contact with interconnect dielectric layers of the interconnect structure. In some embodiments, the semiconductor die further includes at least one test pad disposed within the second region and including a probe mark, and the first underfill directly covers the probe mark. In some embodiments, the at least one test pad includes an array of a plurality of test pads disposed within the second region, the second region includes a dummy area outside of a distribution area of the array of test pads, and the dummy area includes a forbidden area where the at least one second contact is located. In some embodiments, the semiconductor die further includes an array of a plurality of dummy pads disposed in the dummy area outside of the forbidden area, wherein a distribution area of the array of dummy pads in the dummy area is greater than an area of the at least one second contact in the dummy area. In some embodiments, the at least one second contact includes a first end and a second end opposite to the first end and connected to a dummy pad of the interposer, and substantially an entirety of the first end is directly connected to a passivation layer of the semiconductor die. In some embodiments, the at least one second contact includes a first end connected to a dummy pad of the semiconductor die and a second end opposite to the first end, and substantially an entirety of the second end is directly connected to a dielectric layer of the interposer. In some embodiments, the at least one second contact includes a first end and a second end opposite to the first end, substantially an entirety of the first end is directly connected to a passivation layer of the semiconductor die, and substantially an entirety of the second end is directly connected to a dielectric layer of the interposer. In some embodiments, the semiconductor package further includes a circuit substrate disposed below the interposer and electrically coupled to the interposer through a plurality of solder joints and a second underfill disposed between the interposer and the circuit substrate and surrounding the solder joints.

[0057] According to some alternative embodiments, a semiconductor package includes a first package member, a second package member disposed below the first package member, a dummy contact, and an underfill disposed between the first and second package members. The first package member includes an active pad and a dummy pad structure including a first dummy pad disposed at a corner of a die and a second dummy pad disposed alongside the first dummy pad and between the active pad and an edge of the die. The second package member is electrically coupled to the first package member by a first contact coupled to the active pad. The dummy contact is coupled to the first dummy pad and anchors the second package member. The underfill laterally covers the first contact and the dummy contact and is in contact with at least a portion of the second dummy pad.

[0058] In some embodiments, the first package member further includes a seal ring structure separating the active pad from the first dummy pad and the second dummy pad. In some embodiments, the first package member further includes a passivation layer with an opening, the passivation layer partially covering the first dummy pad, the second dummy pad, and the active pad, and the underfill extends into a portion of the opening of the passivation layer to be in direct contact with the second dummy pad. In some embodiments, the first dummy pad, the second dummy pad, and the active pad are disposed at a same level in the first package member and include a same material.

[0059] According to some alternative embodiments, a method of manufacturing a semiconductor package includes providing a semiconductor die and an interposer, respectively, wherein the semiconductor die includes an active bump in a first region, a seal ring structure in a seal ring region surrounding the first region, and a dummy bump in a second region between the seal ring region and an edge of the die; coupling the semiconductor die to the interposer by reflowing the active bump and the dummy bump to form a first contact and a dummy contact, respectively, wherein the semiconductor die is electrically coupled to the interposer by the first contact, and the dummy contact coupled to the semiconductor die and the interposer is electrically floating; and forming an underfill between the semiconductor die and the interposer to surround the first contact and the dummy contact.

[0060] In some embodiments, providing the semiconductor die includes roughening a portion of a passivation material layer by forming a plurality of openings to expose at least a portion of a plurality of dummy pads of the semiconductor die, wherein the dummy pads are disposed within the second region and proximate to the dummy bumps, and after forming the underfill, the underfill extends into the openings to contact the portion of the dummy pads. In some embodiments, coupling the semiconductor die to the interposer includes reflowing the dummy bumps of the semiconductor die to form the second contacts, wherein at least one of the second contacts has one end that is substantially integrally directly connected to a passivation layer of the semiconductor die. In some embodiments, coupling the semiconductor die to the interposer includes reflowing the dummy bumps of the semiconductor die to form the second contacts, wherein at least one of the second contacts has one end that is substantially integrally directly connected to a dielectric layer of the interposer. In some embodiments, coupling the semiconductor die to the interposer includes reflowing the dummy bumps of the semiconductor die to form the second contacts, wherein at least one of the second contacts has opposite ends, and the opposite ends are substantially integrally in direct contact with the semiconductor die and a dielectric layer of the interposer, respectively.

[0061] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and not to limit them; although the embodiments of the present application are described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor package, characterized in that: include: a semiconductor die comprising a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge of the semiconductor die; an interposer disposed below the semiconductor die; a plurality of first contacts electrically coupling the semiconductor die to the interposer, the first contacts being located within the first region; at least one second contact coupling the semiconductor die to the interposer, the at least one second contact being disposed at a corner of the die within the second region and electrically floating in the semiconductor package; as well as A first underfill is disposed between the semiconductor die and the interposer to surround the first contact and the at least one second contact.

2. The semiconductor package according to claim 1, wherein The semiconductor die further comprises: a plurality of first dummy pads and a plurality of second dummy pads arranged in the second region, wherein the at least one second contact lands on one of the second dummy pads; and A passivation layer extends across the first region, the seal ring region, and the second region, and the passivation layer partially covers the first dummy pad and the second dummy pad.

3. The semiconductor package according to claim 2, wherein: The first underfill extends into the plurality of openings in the passivation layer to directly contact the first dummy pads.

4. The semiconductor package according to claim 1, wherein The semiconductor die further comprises: At least one test pad is disposed in the second region and includes a probe mark, and the first underfill directly covers the probe mark.

5. The semiconductor package according to claim 4, wherein The at least one test pad includes an array of multiple test pads arranged in the second area, the second area includes a dummy area outside the distribution area of ​​the array of the test pads, and the dummy area includes a prohibited area where the at least one second contact is located.

6. The semiconductor package according to claim 1, wherein The at least one second contact includes a first end connected to a dummy pad of the semiconductor die and a second end opposite to the first end, and substantially the entirety of the second end is directly connected to the dielectric layer of the interposer.

7. The semiconductor package according to claim 1, wherein The at least one second contact includes a first end and a second end opposite to the first end, the first end is substantially entirely directly connected to the passivation layer of the semiconductor die, and the second end is substantially entirely directly connected to the dielectric layer or dummy pad of the interposer.

8. The semiconductor package according to claim 1, wherein Also includes: a circuit substrate disposed below the interposer and electrically coupled to the interposer via a plurality of solder joints; as well as A second underfill is disposed between the interposer and the circuit substrate and surrounds the solder joints.

9. A semiconductor package, characterized in that: include: The first packaging component comprises: a plurality of active pads; and a dummy pad structure comprising a plurality of first dummy pads disposed at corners of the die and a plurality of second dummy pads disposed beside the first dummy pads and between the active pads and an edge of the die; a second packaging member disposed below the first packaging member and electrically coupled to the first packaging member via a plurality of first contacts coupled to the active pad; a plurality of second contacts coupled to the first dummy pad and anchoring the second packaging component; and An underfill is disposed between the first packaging member and the second packaging member and laterally covers the first contact and the second contact, wherein the underfill contacts at least a portion of the second dummy pad.

10. The semiconductor package according to claim 9, wherein The first packaging component further includes a sealing ring structure separating the active pad from the first dummy pad and the second dummy pad.

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