Semiconductor structure

Abstract

The utility model provides a semiconductor structure. A semiconductor structure includes a first fin extending along an X direction and a second fin parallel to the first fin and spaced apart from the first fin along a Y direction perpendicular to the X direction. Each fin is formed with a first device region and a second device region arranged along the X direction; an isolation region disposed between the plurality of fins; an isolation structure disposed between the plurality of device regions in each fin; and an isolation layer disposed under the plurality of fins. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device region from the second device region in each fin.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor structure's back side isolation. BACKGROUND

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to produce low-cost, high-performance, and low-power integrated circuits (ICs). To date, this demand has been largely met by scaling down the size of semiconductor ICs (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Thus, achieving continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing flows and techniques.

[0003] Multiple gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing OFF-state current, and reducing short channel effects (SCE). One multiple gate device that has been introduced is the fin field-effect transistor (FinFET). FinFETs get their name from the fin-shaped structure that extends from the substrate on which the structure is formed and is used to form the FET channel. Another multiple gate device is the gate-all-around (GAA) transistor, which was introduced in part to address performance challenges associated with FinFETs. GAA devices get their name from their gate structure, which extends completely around the channel, providing better electrostatic control than FinFETs. FinFET devices and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. Moreover, the three-dimensional structure of such devices allows them to be aggressively scaled while maintaining gate control and reducing short channel effects. SUMMARY

[0004] The semiconductor structure includes a first fin extending along an X direction and a second fin parallel to the first fin and spaced apart from the first fin along a Y direction perpendicular to the X direction. Each of the first fin and the second fin is formed with a first device region and a second device region arranged along the X direction. The semiconductor structure includes an isolation region disposed between the first fin and the second fin, an isolation structure disposed between the first device region and the second device region in each of the first fin and the second fin, and an isolation layer disposed below the first fin and the second fin. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin and the second fin and to isolate the first device region and the second device region in each of the first fin and the second fin.

[0005] The semiconductor structure includes a first device region and a second device region adjacent to the first device region. Each of the first device region and the second device region includes a semiconductor substrate, a source feature and a drain feature above the semiconductor substrate, an active region between the source feature and the drain feature, and a gate structure above the active region. The semiconductor structure further includes an isolation structure disposed between the semiconductor substrate in the first device region and the semiconductor substrate in the second device region. Each of the semiconductor substrate in the first device region and the semiconductor substrate in the second device region terminates at a backside, and wherein the isolation structure extends to the backside.

[0006] To make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are specifically described, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] When read with the attached Figure One The figures can best be understood from the following detailed description in conjunction with the accompanying drawings. It is to be understood that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the clarity of discussion.

[0008] Figure 1 is a schematic bottom view of a semiconductor structure according to some embodiments.

[0009] Figure 2 is a schematic X-cut cross-sectional view of the semiconductor structure of Figure 1

[0010] Figure 3 ​is a schematic X-cut cross-sectional view of a semiconductor structure according to other embodiments Figure 1 is a schematic X-cut cross-sectional view of a semiconductor structure according to other embodiments

[0011] Figure 4 is a schematic X-cut cross-sectional view of a semiconductor structure according to other embodiments Figure 1 is a schematic X-cut cross-sectional view of a semiconductor structure according to other embodiments

[0012] Figure 5 is a schematic X-cut cross-sectional view of a semiconductor structure according to some embodiments Figure 1 is a schematic X-cut cross-sectional view of a semiconductor structure according to some embodiments

[0013] Figures 6 to 21 is a schematic view of a method for manufacturing a semiconductor structure according to some embodiments, wherein Figures 6 to 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 are perspective views, and Figure 17 , Figure 17 , Figure 19 and Figure 21 are Y-cut cross-sectional views of the aforementioned perspective views.

[0014] Figures 22 to 24 is a schematic X-cut cross-sectional view of a semiconductor structure during successive manufacturing stages according to some embodiments.

[0015] Figures 25 to 26 is a schematic X-cut cross-sectional view of a semiconductor structure during successive manufacturing stages according to some embodiments.

[0016] Figures 27 to 28 is a schematic Y-cut cross-sectional view of a semiconductor structure during successive manufacturing stages according to some embodiments.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] 1-1, 2-2, 5-5, 28-28: line

[0019] 100: semiconductor structure

[0020] 200: fin

[0021] 201: first fin

[0022] 202: second fin

[0023] 210: device region

[0024] 211: first device region

[0025] 212: second device region

[0026] 219: backside

[0027] 300: shallow trench isolation region

[0028] 350, 1010: interlayer dielectric region

[0029] 400: backside via

[0030] 401, 402: active backside via

[0031] 410: conductive core

[0032] 420: dielectric

[0033] 421: first end

[0034] 422: second end

[0035] 440: silicide

[0036] 500: continuation polysilicon across diffusion layer boundary isolation structure

[0037] 501: isolation structure

[0038] 610: source / drain feature

[0039] 610N: N-type epitaxial material

[0040] 610P: P-type epitaxial material

[0041] 611: source feature

[0042] 612: drain feature

[0043] 615: high doped material

[0044] 616: low doped material

[0045] 617: base structure

[0046] 618: terminating source / drain feature

[0047] 619: dummy source / drain feature

[0048] 620, 625: active region

[0049] 629: terminating active region

[0050] 630: gate structure

[0051] 635: gate

[0052] 640: interlayer dielectric material

[0053] 700: front side interconnect line structure

[0054] 710: conductive contact

[0055] 720: Conductive interconnects

[0056] 800: Inner isolation layer

[0057] 899: Shared bottom surface

[0058] 900: outer isolation layer

[0059] 901: Semiconductor substrate

[0060] 902: Epitaxial Stack

[0061] 903, 904: epitaxial layer

[0062] 905: Platform part

[0063] 910: Sacrificial (dummy) gate structure

[0064] 911: Mask layer

[0065] 912: Spacer

[0066] 920: Isolation layer

[0067] 930: Etch stop layer

[0068] 932: Arrow

[0069] 940: Dielectric Materials

[0070] 950: Backside interconnect structure

[0071] 960: Double-layer hard mask

[0072] 970: Groove

[0073] 1020: Mask DETAILED DESCRIPTION

[0074] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0075] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0076] When a spatially relative term, such as those listed above, is used in the description, it can be used to describe a positional relationship between one element or feature and another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0077] In certain embodiments herein, a "layer of material" is a layer that includes at least 50 mass percent concentration (wt.%) of an identified material, such as at least 60 wt.% of an identified material, or at least 75 wt.% of an identified material, or at least 90 wt.% of an identified material; and a layer that is a "material" includes at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, or at least 90 wt.% of an identified material. For example, certain embodiments, each of a layer of titanium nitride and a layer of titanium nitride is a layer that is at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, or at least 90 wt.% titanium nitride.

[0078] For the sake of brevity, the conventional techniques related to semiconductor device manufacturing can not be described in detail herein. In addition, the various tasks and processes described herein can be incorporated in more complete procedures or processes having additional functionality not specifically described herein. In particular, various

[0079] Embodiments herein provide for forming semiconductor devices, such as gate-all-around (GAA) field effect transistors (FETs), on a front side of a device. Further, embodiments herein provide for forming backside interconnect line structures, which can sometimes be referred to as super power rails (SPRs) or backside power rails (BPRs), for powering the semiconductor devices. Further, embodiments herein provide for isolation for the semiconductor devices and / or super power rails. As a result, junction leakage currents that can lead to data storage or interference are reduced or eliminated. In particular, high voltage coupling from source / drain features to the substrate and stress on unselected devices are reduced or eliminated. Further, well isolation designs can be eliminated through the methods described herein.

[0080] In certain embodiments, mesa portions of the semiconductor substrate under adjacent device regions are physically and electrically isolated from one another through isolation structures in the form of backside vias surrounded by isolation material. In certain embodiments, mesa portions of the semiconductor substrate under adjacent device regions are physically and electrically isolated from one another through isolation structures in the form of Continuous Poly On Diffusion Edge (CPODE) structures. In certain embodiments, adjacent fins are isolated from one another through thinning of the semiconductor substrate or wafer to remove semiconductor material under shallow isolation that is interconnected with the fins. As a result, in each of the embodiments, time-dependent dielectric breakdown (TDDB) can be improved, junction leakage current can be reduced, and stress can be reduced. Further, through thinning of the backside semiconductor material, well leakage noise is reduced and the need for a deep N-doped well can be eliminated.

[0081] Reference is made to Figure 1 , which provides a schematic bottom view (or Z-cut view) of a semiconductor structure 100, in accordance with some embodiments. Figure 2 To Figure 1 provide a schematic X-cut view of the semiconductor structure. In particular, Figure 2 the cross-sectional view of Figure 1 is taken along line 2-2 in Figure 1 . Likewise, Figure 2It is intercepted by line 1-1.

[0082] like Figure 1 As shown, the semiconductor structure 100 includes a plurality of fins 200, which include a first fin 201 and a second fin 202 that are parallel and extend along the X direction. As shown in the figure, the plurality of fins 201 and 202 are spaced apart from each other in the Y direction.

[0083] Each fin 200 includes a plurality of device regions 210 or a plurality of semiconductor substrate portions. For example, each fin 200 includes a first device region 211 and a second device region 212. The plurality of device regions 211 and 212 are laterally adjacent to each other in, for example, the X direction.

[0084] like Figure 1 As shown, the semiconductor structure 100 includes a plurality of isolation regions 300 extending in parallel along the X direction, such as a plurality of shallow trench isolation (STI) regions 300. As shown, the plurality of isolation regions 300 are spaced apart from each other along the Y direction. Each isolation region 300 is located between a pair of adjacent fins 200.

[0085] Furthermore, a plurality of interlayer dielectric (ILD) regions 350 may be disposed within the multi-isolation region 300 and may extend vertically (along the Z direction).

[0086] like Figure 1 As shown, the semiconductor structure 100 includes a plurality of backside vias 400, which are disposed within the plurality of fins 200 and extend vertically (along the Z direction). The plurality of backside vias 400 include a conductive core 410. For example, the conductive core 410 can be formed of tungsten or another suitable conductive metal material. In addition, the plurality of backside vias 400 include a dielectric layer 420 surrounding the conductive core 410. Figure 1 The dielectric layer 420 is annular or ring-shaped. In some embodiments, the dielectric layer 420 is silicon nitride or another dielectric material suitable for insulation.

[0087] As shown, each dielectric layer 420 extends longitudinally (along the Y direction) completely across the plurality of fins 200 from a first end 421 to a second end 422, such that the first end 421 contacts the isolation region 300 and the second end 422 contacts the isolation region 300. Thus, each dielectric layer 420 serves as an isolation structure 500 that physically separates and electrically isolates adjacent plurality of device regions 210 within each fin 200.

[0088] Specifically, in Figure 1In some embodiments, a selected isolation structure 501 is located between the first device region 211 and the second device region 212 in the first fin 201. The isolation structure 501 includes a dielectric layer 420 that physically separates the first device region 211 from the second device region 212 in the first fin 201. In addition, the isolation structure 501 includes a dielectric layer 420 that electrically isolates the first device region 211 from the second device region 212 in the first fin 201.

[0089] Referring now to Figure 2 , more features of the semiconductor structure 100 are illustrated. As shown, in each device region 211 and 212, the semiconductor structure 100 includes a plurality of source / drain features 610, such as source features 611 and drain features 612 above the respective fins 201. As used herein, the “source / drain feature(s)” can refer to a source feature or a drain feature, individually or collectively, depending on the context.

[0090] As further shown, in each device region 211 and 212, the semiconductor structure 100 includes an active region 620 located between the plurality of source / drain features 610. In the illustrated embodiment, the active region 620 is formed of a plurality of nanosheets in an embodiment of a GAA FET.

[0091] In addition, in each device region 211 and 212, the semiconductor structure 100 includes a gate structure 630 above the active region 620. For example, the gate structure 630 can include a high-k dielectric and a metal gate. An interlayer dielectric material 640 can be formed above the plurality of gate structures.

[0092] In Figure 2 , the semiconductor structure 100 includes a front-side interconnect line structure 700 disposed above the plurality of source / drain features 610 and the plurality of gate structures 630 of each device region 211 and 212. For example, the front-side interconnect line structure 700 can include a plurality of conductive contacts 710 connected to selected ones of the plurality of source / drain features 610.

[0093] In some embodiments, each source / drain feature 610 can be formed of a highly doped material 615 (i.e., an epitaxial material with a high dopant concentration) and a lowly doped material 616 (i.e., an epitaxial material with a lower dopant concentration). As shown, each source / drain feature 610 can include a bottom structure 617. In some embodiments, the bottom structure 617 is an undoped material, such as undoped silicon. In other embodiments, the bottom structure 617 is a flexible bottom insulator (FBI) instead of undoped silicon. In some embodiments, the bottom structure 617 can include an undoped material (e.g., undoped silicon) and a flexible bottom insulator.

[0094] like Figure 2 As shown, the semiconductor material of the plurality of terrace portions of the plurality of fins 200 or the plurality of device regions 210 extends vertically downward in the Z direction and terminates at a backside 219. In some embodiments, the backside 219 is planar. Furthermore, the semiconductor structure 100 includes an inner isolation layer 800 disposed below the backside 219. In some embodiments, the inner isolation layer 800 is disposed directly on the backside 219. The inner isolation layer 800 may be silicon nitride or other dielectric materials suitable for insulation.

[0095] like Figure 2 As shown, the plurality of backside vias 400 extend from contact with the selected plurality of source / drain features 610, through the semiconductor material of the plurality of mesa portions of the plurality of fins 200 or the plurality of device regions 210, and through the backside 219 of the semiconductor material of the plurality of fins 200. In some embodiments, the plurality of backside vias 400 extend through the inner isolation layer 800 to a shared bottom surface 899 defined by the inner isolation layer 800 and the plurality of backside vias 400. In some embodiments, the shared bottom surface 899 is planar.

[0096] Therefore, the dielectric layer 420 defining the plurality of backside vias 400 of the isolation structure 500 directly contacts the inner isolation layer 800. As a result, the conductive core 410 of the backside vias 400 is completely physically and electrically isolated from the semiconductor material of the plurality of platform portions of the plurality of fins 200 or the plurality of device regions 210.

[0097] like Figure 2As further shown, semiconductor structure 100 includes an outer isolation layer 900 positioned below a selected isolation structure 501. Specifically, outer isolation layer 900 is disposed directly on shared bottom surface 899 at the selected isolation structure 501, and inner isolation layer 800 is adjacent to the selected isolation structure 501. As a result, dielectric layer 420 defining a plurality of backside vias 400 of isolation structure 500 directly contacts outer isolation layer 900. Thus, conductive core 410 forming backside via 400 of selected isolation structure 501 is electrically disconnected from any conductive path.

[0098] exist Figure 2 In FIG, the semiconductor structure 100 includes a backside interconnect structure 950 disposed below the fin 200 and laterally adjacent to the outer isolation layer 900 in the X direction. In some embodiments, the backside interconnect structure 950 is formed of a metal layer, such as a copper or aluminum layer, or another suitable conductive material. Figure 2 In the embodiment, the backside interconnect structure 950 is disposed below the inner isolation layer 800 .

[0099] like Figure 2 As shown, a plurality of active backside vias 401 and 402 are in contact with and electrically connected to the backside interconnect structure 950. Figure 2 In the embodiment of FIG. 4 , the plurality of active backside vias 401 and 402 contact the source features 611 in each of the device regions 211 and 212 .

[0100] Cross Reference Figure 1 and Figure 2 The semiconductor structure 100 includes a first device region 211 and a second device region 212 adjacent to the first device region 211, wherein each device region includes a semiconductor substrate or fin 201, a source feature 611 and a drain feature 612 above the semiconductor substrate; an active region 620 between the source feature 611 and the drain feature 612; and a gate structure 630 above the active region 620; an isolation structure 501 disposed between the semiconductor substrate in the first device region 211 and the semiconductor substrate in the second device region 212; wherein each semiconductor substrate terminates at a back side 219, and wherein the isolation structure 501 extends to the back side 219.

[0101] As depicted, isolation structure 501 is a dummy backside via 400 that includes a conductive core 410 surrounded by a dielectric layer 420. As a dummy backside via 400, conductive core 410 extends downward to a dead end that is not electrically connected to any conductive feature.

[0102] The semiconductor structure 100 further includes an isolation layer, such as an outer isolation layer 900, disposed under the backside 219 of each semiconductor substrate, and the isolation structure 501 contacts the isolation layer 900.

[0103] The semiconductor structure 100 further includes an active backside via 401 contacting a source feature 611 in the first device region 211 and an active backside via 402 contacting a source feature 611 in the second device region 212. Meanwhile, the semiconductor structure 100 includes a backside interconnect line structure 950 disposed under the backside 219 of the semiconductor substrate in the first device region 211 and adjacent to the isolation layer 900, where the active backside via 401 contacts the backside interconnect line structure 950.

[0104] As further shown, among the plurality of active regions 620, each device region 211 and 212 includes a terminal active region 629 adjacent to the other device region 212 or 211. The semiconductor structure 100 further includes, among the plurality of source / drain features 610, a dummy source / drain feature 619 disposed between the plurality of terminal active regions 629. As shown, the isolation structure 501 contacts the dummy source / drain feature 619.

[0105] In Figures 1 to 2 , the semiconductor structure 100 includes a frontside interconnect line structure 700 disposed over the source feature 611, the drain feature 612, and the gate structure 630 of each device region 211 and 212.

[0106] Through Figure 2 the design of the semiconductor structure, the backside via isolation structure 500 separates the plurality of active regions such that no stress is imparted to the plurality of unselected devices. For example, high voltage coupling from the plurality of source / drain features to the substrate is reduced or eliminated to avoid stressing the unselected devices.

[0107] Reference is now made to Figure 3 , which provides alternative embodiments of the semiconductor structure 100. Figure 3 is a similar figure to Figure 2 , namely Figure 1 a schematic X-section view of a semiconductor structure, such as taken along line 2-2 in Figure 1 .

[0108] Unlike the embodiments of Figure 2 , in Figure 3In the embodiment shown in FIG. 1 , semiconductor structure 100 is formed without backside vias 400 electrically connected to the backside interconnect structure. Instead, outer isolation layer 900 continuously contacts shared bottom surface 899 defined by inner isolation layer 800 and the plurality of backside vias 400 spanning across the plurality of device regions 211 and 212. Thus, dielectric layer 420 of each backside via 400 forms isolation structure 500. Consequently, each source / drain feature 610 is formed as a dummy source / drain feature 619.

[0109] Figure 4 Another embodiment of the semiconductor structure 100 is shown. Figure 4 In FIG, the isolation structure 500 is formed by a continuous poly on diffusion edge (CPODE) process. Therefore, the isolation structure 500 is a continuous poly on diffusion edge structure. Figure 2 An embodiment of Figure 4 The isolation structure 500 in FIG. 5 physically separates and electrically isolates the first terrace portion or device region 211 of the fin from the second terrace portion or device region 212 of the fin.

[0110] like Figure 4 As shown, the semiconductor structure 100 includes a semiconductor substrate or fin 200 having a first device region 211 and a second device region 212, a plurality of source / drain features 610 including a plurality of source features 611 and a plurality of drain features 612, a plurality of active regions 620, a plurality of gate structures 630, and a front-side interconnect structure 700 as described above.

[0111] and Figure 2 and Figure 3 Unlike the embodiments described above, the semiconductor structure 100 may not include the inner isolation layer 800 and / or the outer isolation layer 900. Because the continuous polysilicon cross-diffusion layer boundary isolation structure 500 does not include the conductive core 410, the continuous polysilicon cross-diffusion layer boundary isolation structure 500 does not need to be grounded or terminated to the isolation material.

[0112] like Figure 4 As shown, the fin 200 or semiconductor substrate terminates at the back side 219, and the continuous polysilicon cross-diffusion layer boundary isolation structure 500 extends to the back side 219 and terminates at the back side 219. Figure 4 In FIG. 2 , the plurality of active backside vias 400 physically contact the backside interconnect structure 950 at the backside 219 .

[0113] exist Figure 4In the embodiment of FIG. 5 , each device region 211 and 212 includes a termination source / drain feature 618 among the plurality of source / drain features 610. As shown, the continuous polysilicon cross-diffusion layer boundary isolation structure 500 is disposed directly adjacent to and between the termination source / drain features 618.

[0114] Figure 5 Provide example along the Figure 1 The Y-section view of line 5-5 in FIG. Figures 2 to 4 There are more than 100 features of the semiconductor structure not shown in the X-cut view.

[0115] exist Figure 5 In the embodiment of the present invention, fins 201 and fins 202 are spaced apart from each other in the Y direction. As shown, an interlayer dielectric region 350 is disposed between the plurality of fins 201 and 202 and extends vertically (along the Z direction). In addition, portions of the shallow trench isolation region 300 are longitudinally adjacent to each of the fins 201 and 202 (in the Y direction). For example, a plurality of shallow trench isolation regions 300 are located between the interlayer dielectric region 350 and the plurality of fins 201 and 202.

[0116] The plurality of fins 201 and 202, the plurality of interlayer dielectric regions 350, and the plurality of shallow trench isolation regions 300 all extend downward (along the Z-direction) and terminate at the backside 219. In some embodiments, the backside 219 is planar. As shown, the inner isolation layer 800 is located underneath and directly on the backside 219. In the embodiment shown, the inner isolation layer 800 forms a continuous, uninterrupted interface with the backside 219.

[0117] As shown, a plurality of source / drain features 610 are located above the plurality of fins 201 and 202. In some embodiments, the plurality of source / drain features 610 above adjacent pluralities of fins 201 and 202 are doped differently. For example, the source / drain features 610 above the fin 201 may be P-type epitaxial material 610P, and the source / drain features 610 above the fin 202 may be N-type epitaxial material 610N.

[0118] As further shown, the front-side interconnect structure 700 is formed over the plurality of source / drain features 610 and includes a plurality of conductive contacts 710 connected to the plurality of source / drain features 610. Furthermore, an additional interlayer dielectric region 1010 may be located over the plurality of conductive contacts 710, and the front-side interconnect structure 700 may include a plurality of conductive contacts 720 extending through the interlayer dielectric region 1010 to interconnect the plurality of conductive contacts 710, as shown.

[0119] therefore, Figure 1 and Figure 5The semiconductor structure 100 is shown to include a first fin 201 extending along the X-direction and a second fin 202 parallel to the first fin 201 and spaced apart from the first fin 201 in the Y-direction perpendicular to the X-direction. Furthermore, the semiconductor structure 100 includes an isolation region 300 disposed between the first fin 201 and the second fin 202. Furthermore, the semiconductor structure 100 includes an isolation layer 800 disposed below the first fin 201 and the second fin 202, wherein the isolation region 300 contacts the isolation layer 800, and the isolation region 300 contacts the isolation structure 500, thereby isolating the first fin 201 from the second fin 202.

[0120] Figures 6 to 21 Draw a picture for manufacturing Figures 1 to 5 The method of the semiconductor structure 100 of one or more embodiments is shown in FIG.

[0121] exist Figure 6 In the method, a substrate 901 is provided. In some embodiments, the substrate 901 includes a single crystalline semiconductor layer on at least a portion of its surface. The substrate 901 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 901 is made of Si crystal.

[0122] like Figure 6 As shown, this method forms one or more epitaxial layers above a substrate 901. In some embodiments, an epitaxial stack 902 is formed above the substrate 901. The epitaxial stack 902 includes a plurality of epitaxial layers 903 of a first composition intercalated by a plurality of epitaxial layers 904 of a second composition. The first and second compositions may be different. Various embodiments may include providing various embodiments having different oxidation rates and / or etching selected first and second compositions. In one embodiment, the plurality of epitaxial layers 903 are SiGe and the plurality of epitaxial layers 904 are Si. In embodiments where the epitaxial layers 903 include SiGe and the epitaxial layers 904 include Si, the Si oxidation rate is less than the SiGe oxidation rate. Note that Figure 6 Three epitaxial layers 903 and three epitaxial layers 904 are depicted for illustrative purposes only and are not intended to limit the scope of the present invention beyond that specifically recited in the claims. It will be appreciated that any number of epitaxial layers may be formed in epitaxial stack 902; the number of layers depends on the desired number of channel regions for the GAA device in semiconductor structure 100. In some embodiments, the number of epitaxial layers 904 is between two and ten.

[0123] like Figure 6 As shown, the method patterns the epitaxial stack 902 to form a plurality of semiconductor fins 200. Figure 6The formation of two fins 200 is shown, but any suitable number of fins may be formed. A plurality of trenches are etched between adjacent fins 200 .

[0124] In various embodiments, each fin 200 includes an upper portion of a plurality of interleaved epitaxial layers 903 and 904 and a bottom or platform portion 905 formed by an etched substrate 901. Each fin 200 protrudes upward from the substrate 901 in the Z direction and extends longitudinally in the X direction. The plurality of fins 200 are spaced apart in the Y direction. The plurality of sidewalls of each fin 200 can be straight or sloped. Figure 6 During the manufacturing stage, the plurality of fins 200 remain as interconnected semiconductor material lines extending through the unetched substrate 901 .

[0125] like Figure 6 As shown, this method forms a plurality of shallow trench isolation features (also referred to as STI features) 300 in trenches adjacent to each fin 200 using a dielectric layer. The plurality of shallow trench isolation regions 300 can be formed by first filling the plurality of trenches surrounding each fin 200 with a dielectric material layer to cover the plurality of top surfaces and the plurality of sidewalls (not shown) of the fin 200. The dielectric material layer can include one or more dielectric materials. Suitable dielectric materials for the dielectric layer can include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or spin-on coating techniques. The dielectric material layer is then planarized using, for example, chemical mechanical planarization (CMP). The dielectric material layer can then be recessed to form the plurality of shallow trench isolation regions 300. In the illustrated embodiment, a plurality of shallow trench isolation regions 300 are formed on a substrate 901. The plurality of isolation regions 300 may be recessed using any suitable etching technique, including dry etching, wet etching, reactive ion etching (RIE), and / or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the plurality of isolation regions 300 without etching the plurality of fins 200.

[0126] like Figure 7As shown, this method can form a plurality of sacrificial gate structures 910. The plurality of sacrificial gate structures 910 are formed over portions of the plurality of fins 200 that will become the plurality of channel regions. The plurality of sacrificial gate structures 910 can extend over adjacent fins 200. The plurality of sacrificial gate structures 910 are directly over and define the channel regions of the plurality of GAA devices to be formed. Each sacrificial gate structure 910 includes a sacrificial gate dielectric and a sacrificial gate over the sacrificial gate dielectric. As shown, the plurality of gate structures 910 extend longitudinally along the Y direction and are spaced apart in the X direction.

[0127] The plurality of sacrificial gate structures 910 can be formed by first blanket depositing a sacrificial gate dielectric over the plurality of fins 200. A sacrificial gate layer is then blanket deposited over the sacrificial gate dielectric and over the plurality of fins 200. The sacrificial gate dielectric can include silicon oxide, silicon nitride, or a combination thereof. The sacrificial gate layer can include silicon, such as polysilicon or amorphous silicon. In some embodiments, a planarization operation is performed on the sacrificial gate layer. The sacrificial gate dielectric and the sacrificial gate layer are deposited using chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. A mask layer 911 is formed over the sacrificial gate layer. The mask layer 911 can include a mask sublayer, such as silicon oxide, and a mask sublayer, such as silicon nitride. Subsequently, the mask layer 911 is patterned to pattern the plurality of sacrificial gate layers and the sacrificial gate dielectric into the plurality of sacrificial gate structures 910.

[0128] The fins 200 are partially exposed between and on opposite sides of the plurality of sacrificial gate structures 910, thereby defining a plurality of source / drain regions. In this disclosure, source and drain can be used interchangeably, and their structures are substantially identical.

[0129] Referring still to Figure 7 The method forms a plurality of spacers 912 on the sidewalls of the plurality of sacrificial gate structures 910 and the sidewalls of the plurality of fins 200 by depositing a plurality of spacer materials and subsequently etching. The plurality of spacers 912 can include a plurality of spacer materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer 912 includes multiple layers, such as a liner layer and a main spacer wall layer on the sidewalls of the liner layer.

[0130] For example, multiple spacers 912 can be formed by depositing spacer materials including a liner material layer and a dielectric material layer over the sacrificial gate structure 910 using multiple processes such as a subatmospheric CVD process, a flow CVD process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes.

[0131] like Figure 7 As shown, after depositing the liner material layer and the dielectric material layer, etching-back (e.g., anisotropically) is performed to expose and remove portions of the plurality of fins 200 adjacent to and not covered by the sacrificial gate structure 910. The liner material layer and the dielectric material layer may remain on the sidewalls of the sacrificial gate structure 910 as a plurality of gate sidewall spacers 912, and on the sidewalls of the plurality of fins as a plurality of fin sidewall spacers 912. In some embodiments, the etching-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof.

[0132] The method may continue by forming an isolation layer 920 over the semiconductor substrate 901. Specifically, the isolation layer 920 is formed on the bottom surfaces of the gaps created by etching back the source / drain regions of the fins 200. In an exemplary embodiment, the isolation layer 920 is formed using an atomic layer deposition process. In an exemplary embodiment, the isolation layer 920 is a dielectric material having a wide bandgap. In some embodiments, the isolation layer 920 is formed of silicon oxide, silicon nitride, or a combination thereof.

[0133] like Figure 7 As shown, the method can continue by forming a plurality of source / drain features 610 in the plurality of source / drain regions. In an exemplary embodiment, the plurality of source / drain features 610 are formed by epitaxial growth. For n-channel FETs, the epitaxial material can include one or more layers of Si, SiP, SiC, and SiCP, or for p-channel FETs, the epitaxial material can include Si, SiGe, or Ge. For p-channel FETs, the source / drain can also include boron. The plurality of source / drain epitaxial layers can be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy (MBE).

[0134] refer to Figure 8 The method may continue by forming an interlayer dielectric region 350 over the plurality of source / drain features 610 .

[0135] In addition, the method may include opening a plurality of sacrificial gate structures 910. Specifically, a chemical mechanical planarization (CMP) process may be performed to expose the sacrificial gates. The method may then remove the sacrificial gates to form a plurality of gate cavities defined by a plurality of sidewall spacers 912. The method may then remove the plurality of epitaxial layers 903 to define the plurality of epitaxial layers 904 as a plurality of semiconductor nanosheets spaced vertically apart. The method may then perform a replacement metal gate process to form the plurality of gate structures. After completing the replacement metal gate process, the method may continue to form a cut metal gate isolation structure to isolate adjacent plurality of devices.

[0136] like Figure 8 As shown, the method can then form a plurality of conductive contacts 710 and an interlayer dielectric region 1010 over the semiconductor structure 100. Further processes can include patterning a mask 1020 over the interlayer dielectric region 1010, etching the interlayer dielectric region 1010, and forming a plurality of conductive interconnect lines 720, which extend through the interlayer dielectric region 1010 to interconnect with the plurality of conductive contacts 710.

[0137] like Figure 9 As shown, a back-end-of-line (BEOL) process is then performed to complete the front-side interconnect structure 700 .

[0138] exist Figure 10 In the process, the semiconductor structure 100 is turned over and a backside process is performed. Figure 11 yes Figure 10 FIG. 1 is a cross-sectional view of a semiconductor structure 100 .

[0139] like Figure 10 and Figure 11 As shown, the unetched portion of the semiconductor substrate 901 retains a plurality of mesa portions 905 connecting the plurality of fins 200. In some embodiments, the semiconductor substrate 901 may include an etch stop layer 930 as shown. The etch stop layer extends laterally between the plurality of shallow trench isolation regions 300.

[0140] exist Figure 10 and Figure 11 In the embodiment, a dry thin down process is performed to remove a back side portion of the semiconductor substrate 901 , for example, along the direction of arrow 932 .

[0141] exist Figure 12 In this method, the Figures 10 to 12The remaining portion of the semiconductor substrate 901 located above the etch stop layer 930 is wet removed in a flip direction. Figure 13 yes Figure 12 FIG. 1 is a cross-sectional view of a semiconductor structure 100 .

[0142] As a result of the wet removal of the semiconductor substrate 901 , the etch stop layer 930 and the plurality of shallow trench isolation regions 300 are uncovered.

[0143] exist Figure 14 In the process, the method continues by wet removing the etch stop layer 930 . Figure 15 yes Figure 14 FIG. 1 is a cross-sectional view of a semiconductor structure 100 .

[0144] As Figures 12 to 15 As a result of the removal process, the plurality of terrace portions 905 of the plurality of fins 200 are physically disconnected, ie, no semiconductor material remains interconnecting the plurality of fins 200 .

[0145] exist Figure 16 In the dielectric material 940 is deposited on Figures 14 to 15 The partially fabricated semiconductor structure 100 is shown above. Figure 17 yes Figure 16 As shown, dielectric material 940 contacts the plurality of mesa portions 905 of the plurality of fins 200 and the plurality of shallow trench isolation regions 300. Exemplary dielectric material 940 is silicon oxide.

[0146] exist Figure 18 In the embodiment, a chemical mechanical planarization process is performed to remove the oxide dielectric material 940 and planarize the mesa portions 905 of the fins 200 and the shallow trench isolation regions 300 to the same backside 219. Therefore, the backside 219 is planar. Figure 19 yes Figure 18 sectional view of .

[0147] exist Figure 20 In the embodiment of the present invention, the method includes depositing a hard mask or inner isolation layer 800. An exemplary inner isolation layer 800 is silicon nitride. Figure 21 yes Figure 20 sectional view of .

[0148] Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 and Figure 21 The cross-sectional view is a Y-cut cross-sectional view across two adjacent fins.

[0149] Figures 22 to 24 is an X-section view along a single fin, illustrating the method at various stages of fabrication. Figures 22 to 24, a plurality of epitaxial source / drain features 610 are depicted as optionally including a plurality of bottom structures 617 in the form of a flexible bottom insulator. Specifically, some of the source / drain features 610 include the plurality of bottom structures 617 in the form of a flexible bottom insulator, and some of the source / drain features 610 do not include the plurality of bottom structures 617. It is also contemplated that all of the source / drain features 610 may include the plurality of bottom structures 617 in the form of a flexible bottom insulator, or that no source / drain features 610 include the plurality of bottom structures 617.

[0150] exist Figure 22 In the embodiment, a hard mask, for example, a bi-layer hard mask 960 is formed over the inner isolation layer 800 .

[0151] exist Figure 23 In the embodiment, a photolithography and etching process is performed to etch a plurality of trenches 970 that fall on selected source / drain features 610. In some embodiments, the plurality of trenches 970 fall on the highly doped material 615 in the plurality of source / drain features 610.

[0152] exist Figure 24 In the embodiment of the present invention, a plurality of backside vias 400 are formed in a plurality of trenches 970. For example, a dielectric layer 420 can be formed along the trench sidewalls. In addition, a silicide 440 can be formed on the source / drain features 610 in the plurality of trenches 970, and a plug material can be deposited in the trenches 970 to form a conductive core 410, followed by a planarization process to form a shared surface 899 defined by the isolation layer 800 and the plurality of backside vias 400.

[0153] As shown, a plurality of backside vias 400 are formed in contact with the highly doped material 615, which reduces resistance due to the higher dopant concentration.

[0154] exist Figures 22 to 24 In an embodiment, the plurality of bottom structures 617 may not be utilized, and the via etch depth into the source / drain features 610 may be increased to expand the Z-direction spacing of the backside via to the metal gate.

[0155] Now refer to Figures 25 to 26 , an embodiment of a method for forming a semiconductor structure 100 having a continuous polysilicon cross-diffusion layer boundary isolation structure 500 is described.

[0156] like Figure 25As shown, after forming a plurality of source / drain features 610, a plurality of active regions 620, and a plurality of gates 630, a continuous polysilicon cross-diffusion layer boundary process is performed to remove selected gates 635 and selected active regions 625 below the gates to create a barrier between the plurality of devices. For example, the continuous polysilicon cross-diffusion layer boundary process may include patterning a mask having openings above desired locations of the continuous polysilicon cross-diffusion layer boundary structure 500 (such as above the gates to be removed). One or a series of etching processes are then performed and may land in the substrate 901. According to some embodiments, wet etching, dry etching, a combination thereof, etc. may be used.

[0157] As shown, the etching process removes the selected gate 635 and the underlying active region 625 and forms a deep trench 980 in the semiconductor substrate 901 .

[0158] After further front-side processing as described above, the semiconductor structure 100 is then flipped over, as shown in FIG. Figure 26 As shown, the back side 219 of the semiconductor substrate is thinned. Then, a mask is patterned over the back side 219 of the semiconductor structure 100 as described above, and a plurality of trenches are etched to form a plurality of back side vias 400. Thereafter, the mask can be removed and a back side interconnect structure 950 can be formed directly on the back side 219 of the plurality of back side vias 400, the continuous polysilicon cross-diffusion layer boundary isolation structure 500, and the plurality of remaining portions of the plurality of fins 200. In this manner, the back side 219 of the plurality of fins 200 is manufactured. Figure 4 semiconductor structure.

[0159] Now please refer to Figures 27 to 28 , further describing an embodiment of a method for forming a semiconductor structure 100 with inter-fin isolation.

[0160] like Figure 27 As shown, a plurality of fins 200 are etched from a substrate 901 and a plurality of shallow trench isolation regions 300 are formed between the plurality of fins. In addition, a plurality of interlayer dielectric regions 350 may be formed above the plurality of shallow trench isolation regions 300 and between the plurality of source / drain features 610.

[0161] After the front side process, such as Figure 28 Flip shown Figure 27 Then, the backside thinning and / or removal process removes portions of the semiconductor substrate 901, the mesa portions 905, and the shallow trench isolation regions 300 above the line 28-28 to create a semiconductor structure having a planar backside 219. Then, an inner isolation layer 800 is formed over the backside 219 of the semiconductor structure 100, as shown in FIG. Figure 5 shown.

[0162] As described herein, in some embodiments, substrate isolation is provided by the plurality of backside via structures. Further, in some embodiments, the poly-silicon across diffusion layer boundary structure provides substrate isolation due to substrate thinning, i.e., the thinning process removes portions of the poly-silicon across diffusion layer boundary structure. In some embodiments, due to substrate thinning, the plurality of device regions are isolated from one another.

[0163] In an embodiment, a semiconductor structure includes a first fin extending along an X direction and a second fin parallel to the first fin and spaced apart from the first fin along a Y direction perpendicular to the X direction. Each of the first fin and the second fin is formed with a first device region and a second device region arranged along the X direction. The semiconductor structure includes an isolation region disposed between the first fin and the second fin, an isolation structure disposed between the first device region and the second device region in each of the first fin and the second fin, and an isolation layer disposed under the first fin and the second fin. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin and the second fin and to isolate the first device region and the second device region in each of the first fin and the second fin.

[0164] In certain embodiments of the semiconductor structure, each of the first device region and the second device region includes a source feature and a drain feature over the respective fin, an active region between the source feature and the drain feature, and a gate structure over the active region.

[0165] In certain embodiments, the semiconductor structure further includes an active backside via in each of the first device region and the second device region in contact with the source feature, and a backside interconnect structure disposed under each of the first fin and the second fin adjacent to the isolation layer. The active backside via contacts the backside interconnect structure.

[0166] In certain embodiments, the semiconductor structure further includes a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure in each of the first device region and the second device region.

[0167] In other embodiments, a semiconductor structure includes a first device region and a second device region adjacent to the first device region. Each of the first device region and the second device region includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, an active region between the source feature and the drain feature, and a gate structure over the active region. The semiconductor structure further includes an isolation structure disposed between the semiconductor substrate in the first device region and the semiconductor substrate in the second device region. Each of the semiconductor substrate in the first device region and the semiconductor substrate in the second device region terminates at a backside, and wherein the isolation structure extends to the backside.

[0168] In certain embodiments of the semiconductor structure, the isolation structure is a dummy backside via including a conductive core surrounded by a dielectric.

[0169] In certain embodiments, the semiconductor structure further includes an isolation layer disposed under the backside of each of the semiconductor substrate in the first device region and the semiconductor substrate in the second device region, wherein the isolation structure contacts the isolation layer.

[0170] In certain embodiments, the semiconductor structure further includes an active backside via in the first device region in contact with the source feature, a backside interconnect structure disposed under the backside of the semiconductor substrate in the first device region and adjacent to the isolation layer, wherein the active backside via contacts the backside interconnect structure.

[0171] In certain embodiments of the semiconductor structure, each of the first device region and the second device region includes a terminating active region, the semiconductor substrate further includes a dummy feature disposed between a plurality of the terminating active regions, and the isolation structure contacts the dummy feature.

[0172] In certain embodiments, the semiconductor structure further includes a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure of each of the first device region and the second device region.

[0173] In certain embodiments of the semiconductor structure, the isolation structure is formed by a continuous poly on diffusion edge (CPODE) process.

[0174] In certain embodiments of the semiconductor structure, each of the first device region and the second device region includes a termination source / drain region; and the isolation structure is disposed between a plurality of the termination source / drain regions.

[0175] In another embodiment, a method includes etching a front side of a semiconductor substrate to form a first fin and a second fin parallel to the first fin, wherein an unetched portion of the semiconductor substrate adjacent to a back side of the semiconductor substrate is connected to the first fin and the second fin; forming an isolation region over the unetched portion of the semiconductor substrate between the first fin and the second fin; forming a first semiconductor device over the first fin and a second semiconductor device over the second fin; and removing the unetched portion of the semiconductor substrate connected to the first fin and the second fin to electrically isolate the first fin from the second fin.

[0176] In certain embodiments of the method, removing the unetched portion of the semiconductor substrate connected to the first fin and the second fin to electrically isolate the first fin from the second fin includes forming a recessed back side of the first fin and a recessed back side of the second fin, and wherein the method further includes forming an isolation layer on the recessed back side of the first fin and on the recessed back side of the second fin.

[0177] In certain embodiments of the method, the first semiconductor device includes P-type epitaxial material; and the second semiconductor device includes N-type epitaxial material.

[0178] In certain embodiments of the method, forming a first semiconductor device over the first fin includes forming a first device region and a second device region adjacent to the first device region, wherein each of the first device region and the second device region includes a source feature and a drain feature over the first fin, an active region between the source feature and the drain feature, and a gate structure over the active region; and forming an isolation structure disposed in the first fin between the first device region and the second device region, wherein an underlying portion of the semiconductor substrate is disposed directly below the isolation structure; and wherein removing the unetched portion of the semiconductor substrate connected to the first fin and the second fin to electrically isolate the first fin from the second fin includes removing the underlying portion of the semiconductor substrate to electrically isolate the first device region from the second device region.

[0179] In certain embodiments of the method, the isolation structure is a dummy backside via including a conductive core surrounded by a dielectric layer.

[0180] In another embodiment, the method further includes forming an isolation layer disposed under each of the first fin and the second fin, wherein the isolation structure contacts the isolation layer.

[0181] In certain embodiments of the method, the isolation structure is formed by a continuous poly on diffusion edge (CPODE) process.

[0182] In certain embodiments of the method, each of the first device region and the second device region includes a termination active region; and the isolation structure is disposed between a plurality of the termination active regions.

[0183] Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that include: a first fin extending along an X direction and a second fin parallel to the first fin and spaced apart from the first fin along a Y direction perpendicular to the X direction, wherein each of the first fin and the second fin is formed with a first device region and a second device region arranged along the X direction; an isolation region disposed between the first fin and the second fin; an isolation structure disposed between the first device region and the second device region in each of the first fin and the second fin; as well as An isolation layer is provided below the first fin and the second fin, wherein the isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device region from the second device region in each of the first fin and the second fin.

2. The semiconductor structure according to claim 1, wherein: Each of the first device area and the second device area includes: a source feature and a drain feature over each of the fins; an active region between the source feature and the drain feature; and A gate structure is above the active area.

3. The semiconductor structure according to claim 2, wherein: Also includes: an active backside via in each of the first device region and the second device region contacting the source feature; as well as A backside interconnect structure is disposed below each of the first and second fins and adjacent to the isolation layer, wherein the active backside via contacts the backside interconnect structure.

4. The semiconductor structure according to claim 3, wherein: Also includes: A frontside interconnect structure is disposed over the source feature, the drain feature, and the gate structure in each of the first device region and the second device region.

5. A semiconductor structure, characterized in that include: a first device region and a second device region adjacent to the first device region, wherein each of the first device region and the second device region comprises: semiconductor substrates; a source feature and a drain feature over the semiconductor substrate; an active region between the source feature and the drain feature; and a gate structure over the active area; an isolation structure disposed between the semiconductor substrate in the first device region and the semiconductor substrate in the second device region; and Each of the semiconductor substrate in the first device region and the semiconductor substrate in the second device region terminates at a backside, and wherein the isolation structure extends to the backside.

6. The semiconductor structure according to claim 5, wherein: The isolation structure is a dummy backside via, which includes a conductive core surrounded by a dielectric layer.

7. The semiconductor structure according to claim 6, wherein: Also includes: An isolation layer is disposed below the backside of each of the semiconductor substrate in the first device region and the semiconductor substrate in the second device region, wherein the isolation structure contacts the isolation layer.

8. The semiconductor structure according to claim 7, wherein: Also includes: an active backside via in the first device region contacting the source feature; as well as A backside interconnect structure is disposed below the backside of the semiconductor substrate in the first device region and adjacent to the isolation layer, wherein the active backside via contacts the backside interconnect structure.

9. The semiconductor structure according to claim 6, wherein: in: Each of the first device region and the second device region includes a terminated active region; The semiconductor substrate further includes dummy features disposed between a plurality of the termination active regions; as well as The isolation structure contacts the dummy feature.

10. The semiconductor structure according to claim 5, wherein: The isolation structure is formed by a continuous poly on diffusion edge (CPODE) process.

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