Shield gate trench MOSFET device structure
By introducing a second epitaxial layer and body region into the shielded gate trench MOSFET device and optimizing the doping configuration, the contradiction between increasing the current density and maintaining the breakdown voltage is resolved, thereby achieving a reduction in on-resistance and power loss.
Patent Information
- Application Number
- CN202422751247.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-12
AI Technical Summary
When increasing the doping concentration of the epitaxial layer to improve the current density of existing shielded gate trench MOSFET devices, it is difficult to maintain the breakdown voltage, resulting in increased power loss.
A second epitaxial layer is introduced into the MOSFET device structure, and a body region is set between the first trench and the second trench. The doping concentration of the second epitaxial layer is increased to reduce the trench spacing. Combined with the formation of the shield gate structure and source polysilicon, the doping type and distance configuration are optimized.
While maintaining the breakdown voltage, the on-resistance Ron is reduced, thereby reducing the power loss of the MOSFET device.
Smart Images
Figure CN223452327U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit, concretely relates to shielded gate trench MOSFET device structure. BACKGROUND
[0002] Shielded gate trench MOSFET (SGT-MOSFET, Shielded Gate Trench MOSFET) is an advanced discrete device MOSFET structure, with the characteristics of high breakdown voltage, low on-resistance and fast switching speed. The structure of shielded gate trench MOSFET is generally that the polycrystalline silicon filled in the trench is divided into two parts: the polycrystalline silicon located at the lower part of the trench forms a shielded gate polycrystalline silicon, which is short-circuited with the source of the device; the polycrystalline silicon located at the upper part of the trench forms a polycrystalline silicon gate, and there is a silicon oxide film layer between the two layers of polycrystalline silicon.
[0003] With the development of technology, shielded gate trench MOSFET needs greater current density, i.e. smaller internal resistance under unit area, which can also reduce the power loss of MOSFET. Generally, the doping concentration of the epitaxial layer can be increased to achieve this, but if the doping concentration is simply increased, the breakdown voltage of the MOSFET cannot be maintained, and the breakdown voltage will be reduced. SUMMARY
[0004] In view of the deficiencies of the prior art, the utility model discloses a shielded gate trench MOSFET device structure.
[0005] The technical scheme adopted by the utility model is as follows:
[0006] A shielded gate trench MOSFET device structure, comprising a substrate and an epitaxial layer; the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer grown in the substrate in sequence; at least one MOSFET device unit is arranged in the epitaxial layer;
[0007] The MOSFET device unit comprises two groups of first trenches and a second trench located between the two groups of first trenches; a shielded gate structure is arranged in the first trench, and a source polycrystalline silicon structure is grown in the second trench; the two sides of the first trench and the body region doped between the first trench and the second trench.
[0008] Further technical features are that the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; the doping types of the second epitaxial layer and the first epitaxial layer are the same.
[0009] Further technical features are that in one MOSFET device unit, the distance between the two first trenches is 0.6 μm to 1.0 μm, and the distance between the first trench and the second trench is 0.2 to 0.4 μm.
[0010] Further, the shielding gate structure includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; the source polysilicon structure includes source polysilicon in the trench and a field oxide layer between the source polysilicon and the inner wall of the second trench.
[0011] Further, the MOSFET device unit further includes source regions formed on the body regions on both sides of the first trench; the source regions are electrically connected to the source polysilicon.
[0012] The manufacturing method of the shielding gate trench MOSFET device structure includes the following steps:
[0013] Growth of an epitaxial layer on a substrate; the epitaxial layer includes a first epitaxial layer grown on a substrate and a second epitaxial layer grown on the basis of the first epitaxial layer;
[0014] Formation of trenches on the epitaxial layer, the trenches including two groups of first trenches and a second trench between the two groups of first trenches; and formation of a dielectric layer as a field oxide layer on the bottom and sidewall of the trenches;
[0015] Formation of a shielding gate structure in the first trench and formation of a source polysilicon structure in the second trench; and doping of body regions on both sides of the first trench and between the first trench and the second trench; and doping of source regions on the body regions on both sides of the first trench.
[0016] Further, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the doping type of the second epitaxial layer is the same as that of the first epitaxial layer.
[0017] Further, the body regions are formed on both sides of the first trench and between the first trench and the second trench.
[0018] Further, the steps of forming the shielding gate structure and the source polysilicon structure specifically include:
[0019] Backfilling of the trench; deposition of source polysilicon in the trench, backfilling of the trench, and formation of a source polysilicon structure in the second trench;
[0020] Etching of the source polysilicon; through photolithography and etching, a target thickness of the source polysilicon is etched away in the first trench, and the thickness of the etched-away source polysilicon is less than the depth of the first trench;
[0021] Deposition of a dielectric layer; deposition of a dielectric layer in the first trench, backfilling of the first trench, and then photolithography and etching to etch away a target thickness of the dielectric layer to form an IPO oxide layer;
[0022] Growing gate oxide layer and gate polysilicon; growing gate oxide layer in the first trench, and depositing gate polysilicon, backfilling the first trench, at this time forming shield gate structure in the first trench.
[0023] Further technical features are that it further comprises the steps of forming contact hole and depositing metal: depositing contact hole medium layer of target thickness, then performing photoetching and etching to form contact hole, and depositing contact hole metal; and then depositing source metal.
[0024] The utility model discloses the beneficial effects are as follows:
[0025] The utility model discloses a MOSFET device unit is made in second epitaxial layer, is provided with second trench between two groups of first trench, and is doped as body region between first trench and second trench, relative to prior art, provided second trench and diffused to fill after body region between first trench and second trench, equivalent to reduce the distance between two first trench in prior art design, under the requirement of same breakdown voltage, the doping concentration of second epitaxial layer can increase, thereby resistivity is low, and on -resistance Ron reduces, and then can reduce the power loss of MOSFET device. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 It is the schematic diagram of forming trench step in the utility model embodiment.
[0027] Figure 2 It is the schematic diagram of backfilling trench step in the utility model embodiment.
[0028] Figure 3 It is the schematic diagram of etching source polysilicon step in the utility model embodiment.
[0029] Figure 4 It is the schematic diagram of depositing medium layer step in the utility model embodiment.
[0030] Figure 5 It is the schematic diagram of growing gate oxide layer and gate polysilicon step in the utility model embodiment.
[0031] Figure 6 It is the schematic diagram of forming body region and source region step in the utility model embodiment.
[0032] Figure 7 It is the schematic diagram of forming contact hole step in the utility model embodiment.
[0033] Figure 8 It is the schematic diagram of depositing metal step in the utility model embodiment.
[0034] In the figure: 100, substrate; 101, first epitaxial layer; 102, second epitaxial layer; 103, trench; 104, dielectric layer; 105, source polysilicon; 106, gate polysilicon; 107, body region; 108, source region; 109, contact hole metal; 110, source metal. DETAILED DESCRIPTION
[0035] The specific embodiment of the present application is described below in combination with the drawings.
[0036] Figure 8 The figure is a schematic diagram of the metal depositing step in the embodiment of the present application, and simultaneously, Figure 8 comprehensively displays the shielded gate trench MOSFET device structure in the embodiment. As shown in the figure, Figure 8 the shielded gate trench MOSFET device structure includes a substrate 100 and an epitaxial layer grown on the substrate 100. The epitaxial layer includes a first epitaxial layer 101 and a second epitaxial layer 102 grown on the substrate 100 in sequence.
[0037] At least one MOSFET device unit is arranged in the epitaxial layer 102. The MOSFET device unit includes a trench 103. Generally, the MOSFET device unit is mainly grown on the second epitaxial layer 102, and the thickness of the second epitaxial layer 102 is slightly smaller than the depth of the trench 103 of the MOSFET device unit. The trench 103 includes two groups of first trenches and a second trench located between the two groups of first trenches.
[0038] A shielded gate structure is arranged in the first trench. Specifically, the shielded gate structure includes gate polysilicon 106 and source polysilicon 105. The source polysilicon 105 and the inner wall of the first trench form a field oxide layer, and the gate polysilicon 106 and the inner wall of the first trench form a gate oxide layer. The source polysilicon 105 and the gate polysilicon 106 form an IPO oxide layer.
[0039] A source polysilicon structure is grown in the second trench. Specifically, the source polysilicon structure includes source polysilicon 105 in the second trench and field oxide layer between the source polysilicon 105 and the inner wall of the second trench.
[0040] The two sides of the first trench and the body region 107 doped between the first trench and the second trench, the source region 108 is grown on the body region 107 on the two sides of the first trench, the source region 108 is short-circuited with the source metal 110 through the contact hole metal 109 as the source of the device, and the source region 108 is simultaneously short-circuited with the source polysilicon 105 inside the MOSFET device.
[0041] The doping concentration of the second epitaxial layer 102 is greater than that of the first epitaxial layer 101. The second epitaxial layer 102 and the first epitaxial layer 101 have the same doping type. The specific doping concentration and doping type can be determined by those skilled in the art based on the functional parameters and model of the device. For example, for a device with a maximum operating voltage of 30V, the doping concentration of the first epitaxial layer 101 can be 7×10 15 atoms / cm 3 , the doping concentration of the second epitaxial layer 102 may be 8×10 15 atoms / cm 3 , the first epitaxial layer 101 and the second epitaxial layer 102 are both N-type.
[0042] Preferably, the distance between the two first grooves is 0.55 μm to 0.65 μm, for example, 0.6 μm, and the distance between the first groove and the second groove is 0.15 μm to 0.25 μm, for example, 0.2 μm.
[0043] Compared with the existing technology, such a MOSFET device structure is equivalent to reducing the distance between the two first trenches in the existing design. Under the same breakdown voltage requirement, the doping concentration of the second epitaxial layer can be increased, thereby lowering the resistivity and reducing the on-resistance Ron, thereby reducing the power loss of the MOSFET device.
[0044] This embodiment also discloses a method for manufacturing the shielded gate trench MOSFET device structure described above. The MOSFET device structure includes at least one MOSFET device unit. The following are steps for manufacturing a MOSFET device unit, specifically including:
[0045] Step 1: Forming a groove. Figure 1 Schematic diagram of the step of forming a groove in the embodiment of the present invention. Figure 1 As shown, epitaxial layers are grown on substrate 100. Specifically, a first epitaxial layer 101 having a target thickness and a target doping concentration is formed on substrate 100, and a second epitaxial layer 102 having a target thickness and a target doping concentration is formed on the first epitaxial layer 101. The doping concentration of second epitaxial layer 102 is greater than that of first epitaxial layer 101. The second epitaxial layer 102 and the first epitaxial layer 101 have the same doping type.
[0046] The trenches 103 are formed by a first photolithography, etching and other processes. The trenches 103 include two groups of first trenches and a second trench located between the two groups of first trenches.
[0047] A dielectric layer 104 of target thickness is formed on the bottom and sidewalls of the trench 103 by, but not limited to, thermal oxidation, CVD deposition, etc., serving as a field oxide layer.
[0048] The target thickness and the target doping concentration in this step and the following steps are determined according to the device model and the functional parameters, and can be adjusted according to the known technology by those skilled in the art.
[0049] Step 2, backfilling the trench. Figure 2 The figure is a schematic diagram of the backfilling trench step in the embodiment of the utility model. As shown in the figure, Figure 2 the source polysilicon 105 is deposited in the trench 103, the trench 103 is backfilled, and the surface of the trench 103 is planarized by CMP. At this time, the source polysilicon structure is formed in the second trench.
[0050] Step 3, etching the source polysilicon. Figure 3 The figure is a schematic diagram of the etching source polysilicon step in the embodiment of the utility model. As shown in the figure, Figure 3 the target thickness of the source polysilicon 105 is etched away in the first trench through the second photolithography and etching. The thickness of the etched away source polysilicon 105 is smaller than the depth of the first trench.
[0051] Step 4, depositing a dielectric layer. Figure 4 The figure is a schematic diagram of the depositing dielectric layer step in the embodiment of the utility model. The target thickness of the silicon oxide dielectric layer is deposited in the first trench, the first trench is backfilled, and the silicon surface is planarized by CMP. Then, the third photolithography and etching are performed to etch away the target thickness of the dielectric layer as the IPO oxide layer, so that it is finally as shown in the figure. Figure 4
[0052] Step 5, growing the gate oxide layer and the gate polysilicon. Figure 5 The figure is a schematic diagram of the growing gate oxide layer and gate polysilicon step in the embodiment of the utility model. As shown in the figure, Figure 5 after cleaning, the target thickness of the gate oxide layer is grown in the first trench, and the target thickness of the gate polysilicon 106 is deposited. The first trench is backfilled, and the surface is planarized by CMP. At this time, the shield gate structure is formed in the first trench.
[0053] Step 6, forming the body region and the source region. Figure 6 The figure is a schematic diagram of the forming body region and source region step in the embodiment of the utility model. As shown in the figure, Figure 6 impurities are implanted and annealed to form the body region 107. Then, the fourth photolithography process is performed to implant impurities to form the device source region 108. Specifically, the body region 107 is formed on both sides of the first trench and between the first trench and the second trench. In this embodiment, the body region 107 is implanted with P-type impurities, and the source region 108 is implanted with N-type impurities. The source region 108 is electrically connected with the source polysilicon 105.
[0054] Step 7, forming the contact hole. Figure 7 The figure is a schematic diagram of the forming contact hole step in the embodiment of the utility model. As shown in the figure, Figure 7 As shown, the contact hole medium layer of the target thickness is deposited, then the fifth photoetching process is performed, etching is performed to form the contact hole, and the contact hole metal 109 is deposited.
[0055] Step 8, depositing metal. Figure 8 The figure is a schematic diagram of the step of depositing metal in the embodiment of the utility model. As shown, Figure 8 The source metal 110 is deposited. The contact hole metal 109 electrically connects the source region 108 and the source metal 110.
[0056] Then the sixth photoetching process is performed, metal etching is performed, the protective medium layer is deposited, the seventh photoetching is performed, the protective medium layer is etched to form the MOSFET device protective layer.
[0057] Through the above MOSFET manufacturing process, the MOSFET device structure as shown in Figure 8 is formed. Under the same breakdown voltage requirement, the on-resistance Ron of the device is reduced, and the power loss of the MOSFET device can be reduced.
[0058] In the embodiment, the specific process parameters of steps 1 to 8 are adjusted and selected by the person skilled in the art according to the general process knowledge of integrated circuits and the device parameter requirements, and the specific process parameters are not the content to be protected by the application, and will not be described herein.
[0059] The above description is an explanation of the utility model, not a limitation of the utility model, the range defined by the utility model is referred to the claims, the utility model can be modified in any form without violating the basic structure of the utility model.
Claims
1. A shielded gate trench MOSFET device structure, characterized in that: The device comprises a substrate and an epitaxial layer; the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer sequentially grown on the substrate; at least one MOSFET device unit is provided in the epitaxial layer; The MOSFET device unit includes two groups of first trenches and a second trench located between the two groups of the first trenches; a shielding gate structure is arranged in the first trench, and an active polysilicon structure is grown in the second trench; both sides of the first trench and between the first trench and the second trench are doped into body regions.
2. The shielded gate trench MOSFET device structure according to claim 1, wherein: The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the second epitaxial layer and the first epitaxial layer have the same doping type.
3. The shielded gate trench MOSFET device structure according to claim 1, wherein: In a MOSFET device unit, the distance between two first trenches is 0.6 μm to 1.0 μm, and the distance between the first trench and the second trench is 0.2 to 0.4 μm.
4. The shielded gate trench MOSFET device structure according to claim 1, wherein: The shielding gate structure includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; the source polysilicon structure includes the source polysilicon in the trench and the field oxide layer between the source polysilicon and the inner wall of the second trench.
5. The shielded gate trench MOSFET device structure according to claim 1, wherein: The MOSFET device unit further includes a source region formed on the body region on both sides of the first trench; the source region is electrically connected to the source polysilicon.