BMS active equalization test circuit

Abstract

The utility model discloses a BMS (Battery Management System) active equalization test circuit, which relates to the field of batteries and comprises a main control module used for controlling an equalization module to work or not through an isolation driving module and controlling active equalization; receiving a current sampling signal of the sampling module; communicating with the tested board; the isolation driving module is used for receiving the control signal of the main control module, and feeding back the control signal to the equalization module after isolation; the beneficial effects of the utility model are that when a bidirectional DCDC power supply is not used, a load circuit is provided, and test verification of the active equalization module is realized; meanwhile, a BUCK-BOOST converter is adopted in a traditional bidirectional DCDC power supply, bidirectional current flowing can be achieved, however, due to the fact that the number of simulated battery cells of a BMS is large, overall control is complex, and cost is large, a resistor is directly connected to the output end of the balance current in parallel to serve as a load, and the problems of high cost and complex control can be directly solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a battery field, concretely is a BMS initiative equalization test circuit. BACKGROUND

[0002] BMS (battery management system) is a key system in the field of electric vehicles, energy storage systems, etc., used to monitor the state of the battery, ensuring the safety, reliability and efficient operation of the battery.

[0003] The initiative equalization technology of the battery cell is to use a certain way to charge and discharge between two battery cells with pressure difference, so as to eliminate the pressure difference; the implementation process of initiative equalization can be simplified as using DCDC converter to charge the battery cell with low voltage with the battery cell with high voltage; when initiative equalization, the current between the two battery cells must be one flowing out of the positive electrode of the high-voltage battery cell and one flowing into the positive electrode of the low-voltage battery cell; when two power supplies are connected in parallel to supply power to a load, the current on the power supply supply branch must be smaller.

[0004] The battery cell simulation circuit obtained by using the current bidirectional DCD power supply C grading cannot provide a load circuit during initiative equalization, which is not convenient for testing the initiative equalization effect and needs to be improved. UTILITY MODEL CONTENT

[0005] The utility model aims at providing a BMS initiative equalization test circuit to solve the problems in the above background technology.

[0006] To achieve the above purpose, the utility model provides the following technical scheme:

[0007] A BMS initiative equalization test circuit, comprising:

[0008] A master control module is used to control whether the equalization module works or not through an isolation driving module, control the initiative equalization, receive the current sampling signal of the sampling module, and communicate with the measured board;

[0009] An isolation driving module is used to receive the control signal of the master control module and feedback to the equalization module after isolation;

[0010] An equalization module is used to open the equalization channel switch when working;

[0011] A sampling module is used to sample the current of the equalization module, obtain the current sampling signal, and output to the master control module;

[0012] The master control module is connected with the isolation driving module, the isolation driving module is connected with the equalization module, the equalization module is connected with the sampling module, and the sampling module is connected with the master control module.

[0013] As a further scheme of the utility model: the main control module includes chip U54, the model number of chip U54 is GD32F103RB, the 8th pin of chip U54 is connected isolation driving module through a resistance, and the 20th pin of chip U54 is connected sampling module.

[0014] As a further scheme of the utility model: the isolation driving module includes triode Q44, photoelectric coupler U79, the base of triode Q44 is connected main control module, the emitter of triode Q44 is grounded, the collector of triode Q44 is connected the second end of photoelectric coupler U79, the first end of photoelectric coupler U79 is connected 3.3V voltage, the third end of photoelectric coupler U79 is grounded, and the fourth end of photoelectric coupler U79 is connected one end of resistance R207, equalization module, and the other end of resistance R207 is connected 5V voltage.

[0015] As a further scheme of the utility model: the equalization module includes MOS tube U27, MOS tube U30, the S pole of MOS tube U27 is connected one end of resistance R97, first battery channel, the other end of resistance R97 is connected the output end of voltage stabilizer U26, the D pole of MOS tube U27 is connected one end of resistance R63, and the other end of resistance R63 is connected first battery channel;

[0016] the D pole of MOS tube U30 is connected one end of resistance R70, second battery channel, the other end of resistance R70 is connected the output end of voltage stabilizer U29 through resistance R29, and the S pole of MOS tube U30 is connected second battery channel, the G pole of MOS tube U27 is connected the G pole of MOS tube U30, and isolation driving module.

[0017] As a further scheme of the utility model: the sampling module includes chip U32, chip U33, chip U74, the model number of chip U32 and U33 is CSA231NATSSOP8, the model number of chip U74 is CD74HC4067M96, the 2nd end and 3rd end of chip U32 are connected equalization module, the 6th end and 7th end of chip U32 are connected 1.225V voltage, the 8th pin of chip U32 is connected the 9th pin of chip U74, the 2nd end and 3rd end of chip U33 are connected equalization module, the 6th end and 7th end of chip U33 are connected 1.225V voltage, the 8th pin of chip U33 is connected the 8th pin of chip U74, and the 1st pin of chip U74 is connected main control module.

[0018] Compared with the prior art, the utility model discloses the beneficial effects are: the utility model discloses when not using bidirectional DCDC power supply, provide load circuit, realize the test and verification of initiative equalization module, simultaneously, the traditional bidirectional DCDC power supply adopts BUCK-BOOST converter, can realize the current flow of bidirectional, but due to the great number of BMS's electric core simulation, the overall control is complex and the cost is big, therefore, the utility model directly parallel resistance as load at the output of equalization current, can directly solve the problem of high cost and control complex. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is the circuit diagram of main control module.

[0020] Figure 2 It is the circuit diagram of isolation drive module.

[0021] Figure 3 It is the circuit diagram of equalization module.

[0022] Figure 4 It is the circuit diagram of sampling module.

[0023] Figure 5 It is the circuit diagram of electric core channel conduction control.

[0024] Figure 6 It is the circuit diagram of electric core channel work. DETAILED DESCRIPTION

[0025] The technical scheme in the embodiments of the utility model will be described clearly and completely below in conjunction with the drawings in the embodiments of the utility model, obviously, the described embodiments are only a part of the embodiments of the utility model, not all the embodiments, based on the embodiments in the utility model, all other embodiments obtained by the ordinary skill in the art without making creative labor belong to the range of protection of the utility model.

[0026] Please refer to Figures 1 to 4 A BMS initiative equalization test circuit, comprising:

[0027] The main control module is used for controlling whether the equalization module works through the isolation drive module, controlling the initiative equalization, receiving the current sampling signal of the sampling module, and communicating with the measured board.

[0028] The isolation drive module is used for receiving the control signal of the main control module and feeding back to the equalization module after isolation.

[0029] The equalization module is used for opening the equalization channel switch when working.

[0030] The sampling module is used for sampling the current when the equalization module works, obtaining the current sampling signal, and outputting to the main control module.

[0031] The main control module is connected with the isolation driving module, the isolation driving module is connected with the equalization module, the equalization module is connected with the sampling module, and the sampling module is connected with the main control module.

[0032] In the embodiment, please refer to Figure 1 The main control module comprises a chip U54, the model number of the chip U54 is GD32F103RB, the No. 8 pin of the chip U54 is connected with the isolation driving module through a resistor, and the No. 20 pin of the chip U54 is connected with the sampling module.

[0033] The chip U54 controls the circuit to work.

[0034] In the embodiment, please refer to Figure 2 The isolation driving module comprises a triode Q44 and an optical coupler U79, the base of the triode Q44 is connected with the main control module, the emitter of the triode Q44 is grounded, the collector of the triode Q44 is connected with the second end of the optical coupler U79, the first end of the optical coupler U79 is connected with a 3.3V voltage, the third end of the optical coupler U79 is grounded, and the fourth end of the optical coupler U79 is connected with one end of a resistor R207 and the equalization module, and the other end of the resistor R207 is connected with a 5V voltage.

[0035] When the No. 8 pin of the chip U54 outputs a high level, the triode Q44 is turned on, so that a voltage difference is formed at both ends of an internal light-emitting diode of the optical coupler U79, an internal photosensitive triode of the optical coupler U79 is turned on, the voltage of EN1&2 is pulled down, and the voltage is fed back to the equalization module; conversely, when the No. 8 pin of the chip U54 outputs a low level, the voltage of EN1&2 is a high level.

[0036] In the embodiment, please refer to Figure 3 The equalization module comprises MOS tubes U27 and U30, the S pole of the MOS tube U27 is connected with one end of a resistor R97 and a first battery channel, the other end of the resistor R97 is connected with the output end of a voltage stabilizer U26, the D pole of the MOS tube U27 is connected with one end of a resistor R63, and the other end of the resistor R63 is connected with the first battery channel.

[0037] The D pole of the MOS tube U30 is connected with one end of a resistor R70 and a second battery channel, the other end of the resistor R70 is connected with the output end of a voltage stabilizer U29 through a resistor R29, the S pole of the MOS tube U30 is connected with the second battery channel, and the G pole of the MOS tube U27 is connected with the G pole of the MOS tube U30 and the isolation driving module.

[0038] Please refer to Figure 5 and Figure 6 for an example of the battery channel, in application, Figure 3 the 0 and 1 of the connector network are connected to Figure 5V1_A and V2_A of the network, MOS is turned on after the equalization is opened, CL1_A & CU1_A is connected, the corresponding back-stage equalization battery channel is opened, see Figure 6 , the equalization work is started. The connection mode of the connectors 2 and 3 of the network is the same, and is not described.

[0039] Correction: If the S pole of U27 is not connected to a battery or any analog battery, but is connected to an active equalization circuit; this patent provides an analog battery circuit and also provides a loop for the equalization circuit to flow.

[0040] The test board provides I2C communication (at the SDA and SCL of chip U54) with the test board (BMS active equalization test circuit), and after the active equalization function of the test board is enabled, the active equalization chip is enabled to open the equalization between one battery and another battery, for example, one battery is high voltage and the other battery is low voltage; the MCU (chip U54) sends DRV_1 & 2 signals to the gate of the MOS through the isolation of the optocoupler, and because PMOS (U27) and NMOS (U30) are used as load channel switch control, only one MOS is turned on when the drive signal is high or low, thereby providing a load branch. Taking the conduction of MOS U30 as an example, because the equalization function is opened, the active equalization circuit of the test board charges the battery, that is, a DC source (additional power supply) is connected in parallel across the resistor R70, at this time, the output of the external equalization chip and the output of the voltage stabilizer U29 (always present power supply) are both supplying power to the resistor R70, if the current of the stabilizer U29 power supply branch is measured at this time, according to Ohm's law, The resistance of the external resistor R70 is fixed, the supply voltage of the voltage stabilizer U29 is unchanged, and an additional power supply is added, so the branch current should be obviously different from the current supplied by the voltage stabilizer U29 alone to the load (resistor R70), assuming that the current supplied by the voltage stabilizer U29 alone is I1, then the branch current I2 after the equalization is opened should be less than I1. The current is collected through the sampling circuit and input to the host module as a judgment basis.

[0041] Figure 3 In the middle, chip U25, U28 and their peripheral devices are 24V to 5V DCDC chips and filter circuits; chip U26, U29 and their peripheral devices are manually adjustable 5V power supply; resistors R98, R97 are current sampling resistors with very small resistance; U27, U30 are active equalization channel switch MOS.

[0042] In this embodiment: please refer to Figure 4The sampling module comprises a chip U32, a chip U33 and a chip U74, the model of the chip U32 and the chip U33 is CSA231NATSSOP8, the model of the chip U74 is CD74HC4067M96, the 2nd and 3rd ends of the chip U32 are connected with the equalization module, the 6th and 7th ends of the chip U32 are connected with a 1.225V voltage, the 8th pin of the chip U32 is connected with the 9th pin of the chip U74, the 2nd and 3rd ends of the chip U33 are connected with the equalization module, the 6th and 7th ends of the chip U33 are connected with the 1.225V voltage, the 8th pin of the chip U33 is connected with the 8th pin of the chip U74, and the 1st pin of the chip U74 is connected with the main control module.

[0043] The sampling module samples current information and transmits the current information to the main control module; the isolation driving module, the equalization module and the sampling module are all provided with a plurality of modules, only one module is shown in the drawing (in the drawing, fourteen pins of the 2nd to 9th pins and the 18th to 23rd pins of the chip U74 collect signals, which indicates that there are seven sampling modules, and the chip U54 is provided with DRV_1&2 to DRV_13&14, which also indicates that there are seven isolation driving modules, equalization modules), and the number of the isolation driving module, the equalization module and the sampling module is not limited in actual use.

[0044] The working principle of the utility model is: the main control module is used for controlling whether the equalization module works through the isolation driving module, and is used for controlling active equalization; receiving current sampling signals of the sampling module; communicating with a measured board; the isolation driving module is used for receiving control signals of the main control module, and is used for feeding back to the equalization module after isolation; the equalization module is used for opening equalization channel switches when working; the sampling module is used for sampling currents of the equalization module, obtaining current sampling signals and outputting the current sampling signals to the main control module.

[0045] For those skilled in the art, it is obvious that the utility model is not limited to the details of the above-mentioned exemplary embodiments, and the utility model can be realized in other specific forms without departing from the spirit or basic characteristics of the utility model. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-limiting.

[0046] In addition, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be properly combined to form other embodiments that those skilled in the art can understand.

Claims

1. A BMS active equalization test circuit, characterized in that, The BMS active balancing test circuit comprises: A main control module, which is used for controlling whether the balancing module works or not through an isolation driving module, controlling active balancing, receiving a current sampling signal of a sampling module, and communicating with a measured board; An isolation driving module, which is used for receiving a control signal of the main control module and feeding back to the balancing module after isolation; A balancing module, which is used for opening a balancing channel switch when working; A sampling module, which is used for sampling a current of the balancing module, obtaining a current sampling signal, and outputting the current sampling signal to the main control module; The main control module is connected with the isolation driving module, the isolation driving module is connected with the balancing module, the balancing module is connected with the sampling module, and the sampling module is connected with the main control module.

2. The BMS active equalization test circuit of claim 1, wherein, The main control module comprises a chip U54, the model number of the chip U54 is GD32F103RB, a pin 8 of the chip U54 is connected with the isolation driving module through a resistor, and a pin 20 of the chip U54 is connected with the sampling module.

3. The BMS active equalization test circuit of claim 1, wherein, The isolation driving module comprises a triode Q44 and an optical coupler U79, a base of the triode Q44 is connected with the main control module, an emitter of the triode Q44 is grounded, a collector of the triode Q44 is connected with a second end of the optical coupler U79, a first end of the optical coupler U79 is connected with a 3.3V voltage, a third end of the optical coupler U79 is grounded, and a fourth end of the optical coupler U79 is connected with one end of a resistor R207 and the balancing module, and the other end of the resistor R207 is connected with a 5V voltage.

4. The BMS active equalization test circuit of claim 3, wherein, The balancing module comprises MOS tubes U27 and U30, an S pole of the MOS tube U27 is connected with one end of a resistor R97 and a first cell channel, the other end of the resistor R97 is connected with an output end of a voltage stabilizer U26, a D pole of the MOS tube U27 is connected with one end of a resistor R63, and the other end of the resistor R63 is connected with the first cell channel; a D pole of the MOS tube U30 is connected with one end of a resistor R70 and a second cell channel, the other end of the resistor R70 is connected with an output end of a voltage stabilizer U29 through a resistor R29, and an S pole of the MOS tube U30 is connected with the second cell channel; a G pole of the MOS tube U27 is connected with a G pole of the MOS tube U30 and the isolation driving module.

5. The BMS active equalization test circuit of claim 1, wherein, The sampling module comprises chips U32, U33 and U74, the model numbers of the chips U32 and U33 are CSA231NATSSOP8, the model number of the chip U74 is CD74HC4067M96, 2 and 3 ends of the chip U32 are connected with the balancing module, 6 and 7 ends of the chip U32 are connected with a 1.225V voltage, an 8 pin of the chip U32 is connected with a 9 pin of the chip U74, 2 and 3 ends of the chip U33 are connected with the balancing module, 6 and 7 ends of the chip U33 are connected with the 1.225V voltage, an 8 pin of the chip U33 is connected with an 8 pin of the chip U74, and a 1 pin of the chip U74 is connected with the main control module.

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