Double-pulse test circuit based on power semiconductor and test circuit board

Abstract

The utility model relates to the technical field of electronic circuits, in particular to a dipulse test circuit based on a power semiconductor. The inductance selection and position switching circuit for the power semiconductor dipulse test is formed by the at least two load inductance selection branches, the first position switching branch, the second position switching branch and the power semiconductor to be tested, and the inductance connected into the test circuit is changed through the load inductance selection branches when the inductance selection and position switching circuit is used. The position change of the to-be-tested power semiconductor is realized through the position switching circuit, and the device has the characteristics of high reliability, fast switching and stable test.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field especially relates to a double pulse test circuit and test circuit board based on power semiconductor. BACKGROUND

[0002] Power semiconductor is used for the power electronic device of electric energy conversion and control circuit aspect of electric power equipment, and it is almost used in all electronic manufacturing industry, including notebook, PC, server, display and various peripherals in computer field, mobile phone, telephone and other various terminal and local equipment in network communication field, and automobile power conversion etc.

[0003] When applying power device in various fields, it is needed to test various power devices and select suitable device, at present, the selection of power device is mainly based on datasheet provided by manufacturer, these data are based on some established test circuit, and there is big difference with actual application circuit, therefore, we need to test various indexes of IGBT in specific application circuit to evaluate the performance of overall circuit (including main loop, drive circuit etc.), the prior art adopts manual replacement of load inductance and manual change of inductance upper and lower bridge position mode for double pulse test of MOS, IGBT and other power semiconductor, since inductance value is unstable (inductance is easy to be deformed by knock in the process of inductance replacement, and inductance value deviation occurs), line is easy to be damaged in change, resulting in big deviation of test result, and the operation is complicated and consumes test time.

[0004] Therefore, a circuit for quickly completing power semiconductor test is needed, and the test of power device is faster and more accurate. UTILITY MODEL CONTENT

[0005] In view of the deficiencies in the prior art, the utility model provides a double pulse test circuit and test circuit board based on power semiconductor, the test circuit adds switching circuit in the test circuit of power semiconductor, selects load inductance and changes inductance position automatically by controlling switching switch, so as to achieve the purpose of inductance quick selection and inductance position (upper and lower bridge) quick switching.

[0006] The utility model discloses a kind of double-pulse test circuits based on power semiconductor, including at least two load inductance selection branches, first position switching branch, second position switching branch, first test interface, second test interface and third test interface;Wherein load inductance selection branch includes inductance and switching switch, the first end of switching switch is connected with second test interface, the second end of switching switch is connected with the first end of inductance, the second end of inductance is connected with the first end of first position switching branch and the first end of second position switching branch respectively;The second end of first position switching branch is connected with first test interface, the second end of second position switching branch is connected with third test interface;First test interface is also used to connect the anode of direct current power supply, third test interface is also used to connect the cathode of direct current power supply.

[0007] Further, in the technical solution, the power semiconductor includes an IGBT tube or a MOS tube.

[0008] When testing the IGBT tube, the emitter and collector of the first IGBT tube to be tested are connected with the first test interface and the second test interface respectively, and the emitter and collector of the second IGBT tube to be tested are connected with the second test interface and the third test interface respectively.

[0009] When testing the MOS tube, the source and drain of the first MOS tube to be tested are connected with the first test interface and the second test interface respectively, and the drain and source of the second MOS tube to be tested are connected with the second test interface and the third test interface respectively.

[0010] Further, the load inductance selection branch includes a first load inductance selection branch, a second load inductance selection branch, a third load inductance selection branch and a fourth load inductance selection branch.

[0011] The first load inductance selection branch includes a first inductance and a first switching switch, the first end of the first switching switch is connected with the second test interface, the second end of the first switching switch is connected with the first end of the first inductance, and the second end of the first inductance is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively.

[0012] The second load inductance selection branch includes a second inductance and a second switching switch, the first end of the second switching switch is connected with the second test interface, the second end of the second switching switch is connected with the first end of the second inductance, and the second end of the second inductance is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively.

[0013] The third load inductance selection branch includes a third inductance and a third switch, the first end of the third switch is connected with the second test interface, the second end of the third switch is connected with the first end of the third inductance, and the second end of the third inductance is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively.

[0014] The fourth load inductance selection branch includes a fourth inductance and a fourth switch, the first end of the fourth switch is connected with the second test interface, the second end of the fourth switch is connected with the first end of the fourth inductance, and the second end of the fourth inductance is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively.

[0015] Further, the first inductance, the second inductance, the third inductance and the fourth inductance all include a hollow coil, and no magnetic core or a magnetic core of different sizes is arranged in the hollow coil. The inductance is composed of a hollow coil, and no magnetic core or a magnetic core of different sizes is arranged in the coil. The influence of the magnetic core on the inductance of the coil changes more, which can meet different needs.

[0016] Further, the switch includes a relay or an electrically controlled switch; the control end of the relay or the electrically controlled switch is connected with the inductance switching signal, for controlling the conduction or closure of the switch. The relay or the electrically controlled switch is controlled by the control signal, and the inductance is further controlled whether to be connected to the circuit or the number of inductances connected to the circuit. It is not necessary to manually touch the inductance and other devices on the test circuit of the power device, so that the inductance is not easy to be bumped and deformed, the inductance value is deviated, and the inductance is increased or changed faster.

[0017] Further, the switch includes a switching triode; the collector of the switching triode is connected with the second test interface, the emitter of the switching triode is connected with the first end of the inductance, and the base of the switching triode is connected with the inductance switching signal for controlling the conduction or cut-off of the switching triode. The switching triode has the characteristics of long service life, safety and reliability, no mechanical wear, fast switching speed and small size, which can improve the reliability and service life of the circuit.

[0018] Further, the switch includes an NMOS tube; the source of the NMOS tube is connected with the second test interface, the drain of the NMOS tube is connected with the first end of the inductance, and the gate of the NMOS tube is connected with the inductance switching signal for controlling the conduction or cut-off of the NMOS tube. The NMOS tube has the characteristics of fast switching speed and supporting high-power test circuit.

[0019] Further, the first position switching branch includes a relay or an electrically controlled switch, and the second position switching branch includes a relay or an electrically controlled switch; the control end of the relay or the electrically controlled switch is connected with the position switching signal, for controlling the conduction or closure of the first position switching branch or the second position switching branch.

[0020] In order to achieve the above object, the utility model also provides a test fixture, it includes above based on power semiconductor's double pulse test circuit.

[0021] Compared with prior art, the utility model has following beneficial effects: when using, the IGBT pipe or MOS pipe of to be measured is connected according to above-mentioned mode, the inductance of access circuit is controlled through load inductance selection branch or the branch of testing is changed through position switching branch.It has the characteristics of quick selection inductance, automatic change inductance position, fast switching, and the circuit itself also has the advantages of stability and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical scheme of the utility model, be favorable to the technical effect, technical features and purpose of the utility model further understanding, the utility model is described in detail below with the accompanying drawings, and the accompanying drawings constitute the necessary component of the specification, and with the embodiment of the utility model, it is used to explain the technical scheme of the utility model, but does not constitute the limitation of the utility model.

[0023] Figure 1 The double pulse test circuit based on power semiconductor recorded in the utility model is shown in the figure;

[0024] Figure 2 The double pulse test circuit based on power semiconductor recorded in the utility model is shown in the figure;

[0025] Figure 3 The double pulse test circuit based on power semiconductor recorded in the utility model is shown in the figure. DETAILED DESCRIPTION

[0026] The utility model is further described in detail below with the accompanying drawings and embodiment. Of course, the following description of specific embodiment is only for explaining the technical scheme of the utility model, and is not the limitation of the utility model. In addition, the part expressed in the embodiment or the accompanying drawings, only is the example of the relevant part of the utility model, and is not the whole of the utility model. Meanwhile, all other embodiments obtained by the ordinary skill in the art based on the embodiment of the utility model, should certainly belong to the protection scope of the utility model.

[0027] As Figure 1As shown, the utility model discloses a kind of double-pulse test circuit based on power semiconductor, including 4-way load inductance selection branch, first position switching branch, second position switching branch, first test interface, second test interface and third test interface;Wherein load inductance selection branch includes inductance and switching switch, the first end of switching switch is connected with second test interface, the second end of switching switch is connected with the first end of inductance, the second end of inductance is connected with the first end of first position switching branch and the first end of second position switching branch respectively;The second end of first position switching branch is connected with first test interface, the second end of second position switching branch is connected with third test interface;First test interface is also used to connect the anode of direct current power supply, third test interface is also used to connect the cathode of direct current power supply.

[0028] As Figure 1 Shown in the embodiment, load inductance selection branch includes first load inductance selection branch, second load inductance selection branch, third load inductance selection branch and fourth load inductance selection branch;First load inductance selection branch includes first inductance L1 and first switching switch SW1, the first end of first switching switch SW1 is connected with second test interface IN2, the second end of first switching switch SW1 is connected with the first end of first inductance L1, the second end of first inductance L1 is connected with the first end of first position switching branch and the first end of second position switching branch respectively;Second load inductance selection branch includes second inductance L2 and second switching switch SW2, the first end of second switching switch SW2 is connected with second test interface IN2, the second end of second switching switch SW2 is connected with the first end of second inductance L2, the second end of second inductance L2 is connected with the first end of first position switching branch and the first end of second position switching branch respectively;Third load inductance selection branch includes third inductance L3 and third switching switch SW3, the first end of third switching switch SW3 is connected with second test interface IN2, the second end of third switching switch SW3 is connected with the first end of third inductance L3, the second end of third inductance L3 is connected with the first end of first position switching branch and the first end of second position switching branch respectively;Fourth load inductance selection branch includes fourth inductance L4 and fourth switching switch SW4, the first end of fourth switching switch SW4 is connected with second test interface IN2, the second end of fourth switching switch SW2 is connected with the first end of fourth inductance L4, the second end of fourth inductance L4 is connected with the first end of first position switching branch and the first end of second position switching branch respectively.

[0029] In the embodiment, switching switch uses 4 electrically controlled switches;The control end of 4 switching switches is connected inductance switching signal Signal1-Signal4 respectively, for controlling the conduction or closure of switching switch.

[0030] In the embodiment, the first position switching branch is an electrically controlled switch SW5, and the second position switching branch is an electrically controlled switch SW6; control ends of the electrically controlled switches are connected with position switching signals Signal5 and Signal6 respectively, and are used for controlling the conduction or closure of the first position switching branch or the second position switching branch.

[0031] As shown in the figure, Figure 1 In the embodiment, the measured power semiconductor is a MOSFET. Among them, the collector of the first MOS tube Q1 to be measured and the emitter of the second MOS tube Q2 to be measured are connected to form a half bridge, and AC in the figure is the alternating current output end of the half bridge, DC+ and DC- are the positive and negative poles of the external direct current power supply input voltage respectively, and the voltage range can be adjusted according to the withstand voltage of the MOS tube. The collector of the first MOS tube Q1 is connected with the second test interface, the emitter of the first MOS tube Q1 is connected with the first test interface IN1 (that is, finally connected with one end of the electrically controlled switch SW5), and the collector of the second MOS tube Q2 is connected with the third test interface IN3 (that is, finally connected with one end of the electrically controlled switch SW6).

[0032] As shown in the figure, Figure 2 Action signals are applied to Signal1, Signal2, Signal3 and Signal4, and SW1, SW2, SW3 and SW4 are controlled to keep closed or keep open to select corresponding inductors L1, L2, L3 and L4. The inductor position is controlled by Signal5 to keep SW5 closed to select DC+ connection, to form a single inductor loop or multiple inductor parallel loops. The loop selects any one or more of L1, L2, L3 and L4 to keep the inductance value stable, and is placed between DC+ and AC of the upper bridge first MOS tube Q1 to form a double pulse test circuit for testing the lower bridge second MOS tube Q2, and then the required test is performed.

[0033] As shown in the figure, Figure 3 Action signals are applied to Signal1, Signal2, Signal3 and Signal4, and SW1, SW2, SW3 and SW4 are controlled to keep closed or keep open to select corresponding inductors L1, L2, L3 and L4. The inductor position is controlled by Signal6 to keep SW6 closed to select DC- connection, to form a single inductor loop or multiple inductor parallel loops. The loop selects any one or more of L1, L2, L3 and L4 to keep the inductance value stable, and is placed between AC and DC- of the lower bridge second MOS tube Q2 to form a double pulse test circuit for testing the upper bridge first MOS tube Q1, and then the required test is performed.

[0034] In order to achieve the above purpose, the utility model also provides a test fixture which comprises the above-mentioned double pulse test circuit based on power semiconductor.

[0035] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present application, and those skilled in the art can understand that the embodiments of the present application are not limited to the above content, and the obvious changes, replacements or substitutions based on the above content do not exceed the scope of the technical solutions of the present application; other embodiments will certainly fall within the scope of the present application without departing from the concept of the present application.

Claims

1. A power semiconductor-based double-pulse test circuit, characterized in that: it comprises at least two load inductance selection branches, a first position switching branch, a second position switching branch, a first test interface, a second test interface and a third test interface; the load inductance selection branch comprises an inductor and a switching switch, the first end of the switching switch is connected with the second test interface, the second end of the switching switch is connected with the first end of the inductor, and the second end of the inductor is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively; the second end of the first position switching branch is connected with the first test interface, and the second end of the second position switching branch is connected with the third test interface; the first test interface is further used for connecting the positive pole of a direct current power supply, and the third test interface is further used for connecting the negative pole of the direct current power supply. 2.The power semiconductor-based double-pulse test circuit according to claim 1, characterized in that: the power semiconductor comprises an IGBT tube or a MOS tube; when testing the IGBT tube, the emitter and the collector of the first IGBT tube to be tested are connected with the first test interface and the second test interface respectively, and the emitter and the collector of the second IGBT tube to be tested are connected with the second test interface and the third test interface respectively; when testing the MOS tube, the source and the drain of the first MOS tube to be tested are connected with the first test interface and the second test interface respectively, and the drain and the source of the second MOS tube to be tested are connected with the second test interface and the third test interface respectively. 3.The power semiconductor-based double-pulse test circuit according to claim 2, characterized in that: the load inductance selection branch comprises a first load inductance selection branch, a second load inductance selection branch, a third load inductance selection branch and a fourth load inductance selection branch; the first load inductance selection branch comprises a first inductor and a first switching switch, the first end of the first switching switch is connected with the second test interface, the second end of the first switching switch is connected with the first end of the first inductor, and the second end of the first inductor is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively; the second load inductance selection branch comprises a second inductor and a second switching switch, the first end of the second switching switch is connected with the second test interface, the second end of the second switching switch is connected with the first end of the second inductor, and the second end of the second inductor is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively; the third load inductance selection branch comprises a third inductor and a third switching switch, the first end of the third switching switch is connected with the second test interface, the second end of the third switching switch is connected with the first end of the third inductor, and the second end of the third inductor is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively; The fourth load inductor selection branch includes a fourth inductor and a fourth switching switch, a first end of the fourth switching switch is connected with the second test interface, a second end of the fourth switching switch is connected with a first end of the fourth inductor, and a second end of the fourth inductor is connected with the first end of the first position switching branch and the first end of the second position switching branch respectively.

4. The power semiconductor-based double-pulse test circuit of claim 3, wherein: The first inductor, the second inductor, the third inductor and the fourth inductor each include a hollow coil, and no magnetic core or a magnetic core of different sizes is arranged in the hollow coil.

5. The power semiconductor-based double-pulse test circuit of claim 2, wherein: The switching switch includes a relay or an electrically controlled switch, and control ends of the relay or the electrically controlled switch are connected with inductor switching signals respectively for controlling conduction or closure of the switching switch.

6. The power semiconductor-based double-pulse test circuit of claim 2, wherein: The switching switch includes a switching triode. A collector of the switching triode is connected with the second test interface, and an emitter of the switching triode is connected with the first end of the inductor. A base of the switching triode is connected with an inductor switching signal for controlling conduction or cut-off of the switching triode.

7. The power semiconductor-based double-pulse test circuit of claim 2, wherein: The switching switch includes an NMOS tube. A source of the NMOS tube is connected with the second test interface, and a drain of the NMOS tube is connected with the first end of the inductor. A gate of the NMOS tube is connected with an inductor switching signal for controlling conduction or cut-off of the NMOS tube.

8. The power semiconductor based double pulse test circuit of claim 2, wherein: The first position switching branch includes a relay or an electrically controlled switch, and the second position switching branch includes a relay or an electrically controlled switch, and control ends of the relays or the electrically controlled switches are connected with position switching signals respectively for controlling conduction or closure of the first position switching branch or the second position switching branch.

9. A test circuit board, characterized by: The power semiconductor-based double-pulse test circuit includes any one of the power semiconductor-based double-pulse test circuits of claims 1-8.

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