Back contact cell, cell assembly and photovoltaic system

Abstract

The utility model is applicable to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system, in the back contact cell, an insulating dielectric layer is arranged on at least partial region of a first doping layer, and at a preset position of a spacer region, a second doping layer is arranged on the insulating dielectric layer; the insulating dielectric layer is provided with an extension section which extends out of the first region and is at least partially bent towards one side where the silicon substrate is located, and the extension section, the first doping layer and the silicon substrate jointly form a deposition space. And at the first cross section along the first direction, the extension section, the first doping layer and the silicon substrate jointly form a closed pattern. The electric leakage doping part is arranged in the deposition space and forms electric leakage contact with the first doping layer. At the preset position, the second doping layer is provided with a first extension part which extends and covers at least partial area of the extension section, and the first extension part is in conductive contact with the electric leakage doping part. Therefore, the efficiency loss caused by electric leakage contact can be reduced while the hot spot resistance of the back contact battery is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a back contact cell, a cell module and a photovoltaic system. BACKGROUND

[0002] At present, in the solar cell, the back contact cell is a cell in which the emitter and the base contact electrode are both placed on the back (non-front) of the cell, and the front of the cell is not blocked by any metal electrode, thereby effectively improving the efficiency of the back contact cell.

[0003] In the use process of the module side, when the shielding object in the external environment shields the cell piece, the cell piece that is shielded will appear hot spot phenomenon, and at high temperature, it is easy to cause the carbonization of the encapsulation glue film of the module and even cause fire. In the related art back contact cell, two different doped layers are usually electrically connected at a local position to form a leakage point, thereby reducing the reverse breakdown voltage and improving the hot spot resistance of the back contact cell and reducing the hot spot risk. However, although the current back contact cell can improve the hot spot resistance of the back contact cell, it will cause poor working performance and low conversion efficiency of the back contact cell.

[0004] Therefore, how to improve the hot spot resistance of the back contact cell while ensuring the conversion efficiency of the back contact cell has become a technical problem to be solved by technical personnel. Invention content

[0005] The present application provides a back contact cell, a cell module and a photovoltaic system.

[0006] The present application is realized in this way. The back contact cell of the embodiment of the present application comprises:

[0007] A silicon substrate having opposite front and back surfaces, the back surface comprising a plurality of first regions and a plurality of second regions alternately and spaced apart along a first direction, and a spacing region between the first regions and the second regions, the first regions, the second regions and the spacing region extending along a second direction, the second direction intersecting the first direction;

[0008] A first doped layer provided on the first regions;

[0009] An insulating medium layer provided on at least part of the first doped layer, at a predetermined position of the spacing region, the insulating medium layer has an extension section protruding from the first region and at least partially folded towards the side where the silicon substrate is located, and the end of the extension section is at least partially overlapped with the spacing region, so that the extension section and the first doped layer and the silicon substrate together form a deposition space; wherein, at a first cross section along the first direction, the extension section and the first doped layer and the silicon substrate together form a closed pattern;

[0010] a leakage doped portion disposed in the deposition space and forming a leakage contact with the first doped layer, the leakage doped portion being opposite in polarity to the first doped layer; and

[0011] a second doped layer disposed on a partial region of the second region and the spacer region, the second doped layer being opposite in polarity to the first doped layer, at the preset position, the second doped layer having a first extension extending over at least a partial region of the extension segment, the first extension being in electrically conductive contact with the leakage doped portion, and the first extension further extending over at least a partial region of a portion of the insulating medium layer corresponding to the first doped layer.

[0012] In some embodiments, a through hole is formed on the extension segment, and the first extension is in electrically conductive contact with the leakage doped portion through the through hole.

[0013] In some embodiments, at a second cross section along the first direction, an end of the extension segment is suspended over the spacer region, the extension segment and the first doped layer and the silicon substrate jointly form an open non-enclosed pattern, the second doped layer is in electrically conductive contact with the leakage doped portion at the opening, and the first cross section and the second cross section are parallel to each other in the second direction.

[0014] In some embodiments, in the second direction, the extension segment has a first portion with an end portion overlapping the spacer region and a second portion with an end portion suspended over the spacer region, the second portion has a gap with a surface of the spacer region, and the second doped layer is in electrically conductive contact with the leakage doped portion through the gap.

[0015] In some embodiments, the gap between the second portion and the surface of the spacer region is 5nm-800nm.

[0016] In some embodiments, at a third cross section along the first direction, the leakage doped portion has a cavity therein.

[0017] In some embodiments, an outer diameter of the cavity is 10nm-500nm.

[0018] In some embodiments, an included angle between a surface of the first doped layer forming a leakage contact with the leakage doped portion and a surface of the first region is an acute angle, and the surface of the first doped layer forming a leakage contact with the leakage doped portion has a first recessed region.

[0019] In some embodiments, the surface of the first doped layer forming a leakage contact with the leakage doped portion is a curved surface.

[0020] In some embodiments, the first doped layer has a second extension part extending along the first direction and overhanging the spacer region, the insulating dielectric layer covers a surface of the second extension part facing away from the silicon substrate, the extension segment and the second extension part together with the silicon substrate form the deposition space, and the electrically conductive doped part forms an electrically conductive contact with the second extension part.

[0021] In some embodiments, the electrically conductive doped part forms an electrically conductive contact with a surface of the second extension part facing the spacer region; and / or

[0022] The electrically conductive doped part forms an electrically conductive contact with an end surface of the second extension part in the first direction.

[0023] In some embodiments, the electrically conductive doped part forms an electrically conductive contact with an end surface of the second extension part in the first direction, an included angle between the end surface of the second extension part and a surface of the first region is an acute angle, and the end surface of the second extension part has a second recessed region.

[0024] In some embodiments, an extension length of the second extension part in the first direction is 0.1 μm-3 μm.

[0025] In some embodiments, a first dielectric layer is provided on a surface of the first doped layer forming an electrically conductive contact with the electrically conductive doped part, and the electrically conductive doped part forms an electrically conductive contact with the first doped layer through the first dielectric layer.

[0026] In some embodiments, a second dielectric layer is provided on the spacer region at least at the preset position, an end portion of the extension segment is at least partially overlapped on the second dielectric layer, and the electrically conductive doped part is also provided on the second dielectric layer.

[0027] In some embodiments, at a fourth cross section along the first direction, the extension segment has an overlapping part overlapped on the spacer region, and the second doped layer and the electrically conductive doped part are separated by the extension segment.

[0028] In some embodiments, a length of a portion of the silicon substrate corresponding to the overlapping part in the first direction is less than 150 nm.

[0029] In some embodiments, at the fourth cross section, the overlapping part is a discontinuous structure, so that the overlapping part at the fourth cross section includes a first portion close to the electrically conductive doped part and a second portion spaced from the first portion;

[0030] The second doped layer is conductive with the silicon substrate at a gap between the first portion and the second portion.

[0031] In some embodiments, the length of the portion of the silicon substrate corresponding to the first portion in the first direction is less than 150 nm.

[0032] In some embodiments, in the first direction, the silicon substrate has a silicon wafer extension extending over the spacer, the silicon wafer extension also being provided with the first doped layer, a cross-sectional profile of the silicon wafer extension is triangular, and an included angle between a surface of the silicon wafer extension and a surface of the first region is an acute angle.

[0033] In some embodiments, the length of the silicon wafer extension in the first direction is 0.1-3 μm.

[0034] The present application also provides a battery assembly comprising the back contact battery as described in any one of the above.

[0035] The present application also provides a photovoltaic system comprising the battery assembly as described above.

[0036] In the back contact battery, the battery assembly and the photovoltaic system of the embodiments of the present application, the first doped layer is arranged on the first region, the second doped layer is arranged on the second region and part of the spacer region. The insulating medium layer is arranged on at least part of the first doped layer, at a preset position of the spacer region, the insulating medium layer has an extension section extending out of the first region and at least partially bending towards a side where the silicon substrate is located, an end of the extension section is at least partially overlapped and arranged on the spacer region, so that the extension section, the first doped layer and the silicon substrate together form a deposition space. At a first cross section in the first direction, the extension section, the first doped layer and the silicon substrate together form a closed pattern. The leakage doped part is arranged in the deposition space enclosed by the extension section, the first doped layer and the silicon substrate and forms a leakage contact with the first doped layer. At the preset position, the second doped layer has a first extension part extending over at least part of the extension section, the first extension part is in conductive contact with the leakage doped part, and the first extension part further extends over at least part of the portion of the insulating medium layer corresponding to the first doped layer. In this way, by arranging the leakage doped part in the deposition space enclosed by the extension section of the insulating medium layer, the first doped layer and the silicon substrate, and at the first cross section in the first direction, the extension section, the first doped layer and the silicon substrate together form a closed pattern, the efficiency loss of the back contact battery due to the leakage contact can be effectively reduced, and at the same time, the passivation effect at the leakage contact position can be improved by the extension section of the insulating medium layer, and the efficiency of the back contact battery is optimized.

[0037] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a schematic diagram of a module of a photovoltaic system provided by an embodiment of the present application;

[0039] Figure 2 is a schematic diagram of a module of a battery assembly provided by an embodiment of the present application;

[0040] Figure 3 is a schematic diagram of a planar structure of a back contact cell provided by an embodiment of the present application;

[0041] Figure 4 is a schematic diagram of a cross section of the back contact cell in Figure 3 along line L1-L1;

[0042] Figure 5 is a schematic diagram of a cross section of the back contact cell in Figure 3 along line L2-L2;

[0043] Figure 6 is a schematic diagram of a cross section of the back contact cell in Figure 3 along line L3-L3;

[0044] Figure 7 is a schematic diagram of a structure of a back contact cell at different cross sections provided by an embodiment of the present application;

[0045] Figure 8 is another schematic diagram of a cross section of a back contact cell provided by an embodiment of the present application;

[0046] Figure 9 is still another schematic diagram of a cross section of a back contact cell provided by an embodiment of the present application;

[0047] Figure 10 is a test diagram of a back contact cell at a preset position provided by an embodiment of the present application;

[0048] Figure 11 is another test diagram of a back contact cell at a preset position provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application, and cannot be used to limit the present application.

[0050] In the description of the application, it should be understood that the terms "length", "width", "upper", "lower", "top", "bottom", "lateral", "longitudinal", and the like are directions or positional relationships based on the orientations or positions shown in the drawings, and are merely used for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0051] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0052] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0053] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "above", "over" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "below", "under" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0054] The disclosure that follows provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplicity, the elements of the specific examples below are described in terms of particular components and arrangements. Of course, they are merely examples and are not intended to limit the present application. Further, the application can be implemented in different examples with different components and / or different arrangements. The repeated use of reference characters in the description and drawings is intended to represent the presence of a similar or analogous feature in all examples of the application in which it is used. Further, the application provides examples of various specific processes and materials. One skilled in the art will recognize that other processes and / or materials can be used.

[0055] Referring now to the drawings Figures 1-2 The photovoltaic system 1000 in the embodiments of the present application can include the cell assembly 200 in the embodiments of the present application, and the cell assembly 200 in the embodiments of the present application can include a plurality of the back contact cell 100 in the embodiments of the present application.

[0056] In the embodiments of the present application, the plurality of back contact cells 100 in the cell assembly 200 can be sequentially connected in series to form a plurality of cell strings, and each cell string can be connected in series, in parallel, or in a combination of series and parallel to realize the current output, for example, the connection between each cell can be realized by welding the ribbon, and the connection between each cell string can be realized by the bus bar. In some embodiments, each cell string can form a cell array, and then be packaged together by the front plate, the front adhesive film, the rear adhesive film, and the back plate to form the cell assembly 200.

[0057] Referring now to the drawings Figure 3 and Figure 4 The back contact cell 100 in the embodiments of the present application can include a silicon substrate 10, a first doped layer 20, an insulating dielectric layer 30, a leakage doped portion 40, and a second doped layer 50.

[0058] The silicon substrate 10 can have opposite front surface 11 and back surface 12, and the back surface 12 includes a plurality of first regions 121 and a plurality of second regions 122, as shown in Figure 3 The plurality of first regions 121 and the plurality of second regions 122 are alternately and spacedly arranged along a first direction, and the back surface 12 further includes a plurality of spacing regions 123 between the first regions 121 and the second regions 122, that is, the adjacent first regions 121 and the second regions 122 are separated by the spacing regions 123. The first regions 121, the second regions 122, and the spacing regions 123 all extend along a second direction, and the second direction intersects the first direction.

[0059] Specifically, as shown in Figure 3As shown, the first direction may be the lateral direction of the back-contact cell 100, and the second direction may be the longitudinal direction of the back-contact cell 100, with the two directions being perpendicular to each other. That is, the first regions 121 and the second regions 122 may be alternately arranged along the lateral direction of the silicon substrate 10 and extend along the longitudinal direction, and the spacer regions 123 also extend along the longitudinal direction. Of course, it is understood that in other embodiments, the first direction and the second direction may also be other directions, for example, they may be the directions of the two diagonals of the back-contact cell 100, respectively. This is not a limitation and may be selected based on the actual manufacturing process.

[0060] As a case, Figure 4 As shown, in the direction from the front surface 11 to the back surface 12, the surface of the first region 121 may be higher than the surface of the spacer region 123 and the surface of the second region 122. That is, in the thickness direction of the silicon substrate 10, the spacer region 123 and the second region 122 are closer to the front surface 11 of the silicon substrate 10 than the first region 121.

[0061] The first doping layer 20 is disposed on the first region 121 , the insulating dielectric layer 30 is disposed on at least a portion of the first doping layer 20 , and at a predetermined position 1231 (eg, Figure 3 As shown in FIG, the insulating dielectric layer 30 has an extension section 31 extending out of the first region 121 and at least partially bent toward the side where the silicon substrate 10 is located. The end of the extension section 31 is at least partially overlapped and arranged on the spacer region 123, so that the extension section 31, the first doped layer 20 and the silicon substrate 10 form a deposition space 301 together.

[0062] like Figure 4 As shown, at the first cross section along the first direction ( Figure 4 This is the cross-sectional diagram at the first section. Figure 3 In the cross section formed along line L1-L1 in the middle, the extension section 31, the first doped layer 20, and the silicon substrate 10 together form a closed pattern 302. That is, along the first direction, the extension section 31 has multiple cross sections, and the multiple cross sections are arranged in parallel along the second direction. At one of the cross sections of the extension section 31, the extension section 31, the first doped layer 20, and the silicon substrate 10 together form a closed pattern 302. It should be noted that, in this document, the cross section along the first direction refers to a cross section of the back-contact cell 100 taken along the first direction.

[0063] The leakage-doped portion 40 is arranged in the deposition space 301 and forms a leakage contact with the first doped layer 20, and the leakage-doped portion 40 is opposite in polarity to the first doped layer 20. The second doped layer 50 is arranged on part of the second region 122 and the spacer region 123, and the second doped layer 50 is opposite in polarity to the first doped layer 20. At the preset position 1231, the second doped layer 50 has a first extension 51 extending over at least part of the extension section 31, the first extension 51 is in conductive contact with the leakage-doped portion 40, and the first extension 51 also extends over at least part of the portion of the insulating dielectric layer 30 corresponding to the first doped layer 20. That is, at the preset position 1231 of the spacer region 123, the first doped layer 20 and the second doped layer 50 form a leakage contact through the leakage-doped portion 40.

[0064] It should be noted that, in this article, a certain film layer is arranged on a certain surface region or part of the region, the entire region, which can be directly stacked on the surface region or a certain film layer, or other film layers can be arranged between the film layer and the surface or film layer. Covering only indicates the specific arrangement range of the film layer. For example, in some embodiments, the first doped layer 20 and the surface of the first region 121 can have a dielectric layer, the second doped layer 50 and the surface of the second region 122 can also have a dielectric layer, and the leakage-doped portion 40 and the silicon substrate 10 can also have a dielectric layer, which is not limited here.

[0065] In addition, it should be noted that, in this article, "leakage contact" refers to the absence of insulation between the leakage-doped portion 40 and the first doped layer 20, and the leakage conduction forms a leakage point. The two can be directly in contact to form a leakage point, or other dielectric layers can be used to achieve tunneling to achieve the function of leakage contact, which is not limited here.

[0066] In the back contact cell 100, the cell assembly 200 and the photovoltaic system 1000 in the embodiments of the present application, the first doped layer 20 is arranged on the first region 121, and the second doped layer 50 is arranged on part of the second region 122 and the spacer region 123. The insulating medium layer 30 is arranged on at least part of the first doped layer 20. At the preset position 1231 of the spacer region 123, the insulating medium layer 30 has an extension segment 31 which protrudes from the first region 121 and is at least partially bent towards the side where the silicon substrate 10 is located. The end of the extension segment 31 is at least partially overlapped with the spacer region 123, so that the extension segment 31, together with the first doped layer 20 and the silicon substrate 10, forms a deposition space 301. At the first cross section in the first direction, the extension segment 31, together with the first doped layer 20 and the silicon substrate 10, forms a closed pattern 302. The leakage doped part 40 is arranged in the deposition space 301 formed by the extension segment 31, the first doped layer 20 and the silicon substrate 10, and forms a leakage contact with the first doped layer 20. At the preset position 1231, the second doped layer 50 has a first extension part 51 which extends over at least part of the extension segment 31, and the first extension part 51 is in conductive contact with the leakage doped part 40. The first extension part 51 further extends over at least part of the portion of the insulating medium layer 30 corresponding to the first doped layer 20. In this way, the leakage doped part 40 is in leakage contact with the first doped layer 20 and in conductive contact with the first extension part 51 of the second doped layer 50, which can form a leakage point at the preset position 1231 of the spacer region 123, thereby improving the anti-hot spot performance of the back contact cell 100. By arranging the leakage doped part 40 in the deposition space 301 formed by the extension segment 31 of the insulating medium layer 30, the first doped layer 20 and the silicon substrate 10, and by forming a closed pattern 302 at the first cross section in the first direction, the efficiency loss caused by the leakage contact can be effectively reduced, and the passivation effect at the leakage contact position can be improved by the extension segment 31 of the insulating medium layer 30, thereby optimizing the efficiency of the back contact cell 100. In addition, as a possible case, by the closed design of the extension segment 31 at part of the cross section, the doping concentration of the leakage doped part 40 can be lower than that of the second doped layer 50 during the deposition process of forming the leakage doped part 40, thereby reducing the efficiency loss after forming the leakage contact and improving the efficiency of the back contact cell 100.

[0067] That is to say, in the present application, by designing the extension segment 31 of the insulating medium layer 30 to form a deposition space 301 with the first doped layer 20 and the silicon substrate 10, and by forming a closed pattern 302 at the first cross section, and by designing the leakage doped part 40, the anti-hot spot performance of the back contact cell 100 can be improved while reducing the efficiency loss caused by the leakage contact, thereby ensuring the efficiency of the back contact cell 100.

[0068] Specifically, in the embodiments of the present application, in the present application, the silicon substrate 10 can be a P-type silicon substrate 10 or an N-type silicon substrate 10, which can preferably be an N-type silicon substrate 10, and the specific limitation is not made here.

[0069] The first doped layer 20 is a P-type doped layer, and the second doped layer 50 is an N-type doped layer, or the first doped layer 20 can be an N-type doped layer, and the second doped layer 50 can be a P-type doped layer, and the specific limitation is not made here, as long as the polarities of the two are opposite. The leakage doped portion 40 is opposite to the doping type of the first doped layer 20 and the same as the doping type of the second doped layer 50.

[0070] It should be noted that in the embodiments of the present application, the "preset position 1231" can be understood as the entire interval region 123 or part of the position of the interval region 123, and the specific limitation is not made here. As shown in Figure 3 In some embodiments, the preset position 1231 is preferably part of the interval region 123, and in such a case, the number of preset positions 1231 in each interval region 123 can be single or multiple, as shown in Figure 3 In a single interval region 123, multiple preset positions 1231 can be arranged at intervals along the second direction, and the specific limitation is not made here.

[0071] In addition, in the embodiments of the present application, the number of interval regions 123 with preset positions 1231 can be single or multiple, and the specific limitation is not made here. Further, in some embodiments, the number of preset positions 1231 can be multiple, which can be uniformly distributed on the back surface 12 of the back contact cell 100.

[0072] The insulating medium layer 30 can be a medium layer with insulating function, for example, in some embodiments, the insulating medium layer 30 can be a borosilicate glass layer, a phosphosilicate glass layer or a borophosphosilicate glass layer. For another example, in some embodiments, the insulating medium layer 30 has a silicon oxide layer, a silicon nitride layer and the like with insulating function. In addition, in some embodiments, the insulating medium layer 30 can be a single-layer structure or a multi-layer structure, and the specific limitation is not made here.

[0073] In addition, in the embodiments of the present application, the back contact cell 100 can further include a first electrode (not shown) and a second electrode (not shown), and a back passivation film layer (not shown) can be further provided on the back surface 12 of the silicon substrate 10, the back passivation film layer can cover the entire back surface 12, and the first electrode can be located at the first region 121 and form an ohmic contact with the first doped layer 20 through the back passivation film layer and be insulated and separated from the second doped layer 50. For example, the first electrode can be located at a position where the first doped layer 20 is not covered by the first extension 51, and the second electrode can be located at the second region 122 and form an ohmic contact with the second doped layer 50 through the back passivation film layer.

[0074] Referring to Figure 4 In some embodiments, a first dielectric layer 60 is provided on the surface of the first doped layer 20 forming a leakage contact with the leakage doped portion 40, and the leakage doped portion 40 forms a leakage contact with the first doped layer 20 through the first dielectric layer 60.

[0075] In this way, by providing the first dielectric layer 60, the passivation effect at the leakage contact point can be improved, and the efficiency loss can be reduced.

[0076] Specifically, the first dielectric layer 60 can be a film layer having passivation and conductive functions, such as a tunneling oxide layer (for example, a tunneling silicon oxide film layer) and an intrinsic amorphous silicon layer, and the like, which is not specifically limited here.

[0077] Referring to Figure 4 On the spacing region 123, at least at the predetermined position 1231, a second dielectric layer 70 is provided, and the end portion of the extension segment 31 is at least partially overlapped on the second dielectric layer 70, and the leakage doped portion 40 is also provided on the second dielectric layer 70.

[0078] In this way, by providing the second dielectric layer 70, the passivation effect of the spacing region 123 can be improved, thereby improving the efficiency.

[0079] Specifically, the second dielectric layer 70 can be, for example, a tunneling oxide layer (for example, a tunneling silicon oxide film layer) and an intrinsic amorphous silicon layer, and the like.

[0080] In addition, in some embodiments, a third dielectric layer (not shown) is provided between the first doped layer 20 and the silicon substrate 10, and a fourth dielectric layer 80 is provided between the second doped layer 50 and the silicon substrate 10.

[0081] In this way, the passivation effect of the first region 121 and the second region 122 can be improved, thereby improving the efficiency.

[0082] Specifically, the third dielectric layer and the fourth dielectric layer 80 can be, for example, a tunneling oxide layer (for example, a tunneling silicon oxide film layer) and an intrinsic amorphous silicon layer, and the like.

[0083] In some embodiments, the extension section 31 of the insulating medium layer 30 can be formed with a through hole (not shown in the figure), and the first extension part 51 can be in conductive contact with the leakage-doped portion 40 through the through hole.

[0084] In this way, by forming a plurality of through holes on the extension section 31, the leakage-doped portion 40 can be formed by deposition in the deposition space 301, and the first extension part 51 can be in conductive contact with the leakage-doped portion 40 through the through holes. At other continuous positions, the first extension part 51 is isolated from the leakage-doped portion 40 by the extension section 31, which can avoid excessive efficiency loss caused by the full contact between the first extension part 51 and the leakage-doped portion 40, and can also improve the passivation effect.

[0085] Specifically, in such embodiments, the through holes on the extension section 31 can be single or multiple, which is not limited in particular.

[0086] Please refer to Figure 5 In some embodiments, at the second cross section along the first direction (S2-S2), Figure 5 That is, a cross-sectional view of the second cross section, the second cross section is a cross section formed along the line L2-L2 in Figure 3 The end of the extension section 31 is suspended on the spacing region 123, and the extension section 31, the first doped layer 20 and the silicon substrate 10 together form an open pattern 303 with an opening 304, and the second doped layer 50 is in conductive contact with the leakage-doped portion 40 at the opening 304. The first cross section and the second cross section are parallel to each other in the second direction.

[0087] In this way, at the first cross section, the extension section 31, the first doped layer 20 and the silicon substrate 10 form a closed pattern 302, and at the second cross section, the extension section 31, the first doped layer 20 and the silicon substrate 10 together form an open pattern 303 with an opening, which can enable the leakage-doped portion 40 to be in conductive contact with the second doped layer 50 at the opening of the open pattern 303, so that the first doped layer 20 and the second doped layer 50 can form a leakage contact. By such design of the extension section 31, the efficiency loss caused by the leakage contact can be reduced.

[0088] Please refer to Figure 4 and Figure 5 In some embodiments, in the second direction, the extension section 31 has a first part 311 with an end portion overlapping the spacing region 123 and a second part 312 with an end portion suspended on the spacing region 123, and the second part 312 has a gap 305 with the surface of the spacing region 123, and the second doped layer 50 is in conductive contact with the leakage-doped portion 40 through the gap.

[0089] Thus, at the cross section of the first portion 311, the first portion 311 forms a closed pattern 302 with the first doped layer 20 and the silicon substrate 10, and the first portion 311 isolates the leakage doped portion 40 and the second doped layer 50; at the cross section of the second portion 312, the second portion 312 forms an open pattern 303 with the first doped layer 20 and the silicon substrate 10, and the second doped layer 50 forms a conductive contact with the leakage doped portion 40 through the gap at the open pattern 303. In this way, the area of the conductive contact between the second doped layer 50 and the leakage doped portion 40 can be controlled, and the efficiency loss caused by the conductive contact can be reduced.

[0090] Further, in some embodiments, the gap 305 between the second portion 312 and the surface of the spacing region 123 is 5 nm to 800 nm, i.e., the size of the gap between the end of the second portion 312 and the silicon substrate 10 in the thickness direction of the silicon substrate 10 is 5 nm to 800 nm.

[0091] In this way, the area of the conductive contact between the leakage doped portion 40 and the second doped layer 50 can be controlled within a reasonable range, and the efficiency loss caused by the conductive contact can be reduced.

[0092] Specifically, the size of the gap between the end of the second portion 312 and the silicon substrate 10 can be, for example, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, or any value between 5 nm and 800 nm.

[0093] Please refer to Figure 6 In some embodiments, at the third cross section along the first direction (e.g., the cross section formed along the line L3-L3 in FIG. 3B), the leakage doped portion 40 has a cavity 41, and the third cross section is parallel to the second cross section in the second direction. Figure 6 That is, the third cross section is a cross-sectional view of the second cross section, and the third cross section is parallel to the second cross section in the second direction. Figure 3 In this way, the cavity 41 can effectively release the local stress generated during the fabrication of the leakage doped portion 40, effectively reduce the inward expansion of the leakage doped portion 40 through the second dielectric layer 70 to the silicon substrate 10 during high-temperature doping, reduce the interface defects between the silicon substrate 10 and the second dielectric layer 70, reduce the surface recombination rate, and improve the collection probability of photo-generated carriers.

[0094] In this way, the area of the conductive contact between the second doped layer 50 and the leakage doped portion 40 can be controlled within a reasonable range, and the efficiency loss caused by the conductive contact can be reduced.

[0092] Specifically, the size of the gap between the end of the second portion 312 and the silicon substrate 10 can be, for example, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, or any value between 5 nm and 800 nm.

[0093] Please refer to Figure 6 In some embodiments, at the third cross section along the first direction (e.g., the cross section formed along the line L3-L3 in FIG. 3B), the leakage doped portion 40 has a cavity 41, and the third cross section is parallel to the second cross section in the second direction. Figure 6 That is, the third cross section is a cross-sectional view of the second cross section, and the third cross section is parallel to the second cross section in the second direction. Figure 3 In this way, the cavity 41 can effectively release the local stress generated during the fabrication of the leakage doped portion 40, effectively reduce the inward expansion of the leakage doped portion 40 through the second dielectric layer 70 to the silicon substrate 10 during high-temperature doping, reduce the interface defects between the silicon substrate 10 and the second dielectric layer 70, reduce the surface recombination rate, and improve the collection probability of photo-generated carriers.

[0094]

[0095] Specifically, in such an embodiment, the third cross section may be the same cross section as the first cross section, and the third cross section may also be the same cross section as the second cross section. Of course, in some embodiments, the third cross section may also be a cross section different from both the first cross section and the second cross section. In such a case, the first cross section, the second cross section, and the third cross section are parallel to each other in the second direction.

[0096] In some embodiments, the outer diameter of the cavity 41 is 10 nm-500 nm.

[0097] In this way, it is possible to ensure that the cavity 41 can release the local stress of the leakage doping portion 50 while not affecting the contact area of ​​the leakage doping portion 40 forming a leakage contact with the first doping layer 20 through the first dielectric layer 60 .

[0098] Specifically, in such an embodiment, the outer diameter of the cavity 41 may be, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm or any value between 10 nm and 500 nm.

[0099] In summary, if Figure 7 As shown, Figure 7 Shows the cross-sectional structure at different cross sections. Figure 7 It can be seen that in this application, at different cross sections, the extension section 31, the first doped layer 20 and the silicon substrate 10 form different figures. At some cross sections, the three form a closed figure, and at some cross sections, the three form a non-closed figure.

[0100] See also Figure 4 In some embodiments, the angle between the surface where the first doping layer 20 forms a leakage contact with the leakage doping portion 40 and the surface of the first region 121 is an acute angle, and the surface where the first doping layer 20 forms a leakage contact with the leakage doping portion 40 has a first recessed region 201.

[0101] In this way, by setting the angle between the leakage contact surface of the first doping layer 20 and the surface of the first region 121 to an acute angle and forming a first recessed region 201 on the leakage contact surface, the leakage doping portion 40 can be deposited more easily to form a leakage contact with the first doping layer 20 more easily.

[0102] Furthermore, in such an embodiment, the surface of the first doped layer 20 forming the leakage contact with the leakage doped portion 40 is a curved surface, thereby increasing the leakage contact area between the first doped layer 20 and the leakage doped portion 40 and improving the anti-hot spot performance.

[0103] See also Figure 8 In some embodiments, the first doped layer 20 has a second extension portion 21 extending along the first direction and suspended on the spacer region 123, the insulating dielectric layer 30 covers the surface of the second extension portion 21 facing away from the silicon substrate 10, a deposition space 301 is formed between the extension section 31, the second extension portion 21 and the silicon substrate 10, and the leakage doping portion 40 forms a leakage contact with the second extension portion 21.

[0104] Thus, the second extension portion 21 can increase the leakage contact area between the first doped layer 20 and the leakage doped portion 40 to avoid the contact area between the first doped layer 20 and the leakage doped portion 40 being too small to achieve the desired anti-hot spot effect.

[0105] At the same time, by setting the second extension portion 21, a deposition area is provided between the second extension portion 21 and the silicon substrate 10. In the subsequent deposition process of the back passivation film layer, the setting of such a deposition area can suppress the sufficient exchange of plasma components in the region with plasma components outside the region, thereby achieving a localized distribution of the mobile hydrogen content of the back passivation film layer on the back side 12, so that the mobile hydrogen content of the back passivation film layer 50 on the back side 12 in the deposition area is lower, and the mobile hydrogen content of the back passivation film layer 50 on the back side 12 in the remaining areas is higher, so as to achieve the best passivation and anti-attenuation effect. In addition, the direct bombardment of the plasma on the silicon substrate 10 can be reduced, reducing bombardment damage.

[0106] In some embodiments, the leakage doping portion 40 may be aligned with the surface of the second extension portion 21 facing the spacer 123 (ie, Figure 8 The leakage doping portion 40 forms a leakage contact with the lower surface of the second extension portion 21 shown in FIG. 3 and / or the leakage doping portion 40 forms a leakage contact with the end surface of the second extension portion 21 in the first direction (i.e., the side surface of the second extension portion 21 located at the end and connecting the upper and lower surfaces of the second extension portion 21).

[0107] With such a design, a stable leakage contact can be formed between the leakage doping portion 40 and the first doping layer 20 .

[0108] In some embodiments, the extension length of the second extension portion 21 in the first direction may be 0.1 μm-3 μm.

[0109] Thus, setting the length of the second extension portion 21 within the above range can ensure efficiency while enhancing the anti-hot spot performance of the back contact cell 100 , that is, the efficiency and anti-hot spot performance of the back contact cell 100 can be balanced.

[0110] Specifically, the second extension 21 can have an extension length in the first direction of, for example, 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, or any value between 0.1 μm and 3 μm.

[0111] Referring to Figure 8 , the leakage-doped portion 40 forms a leakage contact with the end surface of the second extension 21 in the first direction, the angle between the end surface of the second extension 21 and the surface of the first region 121 is an acute angle, and the end surface of the second extension 21 has a second recessed region 211.

[0112] In this way, by setting the angle between the end surface of the second extension 21 and the surface of the first region 121 to be an acute angle and forming the second recessed region 211 on the end surface, the leakage-doped portion 40 can be more easily deposited to more easily form a leakage contact with the second extension 21.

[0113] Referring to Figure 9 , in some embodiments, at a fourth cross section in the first direction (the fourth cross section can be the same as or different from the first cross section and the third cross section, which is not particularly limited here), the extension segment 31 has an overlap portion 313 that overlaps the spacing region 123, and the second doped layer 50 and the leakage-doped portion 40 are separated by the extension segment 31, specifically, at the fourth cross section, the extension segment 31 forms a closed pattern with the first doped layer 20 and the silicon substrate 10.

[0114] As shown in Figure 9 , in some embodiments, the length of the portion of the silicon substrate 10 that is covered by the overlap portion 313 in the first direction is less than 150 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or 150 nm.

[0115] In this way, even if the extension segment 31 forms a closed pattern with the first doped layer 20 and the silicon substrate 10 at all cross sections, by setting the length of the portion of the substrate that is covered by the overlap portion 313 to be within this relatively narrow range of less than 150 nm, the second doped layer 50 can be equivalent to being directly conductive with the leakage-doped portion 40, so that the first doped layer 20, the leakage contact portion 40, and the second doped layer 50 form a leakage path, to achieve the effect of improving the hot spot resistance.

[0116] Of course, referring to Figure 10 and Figure 11In some embodiments, at the fourth cross section, the overlap portion 313 can be a discontinuous structure, such that the overlap portion 313 includes a first portion 3131 close to the leakage-doped portion 40 and a second portion 3132 spaced from the first portion 3131 at the fourth cross section;

[0117] The second doped layer 50 is in conduction with the silicon substrate 10 at a gap 3133 between the first portion 3131 and the second portion 3132.

[0118] In such embodiments, the length of the portion of the silicon substrate 10 covered by the first portion 3131 in the first direction is less than 150 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm.

[0119] In this way, by setting the overlap portion 313 to be a discontinuous structure, only the length of the portion of the substrate covered by the first portion 3131 in the first direction needs to be controlled to be less than 150 nm to make the second doped layer 50 equivalent to being in direct conduction with the leakage-doped portion 40, so that the first doped layer 20, the leakage contact portion 40, and the second doped layer 50 form a leakage conduction path, which can reduce the control requirement for the overall length of the entire overlap portion 313 and reduce the difficulty of the manufacturing process.

[0120] It is not difficult to understand that the difference between the present embodiment and the above-mentioned embodiments is that, in the present embodiment, the second doped layer 50 is made to be in direct conduction with the leakage-doped layer 40 through the silicon substrate 10 by setting the overlap portion 313 to be an intermittent first portion 3131 and a second portion 3132 at the fourth cross section, and by controlling the length of the portion of the silicon substrate 10 covered by the first portion 3131 in the first direction. In the previous embodiment, the second doped layer 50 is made to be in direct conduction with the leakage-doped layer 40 through the silicon substrate 10 by directly controlling the overall length of the overlap portion 313 at the fourth cross section.

[0121] Specifically, in both of the above-mentioned embodiments, although the second doped layer 50 is not in direct contact with the leakage contact portion 40 at the fourth cross section, by controlling the length of the portion of the silicon substrate 10 covered by the overlap portion 313 or the first portion 3131 in the first direction to be within a very small range of less than 150 nm, the second doped layer 50 is equivalent to being in direct conduction with the leakage-doped layer 40, so that the two can also be directly in leakage conduction.

[0122] Please refer to Figure 8 , Figure 10 and Figure 11In the first direction, the silicon substrate 10 has a silicon piece extension 13 extending over the spacing region 123, and the silicon piece extension 13 is also provided with the first doped layer 20 (i.e. the upper surface of the silicon piece extension 13 shown in the figure is provided with the first doped layer 20, for example the second extension 21 described above). The cross-sectional profile of the silicon piece extension 13 is triangular, and the included angle between the surface of the silicon piece extension 13 towards the spacing region 123 and the surface of the first region 121 (i.e. the lower surface of the silicon piece extension 13 shown in the figure) is an acute angle.

[0123] In this way, the side surface of the spacing region 123 of the silicon substrate 10 can be provided with a recessed structure by controlling the etching process, and the deposition process of the leakage doped portion 40 can have the effect of gas source flow restriction, the diffusion of the gas source at this position is limited, which can effectively reduce the doping concentration of the silicon base contact surface of the leakage doped portion 40, reduce the interface recombination rate, improve the carrier collection probability, and is also conducive to the formation of the cavity 41, which can effectively eliminate local stress.

[0124] In some embodiments, the extension length of the silicon piece extension 13 in the first direction can be 0.1 μm-3 μm.

[0125] In this way, by controlling the extension length of the silicon piece extension 13 within this reasonable range, the interface recombination rate can be further optimized to achieve a better carrier collection efficiency.

[0126] Specifically, the extension length of the silicon piece extension 13 in the first direction can be, for example, 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, or any value between 0.1 μm-3 μm.

[0127] In the description of the present specification, the description of the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0128] In addition, the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A back contact cell, characterized in that, The application relates to a silicon substrate, which comprises: a silicon substrate having opposite front and back surfaces, the back surface comprising a plurality of first regions and a plurality of second regions alternately and spacedly arranged along a first direction, and a spacing region between the first regions and the second regions, the first regions, the second regions and the spacing region all extending along a second direction intersecting the first direction; a first doped layer arranged on the first regions; an insulating medium layer arranged on at least part of the first doped layer, the insulating medium layer having an extension section extending out of the first regions and at least partially bent towards a side where the silicon substrate is located at a preset position of the spacing region, an end of the extension section at least partially overlapping the spacing region so that the extension section, together with the first doped layer and the silicon substrate, forms a deposition space; wherein, at a first cross section along the first direction, the extension section, together with the first doped layer and the silicon substrate, forms a closed pattern; a leakage current doped part arranged in the deposition space and forming a leakage current contact with the first doped layer, the leakage current doped part being opposite in polarity to the first doped layer; and a second doped layer arranged on part of the second regions and the spacing region, the second doped layer being opposite in polarity to the first doped layer, the second doped layer having a first extension section extending and covering at least part of the extension section at the preset position, the first extension section being in conductive contact with the leakage current doped part, and the first extension section further extending and covering at least part of a portion of the insulating medium layer corresponding to the first doped layer. The extension section has a through hole, and the first extension section is in conductive contact with the leakage current doped part through the through hole. At a second cross section along the first direction, the end of the extension section is suspended on the spacing region, the extension section, together with the first doped layer and the silicon substrate, forms an open non-closed pattern, the second doped layer is in conductive contact with the leakage current doped part at the opening, and the first cross section and the second cross section are parallel to each other in the second direction. In the second direction, the extension section has a first part with the end overlapping the spacing region and a second part with the end suspended on the spacing region, the second part has a gap with the surface of the spacing region, and the second doped layer is in conductive contact with the leakage current doped part through the gap. The gap between the second part and the surface of the spacing region is 5-800 nm. At a third cross section along the first direction, the leakage current doped part has a cavity.

2. The back contact cell of claim 1, wherein, The outer diameter of the cavity is 10-500 nm.

3. The back contact cell of claim 1, wherein, The surface of the leakage current doped part forming the leakage current contact with the first doped layer forms an acute angle with the surface of the first region, and the surface of the leakage current doped part forming the leakage current contact with the first doped layer has a first recessed region.

4. The back contact cell of claim 1, wherein, The surface of the leakage current doped part forming the leakage current contact with the first doped layer is a curved surface.

5. The back contact cell of claim 4, wherein, ​ 6. The back contact cell of claim 1, wherein, ​ 7. The back contact cell of claim 6, wherein, ​ 8. The back contact cell of claim 1, wherein, ​ 9. The back contact cell of claim 8, wherein, ​ 10. The back contact cell of claim 1, wherein, The first doped layer has a second extension part extending along the first direction and overhanging the spacer region, the insulating medium layer covers a surface of the second extension part away from the silicon substrate, the extension segment and the second extension part and the silicon substrate together form the deposition space, and the electrically conductive doped part forms an electrically conductive contact with the second extension part.

11. The back contact cell of claim 10, wherein, The electrically conductive doped part forms an electrically conductive contact with a surface of the second extension part facing the spacer region; and / or The electrically conductive doped part forms an electrically conductive contact with an end surface of the second extension part in the first direction.

12. The back contact cell of claim 11, wherein, The electrically conductive doped part forms an electrically conductive contact with an end surface of the second extension part in the first direction, an included angle between the end surface of the second extension part and a surface of the first region is an acute angle, and the end surface of the second extension part has a second recessed region.

13. The back contact cell of claim 10, wherein, The second extension part has an extension length in the first direction of 0.1 μm-3 μm.

14. The back contact cell of claim 1 wherein, The first doped layer has a first dielectric layer on a surface forming an electrically conductive contact with the electrically conductive doped part, and the electrically conductive doped part forms an electrically conductive contact with the first doped layer through the first dielectric layer.

15. The back contact cell of claim 1, wherein, The spacer region has a second dielectric layer at least at the preset position, and an end part of the extension segment is at least partially overlapped on the second dielectric layer, and the electrically conductive doped part is also on the second dielectric layer.

16. The back contact cell of claim 1, wherein, The extension segment has an overlapping part overlapped on the spacer region at a fourth cross section along the first direction, and the second doped layer and the electrically conductive doped part are separated by the extension segment.

17. The back contact cell of claim 16, wherein, A length of a part of the silicon substrate corresponding to the overlapping part in the first direction is less than 150 nm.

18. The back contact cell of claim 16, wherein, The overlapping part is a discontinuous structure at the fourth cross section, so that the overlapping part includes a first part close to the electrically conductive doped part and a second part spaced from the first part at the fourth cross section. The second doped layer is conductive with the silicon substrate at a gap between the first part and the second part.

19. The back contact cell of claim 18, wherein, A length of a part of the silicon substrate corresponding to the first part in the first direction is less than 150 nm.

20. The back contact cell of claim 1 wherein, The silicon substrate has a silicon wafer extension part extending overhanging to the spacer region in the first direction, the silicon wafer extension part also has the first doped layer, a cross-sectional profile of the silicon wafer extension part is a triangle, and an included angle between a surface of the silicon wafer extension part facing the spacer region and a surface of the first region is an acute angle.

21. The back contact cell of claim 20, wherein, The silicon wafer extension part has an extension length in the first direction of 0.1 μm-3 μm.

22. A battery assembly comprising: A battery assembly including a plurality of back contact cells according to any one of claims 1-21.

23. A photovoltaic system characterized by, A battery assembly according to claim 22.

Images