Clamp plate and system for testing performance of high-speed interface of chip

Abstract

The utility model provides a clamp plate and system for testing the performance of a high-speed interface of a chip, and relates to the technical field of integrated circuit testing. The clamp plate comprises a PCB, a first high-speed connector arranged on the PCB and a second high-speed connector corresponding to the first high-speed connector. Wherein the first high-speed connector is used for being connected with a product board corresponding to a chip, the second high-speed connector is used for being connected with a CLB, and the first high-speed connector and the second high-speed connector are connected through PCB wiring. The first high-speed connector and the second high-speed connector are arranged on the PCB, and the first high-speed connector is directly connected with the product board corresponding to the chip, so that a test environment is closer to an actual application scene, and the accuracy of a test result is improved; besides, a special high-speed interface verification board does not need to be developed in advance, so that the development design, manufacturing and debugging links of the high-speed interface verification board are reduced, the period is remarkably shortened, and the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a fixture board and system for high-speed interface performance testing of chips. Background Technology

[0002] For electronic products, performance is typically improved through chip upgrades. However, chip development faces numerous uncertainties, especially regarding the performance of high-speed chip interfaces.

[0003] In related technologies, to obtain robust chips, system design manufacturers typically develop high-speed interface verification boards for the chips in advance. These boards are used to test the performance of the chip's high-speed interfaces before developing the corresponding product boards based on the test results. However, this approach suffers from problems such as long development cycles, high costs, and low accuracy of test results. Utility Model Content

[0004] This application provides a fixture board and system for testing the performance of high-speed chip interfaces, in order to solve the problems of long cycle, high cost and low accuracy of test results when testing the performance of high-speed chip interfaces using related technologies.

[0005] In a first aspect, this application provides a fixture board for high-speed interface performance testing of chips, including: a printed circuit board (PCB), a first high-speed connector disposed on the PCB, and a second high-speed connector corresponding to the first high-speed connector;

[0006] The first high-speed connector is used to connect to the product board corresponding to the chip;

[0007] The second high-speed connector is used to connect to the CLB (Compliance Load Board);

[0008] The first high-speed connector and the second high-speed connector are connected via PCB traces.

[0009] In one possible implementation, the second high-speed connector includes at least one of a CardElectromechanical (CEM) connector, an Open Compute Project (OCP) connector, and a U.2 connector.

[0010] In one possible implementation, there are multiple second high-speed connectors of the same type, and the PCB trace length corresponding to each second high-speed connector among the multiple second high-speed connectors increases based on a set loss value.

[0011] In one possible implementation, the first high-speed connector and the second high-speed connector correspond one-to-one and are symmetrically arranged on both sides of the PCB.

[0012] In one possible implementation, the first high-speed connector is of the same type as the high-speed connector corresponding to the product board.

[0013] In one possible implementation, the cable used to connect the first high-speed connector to the product board is the same as the cable used on the product board.

[0014] Secondly, this application provides a system for testing the performance of high-speed chip interfaces, comprising:

[0015] The clamping plate as described in any one of the first aspects;

[0016] CLB connected to the second high-speed connector in the fixture plate;

[0017] Test instruments connected to the CLB.

[0018] In one possible implementation, the test instrument includes at least one of an oscilloscope, a bit error rate tester, a spectrum analyzer, a signal generator, and a logic analyzer.

[0019] In one possible implementation, the CLB's interface is variable.

[0020] In one possible implementation, the fixture board is connected to the product under test (DUT) board corresponding to the chip via a cable, and the cable is the same as that used on the DUT board.

[0021] This application provides a fixture board and system for high-speed chip interface performance testing, comprising: a PCB, a first high-speed connector mounted on the PCB, and a second high-speed connector corresponding to the first high-speed connector; wherein, the first high-speed connector is used to connect to the product board corresponding to the chip, and the second high-speed connector is used to connect to the CLB, and the first and second high-speed connectors are connected via PCB traces. This application, by setting the first and second high-speed connectors on the PCB and directly connecting the first high-speed connector to the product board corresponding to the chip, makes the testing environment closer to the actual application scenario, thereby improving the accuracy and reliability of the chip high-speed interface performance test results; in addition, since the test can be performed directly on the product board without the need to develop a dedicated high-speed interface verification board in advance, the development, design, manufacturing, and debugging of the high-speed interface verification board are reduced, thereby significantly shortening the development cycle and reducing costs. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 This is a network diagram illustrating the use of a high-speed interface verification board for chip high-speed interface performance testing in related technologies.

[0024] Figure 2 A schematic diagram of the network topology of a fixture board for high-speed chip interface performance testing provided as an exemplary embodiment of this application;

[0025] Figure 3 A network diagram of another fixture board for high-speed chip interface performance testing provided as an exemplary embodiment of this application;

[0026] Figure 4 A network diagram of another fixture board for high-speed chip interface performance testing provided as an exemplary embodiment of this application when used for high-speed chip interface performance testing;

[0027] Figure 5 A schematic diagram of a system for high-speed chip interface performance testing provided as an exemplary embodiment of this application.

[0028] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0030] The terms “first,” “second,” etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or apparatus.

[0031] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0032] First, some of the terms used in this application will be explained:

[0033] MCIO connector: It is a high-speed connector for the mainstream external high-speed cable used for Peripheral Component Interconnect Express (PCIE) communication.

[0034] Sub-Miniature Version A (SMA) connector: refers to a type of coaxial connector.

[0035] CLB: An industry-standard fixture board for high-speed signal testing, replacing standard cards.

[0036] In related technologies, for server design manufacturers, high-speed interface verification boards are primarily used to verify the performance of PCIe interfaces. Specifically, when designing a high-speed interface verification board, each pair of PCIe signals needs to be routed to the edge of the board and connected to an SMA connector. A coaxial cable is then used to connect to a CEM (Card Electromechanical) test board, which is custom-developed for interfacing with a CLB (Content Module Block). The CLB is inserted into the CEM connector on the CEM test board, and a coaxial cable is used to connect the SMA connector on the CLB to the testing equipment for signal quality testing. The actual transmitting and receiving capabilities of the interface are tested by gradually increasing the length of the coaxial cable. For example... Figure 1 This is a network diagram illustrating the use of a high-speed interface verification board for high-speed chip interface performance testing in related technologies. (Example:) Figure 1 As shown, the SMA connector of the high-speed interface verification board is connected to the SMA connector of the CEM test board via a coaxial cable. The CLB is inserted into the CEM connector of the CEM test board, and the SMA connector on the CLB is connected to the test instrument via a coaxial cable.

[0037] However, since a dedicated high-speed interface verification board needs to be developed for the chip, the performance of the chip's high-speed interface is first tested using the high-speed interface verification board, and then the corresponding product board is developed based on the test results. The entire process involves the design, manufacturing, and debugging of both the high-speed interface verification board and the corresponding product board, resulting in a long development cycle and high costs. In addition, since the connectors on the high-speed interface verification board are SMA connectors, and the reflection and crosstalk performance of SMA connectors may be better than that of the actual connectors on the product board, the test results obtained through the high-speed interface verification board may not accurately reflect the high-speed interface performance of the product board.

[0038] To address the aforementioned issues, this application provides a solution for high-speed interface performance testing of chips. By developing a fixture board for high-speed interface performance testing, a first high-speed connector and a second high-speed connector are provided on the PCB of the fixture board. The first high-speed connector connects to the product board corresponding to the chip, making the testing environment closer to the actual application scenario, thereby improving the accuracy of the test results. In addition, since the test can be performed directly on the product board without the need to develop a dedicated high-speed interface verification board in advance, the design, manufacturing, and debugging of the high-speed interface verification board are reduced, thereby significantly shortening the development cycle and reducing costs.

[0039] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0040] Figure 2 This is a network diagram illustrating a fixture board for high-speed chip interface performance testing, provided as an exemplary embodiment of this application, during high-speed chip interface performance testing. (See diagram below.) Figure 2 As shown, the fixture board for high-speed interface performance testing of a chip includes: a PCB, a first high-speed connector mounted on the PCB, and a second high-speed connector corresponding to the first high-speed connector; wherein, the first high-speed connector is used to connect to the product board corresponding to the chip, the second high-speed connector is used to connect to the CLB, and the first high-speed connector and the second high-speed connector are connected by PCB traces.

[0041] The first high-speed connector is located on one side of the PCB, such as the left side, and is used to connect to the product board corresponding to the chip; the second high-speed connector is located on the other side of the PCB, such as the right side, and is used to connect to the CLB or other test equipment.

[0042] Accordingly, during high-speed interface performance testing, the product board corresponding to the chip is connected to the first high-speed connector of the fixture board via a high-speed cable, the CLB is connected to the fixture board via a second high-speed connector, and the CLB is connected to an external testing instrument via a coaxial cable. Furthermore, the interface of the product board (i.e., ...) is tested by gradually increasing the length of the high-speed cable. Figure 2 The actual transmit and receive capabilities of the third high-speed connector shown.

[0043] It should be noted that, Figure 2 The type of the third high-speed connector shown can be the same as or different from that of the first high-speed connector. When the type of the third high-speed connector is the same as that of the first high-speed connector, they can be directly connected through a high-speed cable. When the type of the third high-speed connector is different from that of the first high-speed connector, the connection between the third high-speed connector and the first high-speed connector can be achieved by setting an adapter, adding a conversion cable, or setting an intermediate interface board between the third high-speed connector, the high-speed cable, and the first high-speed connector.

[0044] The electric motor cooling system provided in this application embodiment, by setting a first high-speed connector and a second high-speed connector on the PCB, and directly connecting the first high-speed connector to the product board corresponding to the chip, makes the test environment closer to the actual application scenario, thereby improving the accuracy and reliability of the chip's high-speed interface performance test results. In addition, since the test can be performed directly on the product board without the need to develop a dedicated high-speed interface verification board in advance, the development, design, manufacturing and debugging of the high-speed interface verification board are reduced, thereby significantly shortening the development cycle and reducing costs.

[0045] In some embodiments, the second high-speed connector includes at least one of a CEM connector, an OCP connector, and a U.2 connector.

[0046] For example, in one implementation, the second high-speed connector includes any one of a CEM connector, an OCP connector, and a U.2 connector. For instance, the second high-speed connector is a CEM connector.

[0047] In another implementation, the second high-speed connector includes any two of the following: a CEM connector, an OCP connector, and a U.2 connector. For example, the second high-speed connector may include both a CEM connector and an OCP connector.

[0048] In another implementation, the second high-speed connector includes CEM connectors, OCP connectors, and U.2 connectors. For example, the second high-speed connector includes CEM connectors, OCP connectors, and U.2 connectors simultaneously.

[0049] In this embodiment, by supporting multiple types of high-speed connectors, the fixture board can be compatible with different standards and devices. It can not only verify standard PCIe connectors such as CEM connectors, but also cover OCP connectors and U.2 connectors, thereby enabling the same fixture board to be used in multiple test scenarios, improving the flexibility and efficiency of testing, while also reducing the need to design and manufacture multiple dedicated fixture boards, thus reducing the overall cost.

[0050] Considering that related technologies require testing using coaxial cables of varying lengths while maintaining consistent loss characteristics among the different cables, multiple coaxial cables are needed for testing, leading to high costs for testing materials. Furthermore, the repeated disconnection and tightening of SMA connectors due to the need for constant coaxial cable replacement makes the SMA connector interfaces prone to damage or wear. Therefore, in some embodiments, multiple second high-speed connectors of the same type are used, with the PCB trace length corresponding to each second high-speed connector increasing based on a predetermined loss value.

[0051] For example, Figure 3 This is a network diagram illustrating another fixture board for high-speed chip interface performance testing, provided as an exemplary embodiment of this application, when used for high-speed chip interface performance testing. (See diagram below.) Figure 3 As shown, the right side of the fixture plate is equipped with multiple second high-speed connectors of different types, namely high-speed connector 2, high-speed connector 3, and high-speed connector 4, with multiple high-speed connectors 2, 3, and 4. These high-speed connectors 2, 3, and 4 are connected to the first high-speed connector (i.e., high-speed connector 1) located on the left side of the fixture plate. For multiple second high-speed connectors of the same type, such as high-speed connector 2, the PCB trace length corresponding to each high-speed connector 2 increases based on a set loss value. In other words, the PCB trace length and loss are linearly positively correlated. For example, assuming a set loss value of 0.5dB@16GHz, the PCB trace lengths corresponding to each high-speed connector 2, such as length 1, length 2, ..., length n, increase by 0.5dB@16GHz, where n is a positive integer greater than or equal to 1.

[0052] Here, 0.5dB@16GHz means that at a frequency of 16GHz, the signal loss increases by 0.5dB for each additional PCB trace. This PCB routing method allows for precise control and adjustment of the electrical characteristics of the PCB traces, achieving incremental loss across the entire signal path. This enables accurate measurement of performance boundaries when applying this method to high-speed chip interface performance testing. Correspondingly, by using high-speed cables of appropriate length and sequentially selecting channels with increasing PCB trace lengths on the fixture board, the performance of the product board's high-speed interface can be preliminarily tested.

[0053] It should be noted that the above-mentioned loss setting of 0.5dB@16GHz is only an example. In actual applications, the loss setting can be based on the loss parameters of the selected fixture plate material, etc.

[0054] In this embodiment, channel loss is precisely adjusted by changing the PCB trace length, enabling test results to more accurately reflect the chip's true performance and further improving test result accuracy. In addition, by implementing loss adjustment on the PCB, reliance on external cables is reduced, thereby saving material costs. Furthermore, the built-in loss adjustment function reduces the need for cable replacement during testing, simplifies the testing process, and improves testing efficiency.

[0055] In some embodiments, the first high-speed connector and the second high-speed connector correspond one-to-one and are symmetrically arranged on both sides of the PCB.

[0056] For example, such as Figure 3 As shown, the high-speed connector 1 on the left side of the fixture plate is symmetrically arranged on the PCB with multiple high-speed connectors 2, multiple high-speed connectors 3 and multiple high-speed connectors 4 on the right side of the fixture plate. Each high-speed connector 1 is directly connected to the corresponding high-speed connector 2, high-speed connector 3 and high-speed connector 4 through the PCB traces inside the PCB.

[0057] In this embodiment, by setting the first high-speed connector and the second high-speed connector in a one-to-one correspondence, the signal transmission path is simplified and possible interference and crosstalk are reduced. In addition, by setting the first high-speed connector and the second high-speed connector on both sides of the PCB, signal reflection and loss are reduced, thereby improving signal integrity and further improving the reliability and consistency of test results.

[0058] In some embodiments, the first high-speed connector is of the same type as the high-speed connector corresponding to the product board.

[0059] For example, before designing the fixture board, if it is known that the type of high-speed connector corresponding to the product board is high-speed connector 1, then the first high-speed connector type designed for the fixture board is high-speed connector 1. For example, still referring to... Figure 3 The first high-speed connector on the left side of the fixture board is high-speed connector 1, and the corresponding high-speed connector on the product board is also high-speed connector 1. The two have the same interface type. Therefore, there is no need to introduce intermediate nodes such as adapters, conversion cables or intermediate interface boards, making the test environment for chip high-speed interface performance testing closer to the actual application environment.

[0060] In some embodiments, the cable used to connect the first high-speed connector to the product board is the same as the cable used on the product board.

[0061] For example, still refer to Figure 3 The cable used to connect the first high-speed connector to the product board is the same as the cable used on the product board. For example, if the cable used on the product board is an MCIO cable, then the high-speed cable used to connect the high-speed connector 1 of the fixture board to the high-speed connector 1 of the product board is an MCIO cable.

[0062] In this embodiment, by setting the first high-speed connector to be of the same type as the high-speed connector corresponding to the product board, and using the cable used by the product board to connect the first high-speed connector and the product board, the test environment for chip high-speed interface performance testing is closer to the actual application environment, thereby further improving the accuracy of the test results.

[0063] The above embodiments describe the implementation of a fixture board for high-speed chip interface performance testing. The following specific embodiments will illustrate the application of the fixture board for high-speed chip interface performance testing in high-speed chip interface performance testing.

[0064] For example, Figure 4 This is a network diagram illustrating the setup of another fixture board for high-speed chip interface performance testing, provided as an exemplary embodiment of this application, when used for high-speed chip interface performance testing. (See diagram below.) Figure 4 As shown, the first high-speed connector on the left side of the fixture board is an MCIO connector that interfaces with the product board; on the right side, there are CEM connectors, U.2 connectors, and OCP connectors, with n of each type of connector (e.g., n = 5, 10, and 20, etc.); the PCB size is, for example, 18 inch * 10 inch, and a PCB material with a loss value of, for example, 1dB / inch@16GHz is selected, and length1 = 5 inch, length2 = 5.5 inch, length3 = 6 inch, length4 = 6.5 inch, length5 = 7 inch, length6 = 7.5 inch, length7 = 8 inch, length8 = 8.5 inch, length9 = 9 inch, and length10 = 9.5 inch. By using PCB traces of different lengths corresponding to length1, length2, ..., length10, the channel loss can be adjusted from 5dB to 9.5dB. By using MCIO cables of appropriate length, the verification needs of various PCIE5 / 6 device scenarios can be basically covered.

[0065] In summary, this application has at least the following advantages:

[0066] First, by setting up a first high-speed connector and a second high-speed connector on the PCB, and directly connecting the chip to the corresponding product board through the first high-speed connector, the testing environment becomes closer to the actual application scenario, thereby improving the accuracy and reliability of the chip's high-speed interface performance test results. In addition, since the test can be performed directly on the product board without the need to develop a dedicated high-speed interface verification board in advance, the development, design, manufacturing and debugging of the high-speed interface verification board are reduced, thereby significantly shortening the development cycle and reducing costs.

[0067] Second, by supporting multiple types of high-speed connectors, the fixture board is compatible with different standards and devices. It can not only verify standard PCIe connectors such as CEM connectors, but also cover OCP connectors and U.2 connectors. This allows the same fixture board to be used in multiple test scenarios, improving the flexibility and efficiency of testing. At the same time, it reduces the need to design and manufacture multiple dedicated fixture boards, thereby reducing the overall cost.

[0068] Third, by adjusting the PCB trace length, the channel loss can be precisely adjusted, enabling the test results to more accurately reflect the chip's true performance and further improving the accuracy of the test results. In addition, by implementing loss adjustment on the PCB, the reliance on external cables is reduced, thereby saving material costs. Furthermore, the built-in loss adjustment function reduces the need for cable replacement during the testing process, simplifies the testing procedure, and improves testing efficiency.

[0069] Fourth, by setting the first high-speed connector to be the same type as the high-speed connector corresponding to the product board, and using the cable used by the product board to connect the first high-speed connector and the product board, the test environment for high-speed interface performance testing of the chip is closer to the actual application environment, which further improves the accuracy of the test results.

[0070] Figure 5 This is a schematic diagram of a system for high-speed chip interface performance testing, provided as an exemplary embodiment of this application. Figure 5 As shown, the system 50 for high-speed chip interface performance testing includes the fixture board 51 described in the above embodiments;

[0071] CLB52 is connected to the second high-speed connector 512 in the fixture 51;

[0072] Test instrument 53 connected to CLB52.

[0073] The system 50 for high-speed interface performance testing of the chip also includes a first high-speed connector 511, which is connected to a second high-speed connector 512 via PCB traces. For example, the second high-speed connector 512 includes at least one of a CEM connector, an OCP connector, and a U.2 connector. Multiple second high-speed connectors 512 of the same type can be used, and the PCB trace length corresponding to each of the multiple second high-speed connectors 512 increases incrementally based on a set loss value.

[0074] In some embodiments, the test instrument includes at least one of an oscilloscope, a bit error rate tester, a spectrum analyzer, a signal generator, and a logic analyzer.

[0075] For example, in one implementation, the test instrument includes any one of an oscilloscope, a bit error rate tester, a spectrum analyzer, a signal generator, and a logic analyzer. For instance, an oscilloscope is used to observe and analyze signal waveforms in real time, capture the transient characteristics of high-speed signals, and help identify signal integrity problems such as jitter, reflections, and crosstalk.

[0076] In another implementation, the test equipment includes any combination of oscilloscopes, bit error rate testers, spectrum analyzers, signal generators, and logic analyzers. For example, if the test equipment includes an oscilloscope and a bit error rate tester, an RF or microwave splitter can be used to split the signal transmitted by the CLB into two paths, one connected to the oscilloscope and the other to the bit error rate tester. The oscilloscope allows for real-time observation and analysis of the signal waveform, capturing the transient characteristics of high-speed signals and helping to identify signal integrity problems such as jitter, reflections, and crosstalk. The bit error rate tester detects and analyzes the bit error rate in data transmission, helping to evaluate the reliability and stability of the chip in high-speed data transmission.

[0077] In some embodiments, the CLB interface is variable.

[0078] For example, the CLB interface is variable; see reference for more information. Figure 4 When the second high-speed connector corresponds to a CEM connector, the interface type of the CLB can be set to CEM interface; when the second high-speed connector corresponds to an OCP connector, the interface type of the CLB can be set to OCP interface; when the second high-speed connector corresponds to a U.2 connector, the interface type of the CLB can be set to U.2 interface.

[0079] In this embodiment, by making the CLB's interface type variable, the system can adapt to different high-speed connector standards. This compatibility ensures that the same CLB can be used for multiple devices and interface standards, reducing the need for dedicated test equipment. Furthermore, the variable interface design allows for quick switching between different test configurations without replacing the entire CLB, enabling testers to respond quickly to different test requirements and conditions, thereby improving test efficiency.

[0080] In some embodiments, the fixture board is connected to the product under test (DUT) board corresponding to the chip via a cable, and the cable is the same as that used on the DUT board.

[0081] For example, if the high-speed cable used by the product board under test is an MCIO cable, then the high-speed cable used to connect the first connector of the fixture board to the high-speed connector of the product board under test is an MCIO cable.

[0082] In this embodiment, by using the cable used by the product board under test to connect the first high-speed connector to the product board under test, the test environment for high-speed interface performance testing of the chip is closer to the actual application environment, which further improves the accuracy of the test results.

[0083] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0084] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A fixture board for high-speed chip interface performance testing, characterized in that, include: A printed circuit board (PCB), a first high-speed connector disposed on the PCB, and a second high-speed connector corresponding to the first high-speed connector; The first high-speed connector is used to connect to the product board corresponding to the chip; The second high-speed connector is used for connection with the CLB; The first high-speed connector and the second high-speed connector are connected by PCB traces.

2. The clamping plate according to claim 1, characterized in that, The second high-speed connector includes at least one of the following: a Card Electromechanical (CEM) connector, an Open Computing Project (OCP) connector, and a U.2 connector.

3. The clamping plate according to claim 2, characterized in that, There are multiple second high-speed connectors of the same type, and the PCB trace length corresponding to each of the multiple second high-speed connectors increases based on a set loss value.

4. The clamping plate according to any one of claims 1 to 3, characterized in that, The first high-speed connector and the second high-speed connector are one-to-one corresponding and symmetrically arranged on both sides of the PCB.

5. The clamping plate according to any one of claims 1 to 3, characterized in that, The first high-speed connector is of the same type as the high-speed connector corresponding to the product board.

6. The clamping plate according to claim 5, characterized in that, The cable used to connect the first high-speed connector to the product board is the same as the cable used on the product board.

7. A system for testing the performance of high-speed chip interfaces, characterized in that, include: The clamping plate according to any one of claims 1 to 6; CLB connected to the second high-speed connector in the fixture plate; Test instruments connected to the CLB.

8. The system according to claim 7, characterized in that, The testing instruments include at least one of an oscilloscope, a bit error rate tester, a spectrum analyzer, a signal generator, and a logic analyzer.

9. The system according to claim 7 or 8, characterized in that, The interface of the CLB is variable.

10. The system according to claim 7 or 8, characterized in that, The fixture board is connected to the product board under test corresponding to the chip via a cable, and the cable is the same as the cable used by the product board under test.

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