Avionics function parallel test platform based on scene simulation

Abstract

The utility model belongs to the field of aircraft avionics system ground tests, and particularly relates to an avionics function parallel test platform based on scene simulation. Comprising a main control unit, a switch and a plurality of exciter terminals, the exciter terminals and the main control unit form a local area network through the switch; the main control unit sends a control instruction through a local area network, and the exciter terminal generates an excitation signal according to the control instruction; the excitation signal is transmitted to airborne equipment to be tested through a radio frequency cable; and the airborne equipment to be tested generates flight data after receiving the excitation signal, and the flight data is sent to the main control unit through the bus.

Description

Technical Field

[0001] This utility model belongs to the field of ground testing of aircraft avionics systems, and in particular relates to a parallel test platform for avionics functions based on scenario simulation. Background Technology

[0002] Modern aircraft avionics systems are becoming increasingly complex, with subsystems evolving towards high integration. The intricate interoperability and collaboration between these subsystems lead to lengthy integration testing times. To reduce testing and troubleshooting time for avionics systems, we investigate parallel testing strategies to significantly shorten the integration testing time. Utility Model Content

[0003] The purpose of this invention is to provide a parallel test platform for avionics functions based on scenario simulation, which consists of a main control unit, a switch, an exciter terminal, and a wiring harness, to realize parallel testing of the functions of various subsystems of a complex avionics system; and to provide a parallel test management component for simulating test task scenarios, implementing test plans, and processing and storing data, thereby improving the efficiency of avionics system integration testing.

[0004] The technical solution of this utility model:

[0005] A parallel test platform for avionics functions based on scenario simulation includes: a main control unit, a switch, and multiple exciter terminals;

[0006] Multiple actuator terminals and main control units form a local area network via a switch;

[0007] The main control unit sends control commands through the local area network, and the exciter terminal generates excitation signals according to the control commands;

[0008] The excitation signal is transmitted to the airborne equipment under test via an RF cable;

[0009] After receiving the excitation signal, the airborne equipment under test generates flight data, which is then sent to the main control unit via the bus.

[0010] Furthermore, the main control unit includes: a control computer, a data server, a simulation server, and a bus interface simulation module;

[0011] The bus interface simulation module is connected to the airborne equipment under test via a bus. The bus interface simulation module is also connected to the control computer, data server, and simulation server.

[0012] The simulation server is used for test scenario simulation, outputting simulation data and test plans;

[0013] The data server stores simulation data, test plans, and test results;

[0014] The computer controls the actuator terminal, data server, simulation server, and bus interface simulation module.

[0015] Furthermore, the bus interface simulation module includes three types of bus interface simulation boards: FC, A429, and 1553B.

[0016] Furthermore, multiple exciter terminals and the main control unit are physically independent via a local area network (LAN) composed of switches, namely:

[0017] The control network allows the control computer to control each actuator terminal.

[0018] Data network: Control computers transmit simulation data and test plans through the data network;

[0019] The clock network is used to synchronize clock information between the main control unit and the exciter terminal.

[0020] Furthermore, the types of actuator terminals include: compass actuators, beacon actuators, instrument landing actuators, microwave landing actuators, radio altimeter actuators, air traffic control actuators, TACAN actuators, and air collision avoidance actuators.

[0021] Furthermore, each exciter includes: a power board, a processor, a LAN interface, an RF receiver interface, an RF transmitter interface, a status display, a power button, and a power interface.

[0022] The beneficial effects of this utility model are:

[0023] 1. The platform employs a parallel testing strategy. Parallel testing of the navigation device's multi-waveform function test tasks is primarily achieved through a multi-channel structure and multi-threaded design. The connection between the navigation device and each exciter utilizes a multi-channel structure. The navigation device allocates independent RF transceiver channels for each navigation waveform function, and each navigation exciter is connected to its respective RF transceiver channel interface via RF cables. The parallel testing strategy employs a multi-threaded design, integrating the navigation device's test tasks into a single process. The processor then allocates each navigation waveform function test task to different threads, enabling parallel testing of multiple navigation waveform functions.

[0024] 2. A parallel testing platform for multiple navigation devices is implemented using a wiring harness to connect the testing platform and multiple navigation devices in parallel, reducing idle time, improving throughput, and allowing for the sharing of expensive testing equipment to reduce costs. The parallel testing strategy decomposes the testing tasks of eight navigation devices into eight multi-waveform parallel testing processes. The main control unit calls multiple processors to process the eight processes simultaneously, and after data processing and analysis, generates test results for multiple navigation devices. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a parallel testing platform for navigation equipment.

[0026] Figure 2 This is a schematic diagram of the main control unit.

[0027] Figure 3 This is a schematic diagram of the independent design of the three networks.

[0028] Figure 4 This is a schematic diagram of the navigation exciter.

[0029] Figure 5 This is a schematic diagram of a multi-threaded structure.

[0030] Figure 6 This is a schematic diagram of the testing process for a parallel testing platform for navigation equipment.

[0031] Figure 7 This is a schematic diagram of a parallel testing strategy for flight route scenarios.

[0032] Figure 8 This is a schematic diagram of the parallel testing strategy for the entry scenario.

[0033] Figure 9 This is a schematic diagram of the system architecture of a parallel testing platform for multiple navigation devices. Detailed Implementation

[0034] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0035] 1. Parallel testing platform for navigation equipment

[0036] i. This platform adopts a local area network (LAN) design, with the main control unit and each exciter terminal forming a LAN. The main control unit hosts a parallel test management component, including a simulation module, a control module, and a data processing module. The simulation module performs real-time dynamic simulation of various navigation signals required by the aircraft during the en route and approach phases. The control module generates test plans based on the scenario simulation and sends control commands to each exciter via the LAN. The data processing module processes and stores the flight data from the navigation equipment. Each exciter hosts a parallel test management software agent program, which receives control commands from the main control unit via the LAN and synchronously outputs simulated navigation ground station signals according to the control commands, enabling parallel testing of multiple navigation waveforms in the aircraft avionics system.

[0037] ii. Navigation actuators include, but are not limited to: compass actuators, beacon actuators, instrument landing actuators, microwave landing actuators, radio altimeter actuators, air traffic control actuators, TACAN actuators, and air collision avoidance actuators. The specific type will depend on the needs of the verification aircraft.

[0038] A schematic diagram of the parallel testing platform for navigation equipment is shown below. Figure 1 As shown.

[0039] (1) Main control unit

[0040] i. The main control unit consists of a bus interface simulation module, a simulation server, a data server, and a control computer.

[0041] ii. Bus interface simulation module: This module includes three types of bus interface simulation boards: FC, A429, and 1553B.

[0042] The schematic diagram of the main control unit is as follows: Figure 2 As shown.

[0043] The bus interface simulation module is connected to the airborne equipment via a bus, forwarding the bus service data of the airborne equipment to the data server and sending bus control commands to the airborne equipment, thereby realizing the bus service data transmission between the airborne equipment and the main control unit.

[0044] The simulation server performs test scenario simulations to achieve real-time dynamic simulation of the navigation ground station signals required by the aircraft during departure, en route, and approach phases, generating simulation data and test plans.

[0045] The data server backs up and stores bus service data, simulation data, test plans, and test results, and provides retrieval functionality.

[0046] The control computer hosts a parallel test management component, including a simulation module, a control module, and a data processing module. It provides users with a graphical user interface, including a test plan interface, a control command interface, an exciter status interface, and a test result interface. The test plan interface provides test task planning and test strategy settings, and offers test plan backup and search capabilities. The control command interface references test plans and generates specific parameter settings for each exciter, and also offers control command backup and search capabilities. The exciter status interface displays the real-time status of each exciter's parameter settings. The test result interface provides reports displaying bus service data and navigation signal test results, and offers test result backup and search capabilities. The control computer exchanges data with the bus interface simulation module, simulation server, data server, and each exciter via Ethernet.

[0047] (2) Switch

[0048] i. Switches are used to build local area networks, and the three networks are designed to be physically independent so that control commands, time information, and service data are independent and do not affect each other.

[0049] The platform is designed for the integration and verification testing of complex avionics systems. The network topology is highly complex, and the system's stability directly determines the effectiveness of the user's avionics system integration and verification testing. To improve system stability and ensure the accuracy of system testing, the switch is specially designed with physical independence for the three networks, ensuring that data does not interfere with each other.

[0050] There are three physically independent local area networks: a control network, a clock network, and a data network.

[0051] The control network is responsible for test control and data transmission of status between the control computer and each actuator, and can also perform online system monitoring.

[0052] The clock network is responsible for synchronizing the clock between the main control unit and each excitation device, which can effectively enable multi-exciter collaborative simulation of the external environment.

[0053] The data network is responsible for transmitting bus service data, simulation data, and experimental data between the control computer and the bus interface simulation module, simulation server, and data server.

[0054] A schematic diagram of the independent three-network design is shown below. Figure 3 As shown.

[0055] (3) Exciter

[0056] i. The navigation exciter integrates a network module and Ethernet port, enabling data exchange with the control computer via a local area network.

[0057] The following diagram shows the architecture of the navigation exciter:

[0058] The platform integrates a network module and Ethernet port within the navigation actuator to enable local area network (LAN) data interaction between the actuator and the control computer. The actuator receives control commands from the control computer via the LAN interface. These commands are processed by the network module and then sent to the core algorithm module. The core algorithm module, hosted on the parallel test management software's agent program, processes the control commands. The RF transceiver module generates the navigation RF signal required by the control command based on the data processing results and sends it to the onboard equipment via the RF transmit interface. The actuator also receives RF signals from the onboard equipment via the RF receive interface. After processing by the core algorithm module, it generates navigation signal test result data, which is then processed by the network module and forwarded to the control computer's test result display interface via the LAN. Simultaneously, the core algorithm module collects actuator status data, processes it through the network module, and forwards it to the control computer's actuator status display interface via the LAN.

[0059] A schematic diagram of the navigation exciter is shown below. Figure 4 As shown.

[0060] 2. Parallel Testing Methods

[0061] (1) Parallel testing of a single navigation device

[0062] i. Parallel testing of a single navigation device involves parallel testing of various navigation waveform function test tasks, mainly achieved by adopting a multi-channel structure and multi-threaded design.

[0063] The connection between the navigation equipment and each exciter adopts a multi-channel structure design. The navigation equipment assigns independent RF transceiver channels for each navigation waveform function. Each navigation exciter is connected to its respective RF transceiver channel interface via RF cables. Physical isolation is maintained between the RF channels of each navigation waveform function, effectively eliminating potential interference and coupling between different navigation waveform function test tasks. The main control unit is interconnected with each exciter via a local area network. The control computer controls the parameter settings of each exciter according to the test plan, and multiple navigation excitation signals are simultaneously sent to the navigation equipment, enabling parallel testing of multiple navigation waveform functions.

[0064] The parallel testing strategy employs a multi-threaded design, integrating the testing tasks of the navigation device into a single process. The processor then distributes the various navigation waveform function testing tasks to different threads, enabling parallel testing of multiple navigation waveform functions. Since all threads in the multi-threaded design reside within a single process, it allows for better sharing of test resources and data. Furthermore, switching between multiple threads incurs significantly less memory overhead compared to switching between multiple processes, resulting in shorter testing times and higher testing efficiency, making it a suitable parallel testing strategy.

[0065] A diagram of a multi-threaded architecture is shown below. Figure 5 As shown.

[0066] The main control platform's control computer hosts a parallel test management component, including a simulation module, a control module, and a data processing module.

[0067] The simulation module includes a task simulation module and a task editing module.

[0068] The task simulation module calls on simulation server resources to perform scenario simulation of the task and generate a test plan; the task editing module configures the test environment, test nodes, test items, test cases and multi-threaded parallel configuration according to the test plan.

[0069] The control module includes node control and parameter control. Based on the test plan, it generates test task scripts and automatically sends control commands to each exciter. Node control sends local area network node on / off control commands to the required navigation exciters; parameter control sends parameter control commands to each exciter.

[0070] The data processing module includes a result analysis module and a result backup and search module. The result analysis module performs packet capture, protocol conversion, and timestamp calibration on local area network data and bus data, and outputs the analysis results. The result backup and search module calls the data server to back up the test results and provides a search function.

[0071] A schematic diagram of the testing process for the parallel testing platform for navigation devices is shown below. Figure 6 As shown.

[0072] Example 1: For the flight scenario of an aircraft's flight path, the parallel testing strategy is as follows:

[0073] The simulation module performs mission simulations for flight route scenarios, generating test plans including functional tests of four navigation waveforms: radio altimeter, air traffic control, TACAN, and air collision avoidance. The mission editing module accesses node resources of the test platform via a local area network. The control module issues control commands to the radio altimeter exciter, air traffic control exciter, TACAN exciter, and air collision avoidance exciter to generate navigation signals, which are transmitted in parallel to the navigation equipment via radio frequency lines to simulate the simultaneous reception of multiple navigation signals by the aircraft in a real flight route scenario. The data processing module processes and analyzes the flight data from the navigation equipment and outputs the test results.

[0074] A schematic diagram of the parallel testing strategy for flight route scenarios is shown below. Figure 7 As shown.

[0075] Example 2: For the flight scenario of an aircraft approaching the airfield, the parallel testing strategy is as follows:

[0076] The simulation module performs task simulation for the approach scenario, generating test plans including tests of eight navigation waveform functions: compass, beacon, instrument landing, microwave landing, radio altimeter, air traffic control, TACAN, and air collision avoidance. The task editing module accesses node resources of the test platform via a local area network. The control module issues control commands to the compass exciter, beacon exciter, instrument landing exciter, microwave landing exciter, radio altimeter exciter, air traffic control exciter, TACAN exciter, and air collision avoidance exciter to generate navigation signals, which are transmitted in parallel to the navigation equipment via radio frequency lines to simulate the simultaneous reception of multiple navigation signals by the aircraft in a real aircraft approach scenario. The data processing module processes and analyzes the flight data from the navigation equipment and outputs the test results.

[0077] A schematic diagram of the parallel testing strategy for the entry scenario is shown below. Figure 8 As shown.

[0078] The parallel testing strategy integrates the scenario testing tasks of the navigation device into a single process. The simulation module decomposes the scenario testing tasks into various navigation waveform test items and assigns these items to multiple threads. The testing platform calls the corresponding navigation exciter to generate navigation signals and utilizes processor computing resources to perform parallel testing of multiple navigation waveform functions. After data processing and analysis, test results for multiple navigation waveforms are generated. All threads in the multi-threaded testing strategy reside within a single process, allowing for better sharing of the testing platform's computing resources, resulting in shorter testing time and higher testing efficiency.

[0079] (2) Parallel testing of multiple navigation devices

[0080] i. Parallel testing of multiple navigation devices is a parallel test that simultaneously completes multiple navigation waveform function test tasks for multiple navigation devices.

[0081] A wiring harness was added to the parallel test platform for multiple navigation devices, enabling parallel connection of multiple navigation devices with the test platform. The bus and RF interfaces of multiple navigation devices are connected in parallel with the wiring harness. The wiring harness connects the main control unit bus interface with the bus interfaces of multiple navigation devices, and connects the RF interfaces of multiple navigation devices with their corresponding navigation exciters.

[0082] The wiring harness integrates a bus interface management module, enabling the main control unit to manage and configure multiple navigation device bus nodes.

[0083] The wiring harness integrates a power divider circuit and a gain control circuit. The power divider circuit distributes the navigation excitation signals sent by each exciter to multiple navigation devices. The gain control circuit compensates for the energy attenuation of the navigation excitation signals after passing through the power divider circuit, ensuring that the navigation excitation signals received by multiple navigation devices are consistent with the navigation excitation signals sent by the exciter.

[0084] A parallel testing platform for multiple navigation devices enables the test platform and multiple navigation devices to be connected in parallel via a wiring harness, reducing the idle time of the test platform, improving throughput, and allowing the sharing of expensive test equipment to reduce costs.

[0085] A schematic diagram of the system architecture of a parallel testing platform for multiple navigation devices is shown below. Figure 9 As shown.

[0086] The parallel testing strategy for eight navigation devices is as follows:

[0087] Eight navigation devices are connected in parallel via a patch panel. The patch panel's bus interface management module assigns eight nodes to the main control unit, labeled as devices 1-8. The simulation module performs task simulation on the eight navigation devices and generates test items. The eight navigation signal waveforms are abbreviated as AH. The test items for the eight navigation waveforms of each device are arranged in a traversal manner into eight test processes.

[0088] The parallel testing strategy decomposes the test tasks of eight navigation devices into eight parallel multi-waveform test processes for navigation devices. The main control unit calls multiple processors to process the eight processes simultaneously, and after data processing and analysis, generates test results for multiple navigation devices.

[0089] The parallel testing strategy connects eight navigation devices to a single test platform, reducing the cost of the test platform and improving efficiency. The testing tasks for the eight navigation devices are broken down into eight test processes that are processed simultaneously, reducing testing time and improving overall testing efficiency.

[0090] The parallel testing strategy for the eight navigation devices is shown in Table 1:

[0091] Table 1 Parallel Testing Strategies for Eight Navigation Devices

[0092] Equipment 1 Equipment 2 Equipment 3 Equipment 4 Equipment 5 Equipment 6 Equipment 7 Equipment 8 Process 1 A B C D E F G H Process 2 H A B C D E F G Process 3 G H A B C D E F Process 4 F G H A B C D E Process 5 E F G H A B C D Process 6 D E F G H A B C Process 7 C D E F G H A B Process 8 B C D E F G H A

[0093] The above description is merely a specific embodiment of this utility model, providing a detailed description of the utility model. Parts not covered in detail are conventional techniques. However, the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this utility model should be included within the protection scope of this utility model. The protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A parallel test platform for avionics functions based on scenario simulation, characterized in that: The platform includes: a main control unit, a switch, and multiple exciter terminals; Multiple actuator terminals and main control units form a local area network via a switch; The main control unit sends control commands through the local area network, and the exciter terminal generates excitation signals according to the control commands; The excitation signal is transmitted to the airborne equipment under test via an RF cable; After receiving the excitation signal, the airborne equipment under test generates flight data, which is then sent to the main control unit via the bus.

2. The parallel test platform for avionics functions based on scenario simulation according to claim 1, characterized in that: The main control unit includes: a control computer, a data server, a simulation server, and a bus interface simulation module; The bus interface simulation module is connected to the airborne equipment under test via a bus. The bus interface simulation module is also connected to the control computer, data server, and simulation server. The simulation server is used for test scenario simulation, outputting simulation data and test plans; The data server stores simulation data, test plans, and test results; The computer controls the actuator terminal, data server, simulation server, and bus interface simulation module.

3. The parallel test platform for avionics functions based on scenario simulation according to claim 2, characterized in that: The bus interface simulation module includes three types of bus interface simulation boards: FC, A429, and 1553B.

4. The parallel test platform for avionics functions based on scenario simulation according to claim 3, characterized in that: Multiple actuator terminals and main control units are physically independent via a local area network (LAN) composed of switches, namely: The control network allows the control computer to control each actuator terminal. Data network: Control computers transmit simulation data and test plans through the data network; The clock network is used to synchronize clock information between the main control unit and the exciter terminal.

5. The parallel test platform for avionics functions based on scenario simulation according to claim 4, characterized in that: Exciter terminal types include: compass exciters, beacon exciters, instrument landing exciters, microwave landing exciters, radio altimeter exciters, air traffic control exciters, TACAN exciters, and air collision avoidance exciters.

6. The parallel test platform for avionics functions based on scenario simulation according to claim 5, characterized in that: Each exciter includes: a power board, a processor, a LAN interface, an RF receiver interface, an RF transmitter interface, a status display, a power button, and a power interface.

Images