Network card interface circuit for virtual reality equipment

Abstract

The utility model relates to a network card interface circuit for virtual reality equipment. The network card interface circuit comprises a network cable end circuit and a USB end circuit, the network cable end circuit comprises a network card chip, a network transformer and a network cable interface; wherein the network card chip is connected with the network cable interface through the network transformer; the USB end circuit comprises the network card chip and a USB plug; wherein the network card chip is connected with the USB plug; compared with the prior art, the technical scheme of the utility model can improve the data transmission distance.

Description

Technical Field

[0001] This application relates to the field of virtual reality technology, and more particularly to a network card interface circuit for virtual reality devices. Background Technology

[0002] In the field of virtual reality headset technology, the application of technologies such as USB streaming and DP streaming faces a series of challenges, which affect the performance of headset devices and user experience.

[0003] First, while USB streaming technology provides high-bandwidth wired connections, it is limited by cable length. Generally, USB cables shorter than 5 meters can stream stably, but beyond 3 meters, some cables may not stream stably, and beyond 5 meters, almost all cables cannot stream stably. This is because the characteristic impedance and insertion loss of USB cables have strict requirements for signal transmission quality, and long cables are difficult to manufacture and cannot meet these requirements. Second, similar to USB, DP streaming technology is also limited by streaming distance and can only stream video content. Human-computer interaction data still needs to be transmitted via USB, which limits the use of DP streaming in virtual reality applications that require high bandwidth and low latency. Utility Model Content

[0004] This application provides a network card interface circuit for virtual reality devices, which can solve the problem of short data transmission distance in existing systems.

[0005] In a first aspect, this application provides a network card interface circuit for a virtual reality device, comprising: a network cable end circuit and a USB end circuit; the network cable end circuit includes a network card chip, a network transformer, and a network cable interface; wherein the network card chip is connected to the network cable interface through the network transformer; the USB end circuit includes the network card chip and a USB plug; wherein the network card chip is connected to the USB plug.

[0006] Further, the network interface card (NIC) chip includes a first NIC chip pin, a second NIC chip pin, a fourth NIC chip pin, a fifth NIC chip pin, a sixth NIC chip pin, a seventh NIC chip pin, a ninth NIC chip pin, and a tenth NIC chip pin; the network cable interface includes a first network cable interface pin, a second network cable interface pin, a third network cable interface pin, a fourth network cable interface pin, a fifth network cable interface pin, a sixth network cable interface pin, a seventh network cable interface pin, and an eighth network cable interface pin; wherein, the first NIC chip pin is connected to the first network cable interface pin through the network transformer, and the second NIC chip pin is connected to the network transformer through the network transformer. The device is connected to the second network cable interface pin. The fourth network card chip pin is connected to the third network cable interface pin through the network transformer. The fifth network card chip pin is connected to the fourth network cable interface pin through the network transformer. The sixth network card chip pin is connected to the fifth network cable interface pin through the network transformer. The seventh network card chip pin is connected to the sixth network cable interface pin through the network transformer. The ninth network card chip pin is connected to the seventh network cable interface pin through the network transformer. The tenth network card chip pin is connected to the eighth network cable interface pin through the network transformer.

[0007] Further, the network transformer includes a second transformer pin, a third transformer pin, a fifth transformer pin, a sixth transformer pin, an eighth transformer pin, a ninth transformer pin, an eleventh transformer pin, a twelfth transformer pin, a thirteenth transformer pin, a fourteenth transformer pin, a sixteenth transformer pin, a seventeenth transformer pin, a nineteenth transformer pin, a twentieth transformer pin, a twenty-second transformer pin, and a twenty-third transformer pin; wherein, the first network card chip pin is connected to the second transformer pin, the second network card chip pin is connected to the third transformer pin, the fourth network card chip pin is connected to the fifth transformer pin, the fifth network card chip pin is connected to the sixth transformer pin, the sixth network card chip pin is connected to the eighth transformer pin, and the seventh... The network card chip pin is connected to the ninth transformer pin, the ninth network card chip pin is connected to the eleventh transformer pin, and the tenth network card chip pin is connected to the twelfth transformer pin; the thirteenth transformer pin is connected to the eighth network cable interface pin, the fourteenth transformer pin is connected to the seventh network cable interface pin, the sixteenth transformer pin is connected to the sixth network cable interface pin, the seventeenth transformer pin is connected to the fifth network cable interface pin, the nineteenth transformer pin is connected to the fourth network cable interface pin, the twentieth transformer pin is connected to the third network cable interface pin, the twenty-second transformer pin is connected to the second network cable interface pin, and the twenty-third transformer pin is connected to the first network cable interface pin.

[0008] Further, the network transformer includes a fifteenth transformer pin, an eighteenth transformer pin, a twenty-first transformer pin, and a twenty-fourth transformer pin; the network cable interface includes a ninth network cable interface pin and a tenth network cable interface pin; the network cable terminal circuit also includes a first resistor, a second resistor, a fourth resistor, a fifth resistor, a third capacitor, a fifth capacitor, and a sixth capacitor; wherein, the twenty-fourth transformer pin is connected to the first end of the first resistor, the twenty-first transformer pin is connected to the first end of the second resistor, the eighteenth transformer pin is connected to the first end of the fourth resistor, the fifteenth transformer pin is connected to the first end of the fifth resistor, the second ends of the first resistor, the second ends of the second resistor, the second ends of the fourth resistor, and the second ends of the fifth resistor are respectively connected to the first end of the third capacitor, the second end of the third capacitor is respectively connected to the first ends of the fifth capacitor and the sixth capacitor, the ninth network cable interface pin and the tenth network cable interface pin are respectively connected to the first ends of the fifth capacitor and the sixth capacitor, and the second ends of the fifth capacitor and the sixth capacitor are respectively grounded.

[0009] Furthermore, the USB terminal circuit also includes a seventh capacitor and an eighth capacitor; the network card chip includes a twelfth network card chip pin, a thirteenth network card chip pin, a fifteenth network card chip pin, a sixteenth network card chip pin, a seventeenth network card chip pin, and an eighteenth network card chip pin; the USB plug includes a second USB pin, a third USB pin, a sixth USB pin, a seventh USB pin, a tenth USB pin, and an eleventh USB pin; wherein, the twelfth network card chip pin is connected to the first end of the seventh capacitor, the second end of the seventh capacitor is connected to the tenth USB pin, the thirteenth network card chip pin is connected to the first end of the eighth capacitor, the second end of the eighth capacitor is connected to the eleventh USB pin, the fifteenth network card chip pin is connected to the third USB pin, the sixteenth network card chip pin is connected to the second USB pin, the seventeenth network card chip pin is connected to the seventh USB pin, and the eighteenth network card chip pin is connected to the sixth USB pin.

[0010] Furthermore, the USB plug also includes a first USB pin and a ninth USB pin; wherein the ninth USB pin is connected to the first power supply circuit, and the first USB pin is grounded.

[0011] Further, the first power supply circuit includes a power input terminal, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a power supply voltage, and a register power supply voltage; wherein, the power input terminal is connected to the first terminal of the ninth capacitor, the first terminal of the power supply voltage, and the first terminal of the register power supply voltage, respectively; the second terminal of the register power supply voltage is connected to the first terminal of the tenth capacitor and the first terminal of the eleventh capacitor, respectively, and the second terminal of the register power supply voltage is connected to the first terminal of the twelfth capacitor and the first terminal of the thirteenth capacitor, respectively; the second terminals of the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth capacitor, and the thirteenth capacitor are grounded.

[0012] Furthermore, the network card interface circuit for a virtual reality device provided in this application further includes: a data transceiver circuit; the data transceiver circuit includes a network card chip, a ninth resistor, a tenth resistor, a first LED, and a second LED; wherein the network card chip includes a thirtieth network card chip pin and a thirty-second network card chip pin.

[0013] Furthermore, the thirtieth network card chip pin is connected to the first end of the tenth resistor, the second end of the tenth resistor is connected to the positive terminal of the second LED, and the negative terminal of the second LED is grounded. The thirty-second network card chip pin is connected to the first end of the ninth resistor, the second end of the ninth resistor is connected to the positive terminal of the first LED, and the negative terminal of the first LED is grounded.

[0014] Furthermore, the network cable interface is connected to the terminal device via a network cable, and the USB plug is connected to the virtual reality device.

[0015] The technical solutions provided in this application have the following advantages compared with the prior art:

[0016] This application provides a network card interface circuit for a virtual reality device, comprising: a network cable end circuit and a USB end circuit; in the network cable end circuit, the network card chip is connected to the network cable interface through a network transformer; in the USB end circuit, the network card chip is connected to the USB plug; in this process, the combination of the network card chip and the network transformer can effectively filter out common-mode interference and enhance the signal. Moreover, since the network card chip is connected to both the network cable interface and the USB plug, it can take advantage of the stability and long-distance transmission of the network cable, thereby overcoming the limitation of the USB cable length and increasing the data transmission distance. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This application provides a schematic diagram of the structure of a network card interface circuit for a virtual reality device.

[0021] Figure 2 A schematic diagram of the pin structure of a network interface card (NIC) chip provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram of the pin structure of a network cable interface provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the pin structure of a network transformer provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of the network cable terminal circuit provided in the embodiments of this application;

[0025] Figure 6 This is a schematic diagram of the 1V power supply circuit provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the 3V3 power supply and filter circuit provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the USB terminal circuit provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of the first power supply circuit provided in an embodiment of this application;

[0029] Figure 10 This is a schematic diagram of the structure of the data transceiver circuit provided in the embodiments of this application. Detailed Implementation

[0030] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] The following disclosure provides numerous different embodiments or examples for implementing various structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0032] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0033] Example 1

[0034] See Figure 1 , Figure 1 This is a schematic diagram of the network card interface circuit for a virtual reality device provided by this utility model, as shown below. Figure 1 As shown, the network card interface circuit includes a network cable end circuit 101 and a USB end circuit 102, as detailed below:

[0035] The network cable terminal circuit 101 includes a network card chip U2, a network transformer L1, and a network cable interface CN1; wherein, the network card chip U2 is connected to the network cable interface CN1 through the network transformer L1.

[0036] The USB terminal circuit 102 includes the network card chip U2 and the USB plug USB1; wherein the network card chip U2 is connected to the USB plug USB1.

[0037] In one embodiment, the network interface card (NIC) chip U2 includes a first NIC chip pin MDIO+, a second NIC chip pin MDIO-, a fourth NIC chip pin MDI1+, a fifth NIC chip pin MDI1-, a sixth NIC chip pin MDI2+, a seventh NIC chip pin MDI2-, a ninth NIC chip pin MDI3+, and a tenth NIC chip pin MDI3-, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of the pin structure of a network interface card (NIC) chip.

[0038] In one embodiment, the network cable interface CN1 includes a first network cable interface pin MX0+, a second network cable interface pin MX0-, a third network cable interface pin MX1+, a fourth network cable interface pin MX1-, a fifth network cable interface pin MX2+, a sixth network cable interface pin MX2-, a seventh network cable interface pin MX3+, and an eighth network cable interface pin MX3-; as shown Figure 3 As shown, Figure 3 This is a schematic diagram of the pin structure of a network cable interface.

[0039] In one embodiment, the first network interface card (NIC) chip pin MDIO+ is connected to the first network cable interface pin MX0+ through the network transformer L1; the second NIC chip pin MDIO- is connected to the second network cable interface pin MX0- through the network transformer L1; the fourth NIC chip pin MDI1+ is connected to the third network cable interface pin MX1+ through the network transformer L1; the fifth NIC chip pin MDI1- is connected to the fourth network cable interface pin MX1- through the network transformer L1; the sixth NIC chip pin MDI2+ is connected to the fifth network cable interface pin MX2+ through the network transformer L1; the seventh NIC chip pin MDI2- is connected to the sixth network cable interface pin MX2- through the network transformer L1; the ninth NIC chip pin MDI3+ is connected to the seventh network cable interface pin MX3+ through the network transformer L1; and the tenth NIC chip pin MDI3- is connected to the eighth network cable interface pin MX3- through the network transformer L1.

[0040] In one embodiment, the network transformer L1 includes a second transformer pin, a third transformer pin, a fifth transformer pin, a sixth transformer pin, an eighth transformer pin, a ninth transformer pin, an eleventh transformer pin, a twelfth transformer pin, a thirteenth transformer pin, a fourteenth transformer pin, a sixteenth transformer pin, a seventeenth transformer pin, a nineteenth transformer pin, a twentieth transformer pin, a twenty-second transformer pin, and a twenty-third transformer pin; as shown Figure 4 As shown, Figure 4 This is a schematic diagram of the pin structure of a network transformer.

[0041] like Figure 5 As shown, Figure 5 This is a schematic diagram of the network cable terminal circuit. When the network card chip U2 is connected to the network transformer L1, the first network card chip pin MDIO+ is connected to the second transformer pin, the second network card chip pin MDIO- is connected to the third transformer pin, the fourth network card chip pin MDI1+ is connected to the fifth transformer pin, the fifth network card chip pin MDI1- is connected to the sixth transformer pin, the sixth network card chip pin MDI2+ is connected to the eighth transformer pin, the seventh network card chip pin MDI2- is connected to the ninth transformer pin, the ninth network card chip pin MDI3+ is connected to the eleventh transformer pin, and the tenth network card chip pin MDI3- is connected to the twelfth transformer pin. The pins are connected as follows: When the network transformer L1 is connected to the network cable interface CN1, the thirteenth transformer pin is connected to the eighth network cable interface pin MX3-, the fourteenth transformer pin is connected to the seventh network cable interface pin MX3+, the sixteenth transformer pin is connected to the sixth network cable interface pin MX2-, the seventeenth transformer pin is connected to the fifth network cable interface pin MX2+, the nineteenth transformer pin is connected to the fourth network cable interface pin MX1-, the twentieth transformer pin is connected to the third network cable interface pin MX1+, the twenty-second transformer pin is connected to the second network cable interface pin MX0-, and the twenty-third transformer pin is connected to the first network cable interface pin MX0+.

[0042] In one embodiment, the network transformer L1 includes a fifteenth transformer pin, an eighteenth transformer pin, a twenty-first transformer pin, and a twenty-fourth transformer pin.

[0043] In one embodiment, the network cable interface CN1 includes a ninth network cable interface pin and a tenth network cable interface pin.

[0044] In one embodiment, the network cable terminal circuit 101 further includes a first resistor R1, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, a fifth capacitor C5, and a sixth capacitor C6.

[0045] In one embodiment, the 24th transformer pin is connected to the first end of the first resistor R1, the 21st transformer pin is connected to the first end of the second resistor R2, the 18th transformer pin is connected to the first end of the fourth resistor R4, and the 15th transformer pin is connected to the first end of the fifth resistor R5. The second ends of the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5 are respectively connected to the first end of the third capacitor C3. The second end of the third capacitor C3 is respectively connected to the first end of the fifth capacitor C5 and the first end of the sixth capacitor C6. The 9th and 10th network cable interface pins are respectively connected to the first end of the fifth capacitor C5 and the first end of the sixth capacitor C6. The second ends of the fifth capacitor C5 and the sixth capacitor C6 are respectively grounded. Figure 5 As shown.

[0046] In one embodiment, the network transformer L1 further includes a first transformer pin, a fourth transformer pin, a seventh transformer pin, and a tenth transformer pin.

[0047] In one embodiment, the USB terminal circuit 102 further includes a fourth capacitor C4.

[0048] Specifically, the first transformer pin, the fourth transformer pin, the seventh transformer pin, and the tenth transformer pin are respectively connected to the first terminal of the fourth capacitor C4, and the second terminal of the fourth capacitor C4 is grounded.

[0049] In one embodiment, in the network cable terminal circuit 101, the network card chip U2 further includes a third network card chip pin, an eighth network card chip pin, and an eleventh network card chip pin.

[0050] Specifically, the third and eighth network card chip pins are connected to a 1V power supply circuit, and the eleventh network card chip pin is connected to a 3V3 power supply and a filtering circuit.

[0051] like Figure 6 As shown, Figure 6This is a schematic diagram of a 1V power supply circuit. The 1V power supply circuit includes a 23rd capacitor C23, a 24th capacitor C24, a 25th capacitor C25, a 26th capacitor C26, a 27th capacitor C27, a 28th capacitor C28, a 29th capacitor C29, and a second inductor L2. The output voltage pin is connected to the first terminal of the second inductor L2. The second terminal of the second inductor L2 is connected to the first terminals of the 23rd capacitor C23, the 24th capacitor C24, the 25th capacitor C25, the 26th capacitor C26, the 27th capacitor C27, the 28th capacitor C28, and the 29th capacitor C29. The second terminals of the 23rd capacitor C23, the 24th capacitor C24, the 25th capacitor C25, the 26th capacitor C26, the 27th capacitor C27, the 28th capacitor C28, and the 29th capacitor C29 are grounded.

[0052] Preferably, the portion where the second terminal of the second inductor L2 is connected to the first terminal of the twenty-eighth capacitor C28 and the first terminal of the twenty-ninth capacitor C29, and the portion where the second terminal of the twenty-eighth capacitor C28 and the second terminal of the twenty-ninth capacitor C29 are respectively grounded, can also be configured such that the second terminal of the second inductor L2 is connected to the first terminal of the thirtieth capacitor C30, the first terminal of the thirty-first capacitor C31, and the first terminal of the thirty-second capacitor C32, and the second terminals of the thirtieth capacitor C30, the thirty-first capacitor C31, and the thirty-second capacitor C32 are respectively grounded; similarly, it can also be configured such that the second terminal of the second inductor L2 is connected to the first terminal of the thirty-third capacitor C33, and the second terminal of the thirty-third capacitor C33 is grounded.

[0053] like Figure 7 As shown, Figure 7This is a schematic diagram of a 3V3 power supply and filtering circuit. The 3V3 power supply and filtering circuit includes a voltage regulator VDDREG33, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, and a twenty-second capacitor C22. Specifically, the output terminal of the 3V3 power supply is connected to the first terminal of the voltage regulator VDDREG33, the first terminal of the fourteenth capacitor C14, the first terminal of the fifteenth capacitor C15, the first terminal of the sixteenth capacitor C16, the first terminal of the seventeenth capacitor C17, the first terminal of the eighteenth capacitor C18, the first terminal of the nineteenth capacitor C19, the first terminal of the twentieth capacitor C20, the first terminal of the twenty-first capacitor C21, and the first terminal of the twenty-second capacitor C22. The first terminal of capacitor C18, the first terminal of the nineteenth capacitor C19, and the first terminal of the twentieth capacitor C20 are connected together. The second terminal of the voltage regulator VDDREG33 is connected to the first terminal of the twenty-first capacitor C221 and the first terminal of the twenty-second capacitor C22, respectively. The second terminals of the fourteenth capacitor C13, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19, the twentieth capacitor C20, the twenty-first capacitor C21, and the twenty-second capacitor C22 are grounded.

[0054] In one embodiment, the network cable interface CN1 is connected to the terminal device via a network cable; preferably, the terminal device includes a computer PC.

[0055] In one embodiment, the USB terminal circuit 102 further includes a seventh capacitor C7 and an eighth capacitor C8.

[0056] In one embodiment, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the pin structure of a network interface card (NIC) chip. The NIC chip U2 includes the twelfth NIC chip pin SSTX-, the thirteenth NIC chip pin SSTX+, the fifteenth NIC chip pin SSRX-, the sixteenth NIC chip pin SSRX+, the seventeenth NIC chip pin DM, and the eighteenth NIC chip pin DP.

[0057] Preferably, the USB terminal circuit 102 further includes an eighth resistor R8, which is connected to the first end of the eighth resistor R8 via the fifth USB pin A5 in the USB plug USB1, and the second end of the eighth resistor R8 is grounded.

[0058] In one embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the pin structure of a network cable interface. The USB plug USB1 includes a second USB pin A2, a third USB pin A3, a sixth USB pin A6, a seventh USB pin AA7, a tenth USB pin B10, and an eleventh USB pin B11.

[0059] In one embodiment, the twelfth network card chip pin SSTX- is connected to the first terminal of the seventh capacitor C7, the second terminal of the seventh capacitor C7 is connected to the tenth USB pin B10, the thirteenth network card chip pin SSTX+ is connected to the first terminal of the eighth capacitor C8, the second terminal of the eighth capacitor C8 is connected to the eleventh USB pin B11, the fifteenth network card chip pin SSRX- is connected to the third USB pin A3, the sixteenth network card chip pin SSRX+ is connected to the second USB pin A2, the seventeenth network card chip pin DM is connected to the seventh USB pin A7, and the eighteenth network card chip pin DP is connected to the sixth USB pin A6. Figure 8 As shown, Figure 8 This is a schematic diagram of the USB end circuit.

[0060] In one embodiment, the USB plug USB1 further includes a first USB pin A1 and a ninth USB pin A9, the ninth USB pin A9 being connected to a first power supply circuit, and the first USB pin A1 being grounded; power supply is provided to the USB plug USB1 through the first USB pin A1 and the ninth USB pin A9.

[0061] like Figure 9 As shown, Figure 9 This is a schematic diagram of the first power supply circuit, which includes a power input terminal, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a register power supply voltage VDDREG5, and a power supply voltage VDD5. The power input terminal VBUS is connected to the first terminals of the ninth capacitor C9, the register power supply voltage VDDREG5, and the power supply voltage VDD5. The second terminal of the register power supply voltage VDDREG5 is connected to the first terminals of the tenth capacitor C10 and the eleventh capacitor C11. The second terminal of the power supply voltage VDD5 is connected to the first terminals of the twelfth capacitor C12 and the thirteenth capacitor C13. The second terminals of the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, and the thirteenth capacitor C13 are grounded.

[0062] In one embodiment, in the USB terminal circuit 102, the network card chip U2 further includes a fourteenth network card chip pin, a nineteenth network card chip pin, and a twentieth network card chip pin.

[0063] Specifically, the fourteenth and nineteenth network card chip pins are connected to the 1V power supply circuit, and the twentieth network card chip pin is connected to the 3V3 power supply and filter circuit.

[0064] In one embodiment, the USB plug USB1 is connected to a virtual reality device; preferably, the virtual reality device includes a virtual reality headset.

[0065] In one embodiment, both the network card chip U2 and the virtual reality headset support the RNDIS protocol, which is a remote network driver interface protocol that allows devices to simulate network connections via USB. With the support of the USB network card, the virtual reality headset has the ability to connect to the network via a network cable.

[0066] The network card interface circuit of the virtual reality device provided in this embodiment also includes a data transceiver circuit.

[0067] In one embodiment, the data transceiver circuit includes a network interface card (NIC) chip U2, a ninth resistor R9, a tenth resistor R10, a first LED LED1, and a second LED LED2; wherein, the NIC chip U2 includes a thirtieth NIC chip pin LED1 / SPICS and a thirty-second NIC chip pin LED0 / SPICS.

[0068] In one embodiment, the 30th network card chip pin LED1 / SPICS is connected to the first end of the 10th resistor R10, the second end of the 10th resistor R10 is connected to the positive terminal of the second LED LED2, and the negative terminal of the second LED LED2 is grounded. The 32nd network card chip pin LED0 / SPICS is connected to the first end of the 9th resistor R9, the second end of the 9th resistor R9 is connected to the positive terminal of the first LED LED1, and the negative terminal of the first LED LED1 is grounded. Figure 10 As shown, Figure 10 This is a schematic diagram of the structure of a data transceiver circuit.

[0069] In one embodiment, the first LED LED1 is a network connection indicator. When connected to the network, the first LED LED11 remains constantly lit. The second LED LED2 is a data transmission indicator. When data is being transmitted or received, the second LED LED2 flashes according to the data transmission and reception frequency.

[0070] In one embodiment, in the data transceiver circuit, the network card chip U2 includes a thirty-fifth network card chip pin XTAL1 and a thirty-sixth network card chip pin XTAL2. The data transceiver circuit also includes a crystal oscillator X1, a first capacitor C1, and a second capacitor C2. The crystal oscillator X1 includes a first interface 1, a second interface 2, a third interface 3, and a fourth interface 4.

[0071] Specifically, the 35th network card chip pin XTAL1 is connected to the first end of the first capacitor C1 and the first interface 1, respectively. The second end of the first capacitor C1, the second interface 2 and the fourth interface are grounded. The 36th network card chip pin XTAL2 is connected to the third interface 3 and the first end of the second capacitor C2. The third interface 3 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is grounded.

[0072] In one embodiment, in the data transceiver circuit, the network card chip U2 further includes a 38th network card chip pin and a 25th network card chip pin SPISI / ENSWREG. The 25th network card chip pin SPISI / ENSWREG is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the 3V3 power supply and filter circuit, the 38th network card chip pin is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded.

[0073] In one embodiment, the USB end circuit 102 is located on the USB plug USB1 of the USB network card, the network cable end circuit 101 is located on the network cable end of the USB network card, and the network card chip U2 is located in the USB network card. The USB plug USB1 of the USB network card is inserted into the USB socket of the virtual reality headset, and the network cable end of the USB network card is connected to the PC through the network cable. This connection enables the virtual reality headset to have network connectivity. The theoretical transmission distance of the network cable can reach 100m, and in actual tests, this method can stably stream at a distance of 20m, meeting the long-distance streaming requirements of virtual reality devices. At the same time, based on the above circuit setup, the original USB interface of the virtual reality headset can be used to extend the transmission distance without redesigning the headset.

[0074] Specifically, multimedia data from a PC can be streamed into a virtual reality headset. Games or videos running on the PC can be compressed into H.264 or H.265 encoded data by streaming software. This data is then streamed to the network card chip U2 of the USB network card via the network cable terminal circuit 101. The network card chip U2 then converts the received network data into USB data via the network cable terminal circuit 101 and streams it into the virtual reality headset via the USB terminal circuit 102. Finally, the virtual reality headset decodes and displays the data to the player, thus enabling multimedia data from a PC to be streamed into the virtual reality headset.

[0075] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0076] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0077] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A network card interface circuit for a virtual reality device, characterized in that, include: Network cable end circuit and USB end circuit; The network cable terminal circuit includes a network interface card (NIC) chip, a network transformer, and a network cable interface; wherein, the NIC chip is connected to the network cable interface through the network transformer; The USB terminal circuit includes the network card chip and the USB plug; wherein the network card chip is connected to the USB plug; The network interface card (NIC) chip includes a first NIC chip pin, a second NIC chip pin, a fourth NIC chip pin, a fifth NIC chip pin, a sixth NIC chip pin, a seventh NIC chip pin, a ninth NIC chip pin, and a tenth NIC chip pin. The network cable interface includes a first network cable interface pin, a second network cable interface pin, a third network cable interface pin, a fourth network cable interface pin, a fifth network cable interface pin, a sixth network cable interface pin, a seventh network cable interface pin, and an eighth network cable interface pin; Specifically, the first network interface card (NIC) chip pin is connected to the first network cable interface pin via the network transformer; the second NIC chip pin is connected to the second network cable interface pin via the network transformer; the fourth NIC chip pin is connected to the third network cable interface pin via the network transformer; the fifth NIC chip pin is connected to the fourth network cable interface pin via the network transformer; the sixth NIC chip pin is connected to the fifth network cable interface pin via the network transformer; the seventh NIC chip pin is connected to the sixth network cable interface pin via the network transformer; the ninth NIC chip pin is connected to the seventh network cable interface pin via the network transformer; and the tenth NIC chip pin is connected to the eighth network cable interface pin via the network transformer. The network transformer includes a second transformer pin, a third transformer pin, a fifth transformer pin, a sixth transformer pin, an eighth transformer pin, a ninth transformer pin, an eleventh transformer pin, a twelfth transformer pin, a thirteenth transformer pin, a fourteenth transformer pin, a sixteenth transformer pin, a seventeenth transformer pin, a nineteenth transformer pin, a twentieth transformer pin, a twenty-second transformer pin, and a twenty-third transformer pin. Wherein, the first network interface card (NIC) chip pin is connected to the second transformer pin, the second NIC chip pin is connected to the third transformer pin, the fourth NIC chip pin is connected to the fifth transformer pin, the fifth NIC chip pin is connected to the sixth transformer pin, the sixth NIC chip pin is connected to the eighth transformer pin, the seventh NIC chip pin is connected to the ninth transformer pin, the ninth NIC chip pin is connected to the eleventh transformer pin, and the tenth NIC chip pin is connected to the twelfth transformer pin; The thirteenth transformer pin is connected to the eighth network cable interface pin, the fourteenth transformer pin is connected to the seventh network cable interface pin, the sixteenth transformer pin is connected to the sixth network cable interface pin, the seventeenth transformer pin is connected to the fifth network cable interface pin, the nineteenth transformer pin is connected to the fourth network cable interface pin, the twentieth transformer pin is connected to the third network cable interface pin, the twenty-second transformer pin is connected to the second network cable interface pin, and the twenty-third transformer pin is connected to the first network cable interface pin.

2. The network card interface circuit for a virtual reality device according to claim 1, characterized in that, The network transformer includes the fifteenth transformer pin, the eighteenth transformer pin, the twenty-first transformer pin, and the twenty-fourth transformer pin; The network cable interface includes a ninth network cable interface pin and a tenth network cable interface pin; The network cable terminal circuit also includes a first resistor, a second resistor, a fourth resistor, a fifth resistor, a third capacitor, a fifth capacitor, and a sixth capacitor; Specifically, the 24th transformer pin is connected to the first end of the first resistor, the 21st transformer pin is connected to the first end of the second resistor, the 18th transformer pin is connected to the first end of the fourth resistor, the 15th transformer pin is connected to the first end of the fifth resistor, the second ends of the first resistor, the second ends of the second resistor, the second ends of the fourth resistor, and the second ends of the fifth resistor are respectively connected to the first end of the third capacitor, the second end of the third capacitor is respectively connected to the first ends of the fifth capacitor and the sixth capacitor, the ninth network cable interface pin and the tenth network cable interface pin are respectively connected to the first ends of the fifth capacitor and the sixth capacitor, and the second ends of the fifth capacitor and the sixth capacitor are respectively grounded.

3. The network card interface circuit for a virtual reality device according to claim 1, characterized in that, The USB terminal circuit also includes a seventh capacitor and an eighth capacitor; The network interface card (NIC) chip includes the twelfth, thirteenth, fifteenth, sixteenth, seventeenth, and eighteenth NIC chip pins. The USB plug includes a second USB pin, a third USB pin, a sixth USB pin, a seventh USB pin, a tenth USB pin, and an eleventh USB pin; Specifically, the twelfth network card chip pin is connected to the first end of the seventh capacitor, the second end of the seventh capacitor is connected to the tenth USB pin, the thirteenth network card chip pin is connected to the first end of the eighth capacitor, the second end of the eighth capacitor is connected to the eleventh USB pin, the fifteenth network card chip pin is connected to the third USB pin, the sixteenth network card chip pin is connected to the second USB pin, the seventeenth network card chip pin is connected to the seventh USB pin, and the eighteenth network card chip pin is connected to the sixth USB pin.

4. The network card interface circuit for a virtual reality device according to claim 1, characterized in that, The USB plug also includes a first USB pin and a ninth USB pin; The ninth USB pin is connected to the first power supply circuit, and the first USB pin is grounded.

5. The network card interface circuit for a virtual reality device according to claim 4, characterized in that, The first power supply circuit includes a power input terminal, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a power supply voltage, and a register power supply voltage; The power input terminal is connected to the first terminal of the ninth capacitor, the first terminal of the power supply voltage, and the first terminal of the register power supply voltage, respectively. The second terminal of the register power supply voltage is connected to the first terminal of the tenth capacitor and the first terminal of the eleventh capacitor, respectively; the second terminal of the register power supply voltage is connected to the first terminal of the twelfth capacitor and the first terminal of the thirteenth capacitor, respectively. The second terminal of the ninth capacitor, the second terminal of the tenth capacitor, the second terminal of the eleventh capacitor, the second terminal of the twelfth capacitor, and the second terminal of the thirteenth capacitor are grounded.

6. The network card interface circuit for a virtual reality device according to claim 1, characterized in that, Also includes: Data transceiver circuit; The data transceiver circuit includes a network card chip, a ninth resistor, a tenth resistor, a first LED, and a second LED. The network interface card (NIC) chip includes a 30th NIC chip pin and a 32nd NIC chip pin.

7. The network card interface circuit for a virtual reality device according to claim 6, characterized in that, The thirtieth network card chip pin is connected to the first end of the tenth resistor, the second end of the tenth resistor is connected to the positive terminal of the second LED, and the negative terminal of the second LED is grounded. The thirty-second network card chip pin is connected to the first end of the ninth resistor, the second end of the ninth resistor is connected to the positive terminal of the first LED, and the negative terminal of the first LED is grounded.

8. The network card interface circuit for a virtual reality device according to claim 1, characterized in that, The network cable interface is connected to the terminal device via a network cable, and the USB plug is connected to the virtual reality device.

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