Semiconductor device

Abstract

A semiconductor device includes a plurality of dielectric structures thereon, the plurality of dielectric structures including a set of isolated long dielectric structures and a set of dense short dielectric structures. Each dielectric structure includes: a dielectric volume; a first dielectric spacer and a second dielectric spacer in direct contact with opposing lateral sides of the dielectric volume; a first continuous etch stop layer in direct contact with a side of the first dielectric spacer opposite the side of the dielectric volume; and a second continuous etch stop layer in direct contact with a side of the second dielectric spacer opposite the side of the dielectric volume. A depth load of the plurality of dielectric structures is + / -60 nanometers.

Description

Technical Field

[0001] This disclosure relates to deep loading of semiconductor devices and their dielectric structures. Background Technology

[0002] Integrated circuits are formed on semiconductor wafers. Optical lithography patterning uses ultraviolet light to transfer the desired mask pattern onto a photoresist layer on the semiconductor wafer. An etching process is then used to transfer the pattern to a layer beneath the photoresist. This process is repeated multiple times with different patterns to construct different layers on the wafer substrate and create useful devices. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor device includes a plurality of dielectric structures thereon, the plurality of dielectric structures including a set of isolated long dielectric structures and a set of dense short dielectric structures; wherein each dielectric structure includes: a dielectric volume; a first dielectric spacer and a second dielectric spacer directly contacting a plurality of opposing lateral sides of the dielectric volume; a first continuous etch stop layer directly contacting a side of the first dielectric spacer opposite to a side of the dielectric volume; and a second continuous etch stop layer directly contacting a side of the second dielectric spacer opposite to a side of the dielectric volume; wherein a depth load of the plurality of dielectric structures is ±60 nanometers.

[0004] According to some embodiments of this disclosure, a semiconductor device includes a plurality of dielectric structures thereon, the plurality of dielectric structures including a set of isolated long dielectric structures and a set of dense short dielectric structures; wherein each dielectric structure includes: a dielectric volume; a first dielectric spacer and a second dielectric spacer directly contacting a plurality of opposing lateral sides of the dielectric volume; a first continuous etch stop layer directly contacting a side of the first dielectric spacer opposite to a side of the dielectric volume; and a second continuous etch stop layer directly contacting a side of the second dielectric spacer opposite to a side of the dielectric volume; wherein an average critical size of the set of isolated long dielectric structures and an average critical size of the set of dense short dielectric structures are each 20 nanometers or less, and a depth load of the plurality of dielectric structures is ±60 nanometers.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a plurality of dielectric structures thereon, the plurality of dielectric structures including a set of isolated long dielectric structures and a set of dense short dielectric structures; wherein each dielectric structure includes: a dielectric volume; a first dielectric spacer and a second dielectric spacer directly contacting a plurality of opposing lateral sides of the dielectric volume; a first continuous etch stop layer directly contacting a side of the first dielectric spacer opposite to a side of the dielectric volume; and a second continuous etch stop layer directly contacting a side of the second dielectric spacer opposite to a side of the dielectric volume; wherein an average depth of the set of isolated long dielectric structures and an average depth of the set of dense short dielectric structures are each at least 180 nanometers, and a depth load of the plurality of dielectric structures is ±60 nanometers. Attached Figure Description

[0006] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A It is a plan view that describes the difference between isolated trenches and dense trenches;

[0008] Figure 1B It is a planar diagram that generally illustrates an ideal situation where there is zero strain or stress;

[0009] Figure 1C It is a set of planar diagrams illustrating the ideal situation of zero strain or stress in isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches.

[0010] Figure 2A It is a general diagram illustrating the use of compressive stress or pressure to improve the depth load of a CPODE structure;

[0011] Figure 2B It is a set of plan views illustrating the application of compressive stress or pressure in isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches.

[0012] Figure 3A It is a general diagram illustrating the use of tensile stress or tension to improve the depth load of a CPODE structure;

[0013] Figure 3B It is a set of planar diagrams illustrating the use of tensile stress or tension in isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches.

[0014] Figure 4 This is a flowchart illustrating a first method for reducing the depth load of the dielectric structure of a substrate of a semiconductor device according to some embodiments;

[0015] Figures 5A to 5D At the beginning Figure 4 Different views of the substrate previously completed using the method; Figure 5A It is a floor plan; Figure 5B It is along Figure 5A X-axis view of the substrate of line XX; Figure 5C It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 5D It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0016] Figures 6A to 6C These are different views of the substrate after a hard masking layer has been applied; Figure 6A It is along Figure 5A X-axis view of the substrate of line XX; Figure 6B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 6C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0017] Figures 7A to 7C These are different views of the substrate after the patterned layer has been applied; Figure 7A It is along Figure 5A X-axis view of the substrate of line XX; Figure 7B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 7C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0018] Figures 8A to 8C These are different views of the substrate after the hard mask layer has been patterned; Figure 8A It is along Figure 5A X-axis view of the substrate of line XX; Figure 8B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 8C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0019] Figures 9A to 9C These are different views of the substrate after the exposed dummy gate has been removed; Figure 9A It is along Figure 5A X-axis view of the substrate of line XX; Figure 9B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 9C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0020] Figures 10A to 10C These are different views of the substrate after the exposed dummy oxide layer has been removed to obtain isolated volumes; Figure 10A It is along Figure 5A X-axis view of the substrate of line XX; Figure 10B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 10C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0021] Figures 11A to 11C These are different views of the substrate after the exposed portions of the semiconductor fins have been removed to form trenches in the substrate; Figure 11A It is along Figure 5A X-axis view of the substrate of line XX; Figure 11B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 11C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0022] Figures 12A to 12C These are different views of the substrate after the trenches and isolated volumes have been refilled with dielectric material to form an electrically isolated structure; Figure 12A It is along Figure 5A X-axis view of the substrate of line XX;

[0023] Figure 12B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 12C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0024] Figures 13A to 13C These are different views of the substrate after the planarization process; Figure 13A It is along Figure 5A X-axis view of the substrate of line XX; Figure 13B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 13C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0025] Figures 14A to 14C These are different views of the substrate after the exposed dummy gate and sacrificial layer in the semiconductor fins have been removed; Figure 14A It is along Figure 5A X-axis view of the substrate of line XX; Figure 14B It is along Figure 5A Y-axis view of the substrate along line Y1-Y1; Figure 14C It is along Figure 5A Y-axis view of the substrate along line Y2-Y2;

[0026] Figures 15A to 15D This is a different view of the substrate after a gate oxide layer has been deposited on the semiconductor channel and a conductive gate material has been applied to obtain a gate-all-around (GAA) transistor; the transistor is separated by a set of isolated long CPODE structures and a set of dense short CPODE structures; a dummy gate material is used to define the set of short CPODE structures; Figure 15A It is a floor plan; Figure 15B It is along Figure 15A X-axis view of the substrate of line XX; Figure 15C It is along Figure 15A Y-axis view of the substrate along line Y1-Y1; Figure 15D It is along Figure 15A Y-axis view of the substrate along line Y2-Y2;

[0027] Figure 16 It is an enlarged X-axis view showing certain relationships between the dummy gate region, dielectric spacers, and etch stop layer;

[0028] Figure 17 This is a line graph showing the CPODE structure measured during the experiments disclosed herein;

[0029] Figure 18 This is an illustration of an example CPODE structure formed according to the method disclosed herein; it shows the bending effect of isolated long trenches and dense short trenches.

[0030]

Explanation of symbols

[0031] 100: First Method

[0032] 102~160: Steps

[0033] 200: Integrated Circuits

[0034] 202:Substrate

[0035] 204: STI layer

[0036] 210: Source / Drain Region

[0037] 212: Dummy gate region

[0038] 218: Internal dielectric spacers

[0039] 220: ILD area

[0040] 224: Dielectric spacer

[0041] 225: Width

[0042] 226:CESL

[0043] 227: Width

[0044] 228: Fictitious oxide layer

[0045] 230: Gate oxide layer

[0046] 240: Trench

[0047] 241: Longitudinal sidewall

[0048] 242: Isolated Volume

[0049] 244: Trench

[0050] 246: First Dielectric Material

[0051] 247: Spacing

[0052] 248: Second dielectric material

[0053] 249: Length

[0054] 250: Gate electrode

[0055] 251: Width

[0056] 253: Width

[0057] 260: Fins

[0058] 268:Wall

[0059] 270: Fin stacking

[0060] 272: Semiconductor Nanosheets

[0061] 274: Sacrifice Layer

[0062] 280: Hard mask layer

[0063] 282: Zone 1

[0064] 284: Second District

[0065] 285: Thickness

[0066] 286: Bottom layer

[0067] 288: Intermediate Layer

[0068] 290: PR layer

[0069] 292: GAA transistor

[0070] 294: Isolated long dielectric structure

[0071] 296: Dense short dielectric structure

[0072] a1~a3: Critical dimensions

[0073] b: Depth Detailed Implementation

[0074] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0075] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0076] The numerical values ​​in the specification and claims of this application should be understood to include the same numerical values ​​when reduced to the same number of significant figures, and numerical values ​​that differ from the stated values ​​by less than the experimental error of conventional measurement techniques used to determine the values ​​as described in this application. All ranges disclosed herein include the stated endpoints.

[0077] The term "about" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "about" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also indicates a range "from 2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0078] This disclosure relates to structures composed of different layers. When the terms "on" or "upon" are used for two different layers (including a substrate), they simply mean that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be in between. For example, all layers of a structure can be considered "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other without any layers in between. Furthermore, when referring to performing process steps on the substrate, this should be interpreted as performing such steps on any layers that may be present on the substrate, depending on the context.

[0079] The term "stress" refers to the force applied to a unit area of ​​material. The term "strain" refers to the change in shape of a material due to the applied force. Note that in this disclosure, these terms may be used interchangeably in some contexts.

[0080] This disclosure relates to methods and systems for reducing the depth load of dielectric structures in electrically isolated adjacent transistors, particularly gate-all-around (GAA) transistors. Continuous poly on diffusion edge (CPODE) structures or patterns are used as electrical insulation or dielectric features on a wafer substrate between transistors. CPODE structures are formed by etching away one or more semiconductor fins and forming trenches in the substrate at the initial location of each fin, followed by filling the trenches with a dielectric material. This provides electrical isolation between adjacent active device regions, such as transistors.

[0081] The term “depth load” as used in this article refers to the difference in etching depth between a set of isolated long trenches / structures and a set of dense short trenches / structures in a CPODE structure. Figure 1A This is a plan view illustrating the meaning of these terms. The left-hand side illustrates the layout of isolated (ISO) trench patterns above the hard mask layer 280. Adjacent trenches are widely spaced. In a specific embodiment, in the isolated trench pattern, the spacing or distance 247 between adjacent trenches 240 is 10 micrometers (10,000 nanometers) or greater. The right-hand side illustrates the layout of dense trench patterns. Adjacent trenches are closely spaced. In a specific embodiment, in the dense trench pattern, the spacing 247 between adjacent trenches is one micrometer (1,000 nanometers) or less, and in a more particular embodiment, about 100 nanometers. The length of the trenches is indicated by reference numeral 249. Short trenches have a length of less than 500 nm, and in some specific embodiments, 150 nm or less. Long trenches have a length of 500 nm or greater, and in some specific embodiments, one micrometer or greater. Figure 1AThe illustration also shows the difference in etched surface area when forming isolated trench patterns compared to dense trench patterns.

[0082] In this regard, it is known that the etching rate varies with the amount of substrate area etched; this is called the loading effect. Specifically, etching a larger surface area results in a lower etching rate compared to etching a smaller surface area. Furthermore, smaller features are etched at lower rates compared to larger features. Therefore, if there is a large range of feature sizes across the etched substrate area, larger features will be etched faster than smaller features. This also affects the resulting etching uniformity. The loading effect is most severe for isolated long trenches. Because… Figure 1A The two sets of trenches / structures have different surface areas and feature dimensions, resulting in etching non-uniformity, which is measured by depth load. Higher uniformity, or in other words, a depth load closer to zero, is desired.

[0083] The method disclosed herein influences depth load by altering the stress applied to the substrate during the etching step that forms the CPODE structure. In this regard, the substrate may warp due to mechanical stress. For example, mechanical stress may arise due to differences in the coefficients of thermal expansion between different layers, or due to inhomogeneous distribution of material on the substrate, which can lead to uneven or unbalanced expansion or contraction. In this disclosure, the composition of the hard mask layer is altered to apply a stress that counteracts the stresses in other layers of the substrate. This provides control over the critical dimension (CD) and depth of the CPODE structure, and thus control over depth load.

[0084] Figure 1B The diagram illustrates an ideal condition where the total strain on the substrate is zero. (Example:) Figure 1B As shown in the cross-sectional view, a hard masking layer 280 exists on the substrate 202. The substrate is planar, or the surface area of ​​the top surface is equal to the surface area of ​​the bottom surface. Figure 1B In the plan view, a hard mask layer 280 and a trench 240 on the substrate are visible. The trench is formed by removing dummy gate material. The trench has a length 249 in the lateral direction. Two dielectric spacers 224 extend in the lateral direction and directly contact the opposite sides of the trench. Two continuous etch stop layers (CESLs) 226 also extend in the lateral direction and directly contact the sides of the dielectric spacers 224 opposite to the trench 240. Two longitudinal sidewalls 241 are present at the opposite ends of the trench 240 and are typically formed of dummy gate material. As shown herein, the width 251 of the trench near the two ends of the longitudinal sidewalls is the same as the width 253 at the center of the trench. Figure 1CThe figure shows the same conditions occurring in isolated long grooves, isolated short grooves, dense long grooves, and dense short grooves, where the width of the grooves does not change between the ends and the center.

[0085] Figures 2A to 2B Generally, the figure shows a concept for controlling the depth load. As Figure 2A shown in the top part of, a hard mask layer 280 exists on the substrate 202. The substrate is shown to have a concave shape, where the surface area of the top surface is larger than the surface area of the bottom surface. The hard mask layer can be made or formed so as to apply compressive stress to contract the surface area of the top surface.

[0086] As Figure 2A shown in the plan view of, the width 251 at the two ends of the groove near the longitudinal sidewalls is larger than the width 253 at the center of the groove. This is because the Young's modulus of the dielectric spacer 224 can be less than the Young's modulus of the longitudinal sidewall 241, can also be less than the Young's modulus of the CESL 226, and can also be less than the Young's modulus of the hard mask layer 280. Therefore, the shape of the groove / dummy gate region is controlled by the material with a higher Young's modulus. In this compressive stress situation, various layers thus bend into the groove. Figure 2B The figure shows the same conditions occurring in isolated long grooves, isolated short grooves, dense long grooves, and dense short grooves.

[0087] In a specific embodiment, the dielectric spacer has a Young's modulus of 75 GPa or less. In a specific embodiment, the CESL has a Young's modulus of about 250 GPa or higher. In a specific embodiment, the material (such as the dummy gate material) used to form the longitudinal sidewall has a Young's modulus of about 140 GPa to about 180 GPa.

[0088] In a specific embodiment, the hard mask layer is formed of silicon nitride (Si x N y , 0 < x, y ≤ 1). In a specific embodiment, the dielectric spacer is made of silicon oxide (SiO y , 0 < y ≤ 1) or silicon carbon oxynitride (SiC x O y N z , 0 < y ≤ 1, 0 ≤ x, z ≤ 1). Regarding the dielectric spacer, a higher O concentration results in a lower Young's modulus, which makes this layer more prone to deformation. In a more particular embodiment, the dielectric spacer material has a (carbon + nitrogen) content of less than 5 mol% to reduce the parasitic capacitance.

[0089] In a specific embodiment, the CESL is also formed of silicon nitride. Its composition can also be varied to alter the stress applied to the trench. In a specific embodiment, a dummy gate material is used to form the longitudinal sidewalls of the trench and is polysilicon. Similarly, materials for other components on the substrate can be selected to tune the degree of deformation and balance this property with other desired characteristics of the semiconductor device. The following table includes information on various materials that may be relevant to this disclosure.

[0090] Table A.

[0091] Material Dielectric constant (k) Young's modulus (E, GPa) use Si 11.7 140～180 Dummy gate SiC 9.7 410 SiN 7～8 280～290 CESL, Hard Mask SiO2 3.9 75 ILD, dielectric spacer SiCON ≤5 ≤75 Dielectric spacers W 405 Metal gate TiN 260～600 Metal gate TiAl 236～270 Metal gate

[0092] Figures 3A to 3B This is generally illustrated as another concept used to control depth load. Figure 3A In the top portion, the substrate is illustrated as having a convex shape, wherein the surface area of ​​the top surface is smaller than the surface area of ​​the bottom surface. A hard masking layer is formed or fabricated to apply tensile stress, thereby increasing the surface area of ​​the top surface.

[0093] like Figure 3A As shown in the plan view, the width 251 at the two ends of the trench near the longitudinal sidewalls is smaller than the width 253 at the center of the trench. Again, this is because the shape of the trench / dummy gate region is controlled by a material with a high Young's modulus, namely, the hard masking layer 280. Under this compressive stress, the various layers are therefore "pulled" away from the trench. Figure 3B The diagram shows the same conditions appearing in isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches.

[0094] Figure 4 This is a flowchart illustrating a first method 100 for reducing the depth load of dielectric structures on a substrate according to some embodiments. The method can be used to electrically isolate transistors disposed on a substrate at different densities (i.e., transistors per unit area). Figures 5A to 15C The diagrams illustrate the various steps of the method, and these diagrams are discussed together. These diagrams provide different views for better understanding.

[0095] It should be noted that in the following discussion, some conventional steps are not described in full every time, and should be referred to only for their results. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching, but the following discussion may refer only to patterning a given layer. For completeness, some of these different steps are now described.

[0096] Generally, photoresist layers can be applied, for example, by spin coating, or by spraying, roller coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include a vacuum chuck for holding the substrate in place. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to spread the resist evenly from the center of the substrate to its periphery. The rotation speed of the platform is then fixed, which controls the final thickness of the photoresist layer.

[0097] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate or oven, or similar equipment. As a result, a photoresist layer is formed on the substrate.

[0098] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the desired masking pattern. In a specific embodiment, EUV light with a wavelength of approximately 13.5 nm is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation, while other portions are not. This exposure causes some portions of the photoresist to become soluble in the developer, while other portions remain insoluble in the developer.

[0099] Following exposure to radiation, an additional photoresist baking step (post-exposure baking, or PEB) may occur. For example, this may help release acid-leaking groups (ALGs) or other molecules that are important in chemically amplified photoresists.

[0100] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. During the development step, the soluble portions of the photoresist layer are dissolved and washed away, leaving the photoresist pattern. A common example of a developer is aqueous tetramethylammonium hydroxide (TMAH). Other developers may include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate or propylene glycol monomethyl ether acetate, n-amyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" may be performed to stabilize the photoresist pattern after development for optimal performance in subsequent steps.

[0101] Continuing, the portion of the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. The patterned photoresist layer can be removed after use, for example, using various solvents such as N-methylpyrrolidone (NMP) or alkaline media or other stripping agents at elevated temperatures, or by dry etching using oxygen plasma.

[0102] Generally, any etching step used herein may be performed using wet etching, dry etching, or plasma etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or combinations thereof, as appropriate. Etching can be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), fluorinated carbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), or similar substances, or combinations thereof in different proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4, and / or H2.

[0103] Planarization can be performed to obtain a flat surface. For example, planarization can be performed using a chemical mechanical polishing (CMP) process. Generally, CMP is performed using a rotating stage with an attached polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier rotate, which creates mechanical and chemical effects on the surface of the wafer substrate and / or its top layers, thereby removing unwanted material and forming a highly flat surface. A post-CMP cleaning step is then performed using a rotating scrubber brush along with a cleaning solution to clean one or both sides of the wafer substrate.

[0104] Finally, a cleaning step, such as wet cleaning, can be performed between the various processing steps. The cleaning solution will depend on the etching formulation and the exposed layers. Examples of cleaning solutions may include deionized water, diluted HF, and other solutions.

[0105] The methods and systems disclosed herein include several different dielectric structures. Such dielectric structures can generally be made from any suitable combination of dielectric materials, although the properties of any specific layer can be further defined. Examples of dielectric materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon oxynitride (SiO2). x N y ), Hafnium oxynitride (HfO) x N y ) or zirconium oxynitride (ZrO) x N y ), or hafnium silicate (HfSi) x O y ) or zirconium silicate (ZrSi) x O y ) or silicon carbide (SiC) x O y N z Alternatively, it can be hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicone glass (FSG), silicon-free glass (USG), high-stress silicon-free glass (HSUSG), and borosilicate glass (BSG).

[0106] Continue, then Figures 5A to 5D This shows that before performing method steps, in such... Figure 4 The initial state of the partially completed integrated circuit 200 on the wafer substrate 202 received in step 102. First refer to Figure 5A The plan view shows multiple long dummy gate regions 212 or long dummy gate regions extending in the lateral direction. A pair of low-k dielectric spacers 224 and a continuous etch stop layer (CESL) 226 are located between each pair of dummy gate regions 212. Dashed lines indicate the location of semiconductor fins 260 below the dummy gate regions 212, dielectric spacers 224, and CESL 226. As shown in this example, there are four semiconductor fins extending in the longitudinal direction.

[0107] Figure 5C and Figure 5D Two Y-axis views are provided via lines Y1-Y1 and Y2-Y2. These views will illustrate the difference between isolated long trenches and dense short trenches, which will become extremely clear.

[0108] Now for reference Figure 5BThe diagram provides an X-axis cross-sectional view. An integrated circuit is built upon substrate 202. The substrate is typically a wafer made of a semiconductor material. Such materials may include silicon, for example, in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In a specific embodiment, the wafer substrate is silicon.

[0109] Continue, as Figure 5C and Figure 5D Most readily visible in the Y-axis view is a shallow trench isolation (STI) region or layer 204 above the substrate 202 surrounding the semiconductor fins. The dielectric material in the STI layer is typically silicon dioxide, although other dielectric materials may also be used, such as undoped polysilicon, silicon oxide (e.g., SiO2), silicon nitride, silicon oxynitride, fluorosilicone glass, or other low-k dielectric materials. Deposition can be performed using physical vapor deposition (PVD) or chemical vapor deposition (CVD) or spin-on processes known in the art, or it may be grown via oxidation. The STI layer is typically deposited prior to the individual layers in the semiconductor fins 260. If desired, the dielectric material can be deposited above the substrate level and then recessed down to the desired height.

[0110] Each fin comprises a fin stack 270 formed by alternating layers of semiconductor nanosheets 272 and sacrificial layers 274. These layers can be fabricated using CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), or any other suitable process. Each semiconductor nanosheet layer can be, for example, silicon or other materials suitable for use as a substrate. The sacrificial layer 274 can be made of any suitable material, which can be selectively etched compared to other materials to be used in the transistor, such as, for example, SiGe.

[0111] Source / drain regions 210 are also present within the fins. In specific embodiments, these regions are formed of epitaxial silicon using CVD, MOCVD, MBE, LPE, VPE, UHVCVD, or similar methods. These regions may also be doped with suitable dopants, such as boron, gallium, or indium; or phosphorus or arsenic. Internal dielectric spacers 218 separate the source / drain regions from the sacrificial layer 274 (which will eventually be removed and filled with a conductive gate material).

[0112] Continuing, the interlayer dielectric (ILD) region 220, the dummy gate region 212, and CESL 226 are alternately placed on top of the substrate. For example... Figure 5B As shown, the ILD region 220 is aligned with the source / drain region 210 and placed above the source / drain region 210.

[0113] The ILD region electrically separates the source / drain region from the final gate terminal or gate electrode. The ILD region can be formed of any dielectric material and does not need to be a high-k dielectric. Suitable dielectrics may include silicon nitride, silicon oxide (e.g., SiO2), phosphorus silicate glass (PSG), fluorosilicone glass (FSG), silicon-free glass (USG), high-stress silicon-free glass (HSUSG), borosilicate glass (BSG), or any combination thereof. The ILD can be deposited using any suitable method, such as CVD. The ILD region 220 is surrounded on three sides (top and sides) by CESL 226. CESL is typically made of silicon nitride.

[0114] A dummy gate region 212 is located between ILD regions. The dummy gate region is typically formed of polysilicon and is used to define the shape of the final gate terminal or gate electrode. The vertical surface of the dummy gate region 212 is covered with a low-k dielectric spacer 224 having a dielectric constant equal to or less than that of silicon nitride (~7). Suitable materials may include various nitrides or oxides. A CPODE structure is typically formed at the location of the dummy gate region.

[0115] A dummy oxide layer 228 is located between the fin portion and the dummy gate region 212. Figure 5B This is visible on the top of fin 260. (As shown) Figure 5C and Figure 5D As shown, a dummy oxide layer exists on the top and sides of each semiconductor fin 260, as well as on the STI layer 204.

[0116] A partially completed integrated circuit 200 on a wafer substrate 202 can be fabricated by first etching the substrate to define the STI layer 204. Next, a fin stack 270 is formed by depositing alternating layers of semiconductor nanosheets 272 and sacrificial layers 274 on the substrate. A hard mask is applied and the fin stack is etched to obtain semiconductor fins having fin portions in their desired locations. Anisotropic etching of the sacrificial layers is performed, forming internal dielectric spacers 218 at these etch locations on the exposed outer walls of the fin stack. The fin stack is then etched to create trenches at desired locations for the source / drain regions 210. Another anisotropic etching is performed on the newly exposed surfaces of the sacrificial layers within these trenches, again forming internal dielectric spacers 218 at the new etch locations. A dummy oxide layer 228 is then formed on the exposed silicon surface. Epitaxial silicon is then deposited into the trenches to form the source / drain regions 210. A dummy gate material, such as polysilicon, is then deposited over the substrate. Another photomask is applied and a dummy gate material is etched to create a trench over the source / drain regions and form a dummy gate region 212. A low-k dielectric spacer 224 is then applied to the exposed vertical surface of the dummy gate region. An ILD region 220 is then formed over the source / drain regions. CESL 226 is then applied over the three exposed sides of the ILD region.

[0117] Now for reference Figure 4 In optional step 104 (not shown), the warpage of substrate 202 is measured. Warpage can be measured using known metrological equipment and methods, such as triaxial strain gauges. The degree of warpage is typically measured in length (micrometers), where zero indicates no warpage (i.e., flatness) and higher values ​​are undesirable. Warpage is generally measured as the difference from the center of the substrate (defined as zero). Note that the acceptable amount of warpage generally remains constant and is independent of grain size (i.e., length and width). The measured value can be used to determine what kind of stress (compressive or tensile) the hard mask layer should apply to the substrate and to determine the stress to be applied.

[0118] Now for reference Figure 4 Step 105, as follows Figures 6A to 6C As shown, a hard mask layer 280 with a thickness of 285 is applied over the dummy gate region 212 and the ILD region 220. In some embodiments, the thickness 285 of the hard mask layer may range from about 600 angstroms to up to about 900 nanometers. The hard mask layer is formed to apply a determined stress and a determined strain force.

[0119] By altering the growth conditions for forming the hard masking layer, the stress (i.e., compressive or tensile stress) applied by the hard masking layer can be changed. For example, the stress can be varied based on deposition temperature, crystallization state, vacancies, grain boundaries, lattice quality (i.e., impurity level), lattice mismatch, and layer thickness. Generally, compressive stress decreases CD, while tensile stress increases CD.

[0120] In a specific embodiment, the hard mask layer is formed of silicon nitride (Si x N y , where 0 < x, y ≤ 1). The silicon nitride can be deposited using ALD (for high aspect ratio trench filling) or CVD. The range of common growth temperatures for silicon nitride is from 200°C to 800°C. The silicon precursors for deposition can include silane and halosilanes. Examples can include but are not limited to tetraethyl orthosilicate (TEOS), trimethylsilane, tetramethylsilane, hexachlorodisilane (HCDS), iodide silane, and other chlorosilanes. The nitrogen precursors for deposition can include but are not limited to ammonia (NH3), N2, and N2O. To promote the dissociation of the precursors, a plasma source such as ICP (inductively coupled plasma) or CCP (capacitively coupled plasma) can be used. To better control the dissociation rate of the precursors and the viscosity of the precursors flowing to the wafer substrate, and to promote dissociation or reduce viscosity, other gases such as argon, hydrogen, or nitrogen can also be included.

[0121] The stress of the hard mask layer, especially when it is made of silicon nitride (SiN), can be tuned / controlled / changed by: (1) changing the deposition or growth temperature to control the degree of thermal expansion of the resulting SiN layer; (2) using different precursors to change the crystalline quality of the resulting layer; (3) changing the dissociation mode of the precursors to control the material that starts to grow the SiN layer on the substrate, thereby tuning the quality of the interface between the substrate and the SiN layer.

[0122] Generally, a higher growth temperature will result in the formation of a layer with greater tensile stress. For example, by raising the growth temperature to the range of 400°C to 600°C, for a SiN layer with a thickness of about 200 nm to about 300 nm, the stress of the SiN layer can increase by 3.2 MPa / °C.

[0123] By reducing the impurity content in the SiN layer, a greater tensile stress can also be exerted by the SiN layer. This can be achieved, for example, by using a plasma source or including gases such as argon or hydrogen to increase the dissociation rate of the precursors.

[0124] In Figure 4 optional step 106 (not shown), the warping of the substrate 202 can be measured. This specific step may be useful in a continuous production process to measure the warping after the SiN layer has been applied and provide feedback to the tool performing the hard mask deposition step 105, so that the recipe of the hard mask layer deposited on subsequent substrates can be better tuned to obtain the desired effect.

[0125] As Figures 7A to 7C shown, in Figure 4In optional step 108, a bottom layer 286 and / or an intermediate layer 288 may be applied over the hard mask layer 280. Spin-on-carbon (SoC) materials are suitable for the bottom layer. Spin-on glass materials are typically suitable for the intermediate layer. The combination of the hard mask layer, bottom layer, and intermediate layer creates a three-layer patterned etching system, which allows for better control over subsequent etching. Then, in Figure 4 In step 110, a photoresist (PR) layer 290 is applied and patterned. In a specific embodiment, extreme ultraviolet (EUV) light with a wavelength of approximately 13.5 nm is used for patterning, as this allows for smaller feature sizes. If no bottom and intermediate layers are used, the PR layer is applied directly to the hard mask layer 280.

[0126] The resulting structure is as follows Figures 7A to 7C As shown. Figure 7A As shown in this example, PR layer 290 is patterned to expose the first region 282, that is, along... Figure 5A Lines Y1-Y1 (only one such dummy gate region is shown) are spaced apart by at least two large dummy gate regions 212. The PR layer is also patterned to expose the second region 284, i.e., along... Figure 5A At least two dummy gate regions 212 that are closely spaced apart by lines Y2-Y2.

[0127] like Figure 7B As shown, along line Y1-Y1, the entire volume between the two outer semiconductor fins 260 is exposed. Figure 7C As shown, along line Y2-Y2, the semiconductor fins remain covered by a hard masking layer between the two exposed fins. As a result, the PR layer will define a set of isolated long trenches in the first region and a set of dense short trenches in the second region. These trenches will... Figure 5A The long dummy gate region is defined above it.

[0128] Next, in Figure 4 In step 115, etching is performed to etch through the hard mask layer 280 and transfer the pattern to the hard mask. This may be referred to as a Hard Mask Open (HMO). When the intermediate layer 288 and the bottom layer 286 are present, etching is first performed through both using an appropriate etchant. After removing the bottom layer, intermediate layer, and PR layer, the resulting structure is as follows: Figures 8A to 8C As shown, the hard mask layer is therefore patterned to define a set of isolated long CPODE trenches in one region and another set of dense short CPODE trenches in another region.

[0129] Next, in Figure 4In step 120, the exposed dummy gate region is removed by etching. When the dummy gate region is formed of polysilicon, suitable etchants may include BCl3, Cl2, SiCl4, HCl, O2, HBr, SF6, and / or NF3 in appropriate combinations and proportions. The resulting structure is as follows. Figures 9A to 9C As shown. Figure 9B and Figure 9C As shown, the removal of each dummy gate region exposes three sides of the semiconductor fin 260 beneath that dummy gate region. The empty dummy gate region may also be referred to herein as an isolated volume 242. [Reference Return] Figure 2A It should be noted that each isolated volume is supported by a dummy gate material that acts as the longitudinal sidewall 241.

[0130] It should also be noted that, Figure 9C In the second region shown, an unexposed semiconductor fin lies between two isolated volumes 242, and some of the dummy gate material (such as polysilicon) is not etched away but remains. This material will act as walls 268, separating the long dummy gate region into multiple short isolated volumes 242. This will create short trenches in the second region, as will be seen later. (Reference Return) Figure 2A The dielectric wall can be considered as one of the longitudinal sidewalls 241 of each short trench.

[0131] Next, in Figure 4 In step 125, the exposed dummy oxide is removed from the semiconductor fins and STI layer. Figures 10A to 10C The resulting structure is shown. The two outer semiconductor fins are unaffected because they are protected by a hard masking layer 280.

[0132] Next, in Figure 4 In step 130, etching is performed to remove the exposed semiconductor fin portions and form trenches 244 in the substrate. In a specific embodiment, etching is performed via an HBr / Cl2-based plasma containing O2 or CO2 in a plasma tool. The etching process may also include pumping / Ar rinsing / SiO passivation (using a SiCl4 / O2 precursor) steps.

[0133] Tools equipped with ICP, resonant antennas, or ECR coils that enable high-density plasma generation can also be used for etching. Common pressure and temperature ranges for the process are approximately 0.1 mTorr to approximately 200 mTorr and approximately 10°C to approximately 200°C, respectively. For ICP and resonant coils, RF power generators can be operated to provide source power in the range of approximately 0 W to approximately 2500 W to form plasma. For ECR plasma generators, source power is typically in the range of approximately 200 W to approximately 1200 W. To facilitate directional etching by accelerating ions in the plasma, the RF bias power to the substrate can range from approximately 0 W to approximately 2000 W. Plasma pulse techniques used for source or bias power typically have a load ratio between 5% and 95% and are also commonly used to achieve an "optimal point" balancing CD and depth.

[0134] Figures 11A to 11C Display the resulting structure. For example... Figure 11A As shown, there is a groove 244 isolated in the first region 282 on the left-hand side, while there are two closely spaced or densely packed grooves 244 in the second region 284 on the right-hand side. The combination of the isolated volume 242 and the groove 244 can also be referred to as a CPODE groove.

[0135] refer to Figure 11A It should be noted that the etchant used for the semiconductor nanosheet 272 and the sacrificial layer 274 will not etch the internal dielectric spacers 218. Therefore, a protective layer formed of epitaxial silicon (which can be etched by the same etchant used for the semiconductor nanosheet) exists between the trench and the source / drain regions 210. Figure 11B and Figure 11C As shown, a portion of the STI layer 204 can also be etched away along with the semiconductor fin portion. In other words, the isolated volume 242 can extend into the STI layer.

[0136] Next, in Figure 4 In step 135, the CPODE trenches (isolated volumes 242 and trenches 244) are filled (or refilled) with at least one dielectric material to form a CPODE structure 240 in the first region 282 and the second region 284. Figures 12A to 12C As shown in the structure, the walls of the trench and the isolated volumes are lined with a first dielectric material 246. This can be done, for example, via ALD. In some embodiments, the first dielectric material is an oxide, such as silicon oxide. The trench and isolated volumes are then filled with a different second dielectric material 248. This can be performed by deposition, as shown herein. In some embodiments, the second dielectric material is a nitride, such as silicon nitride. (Reference) Figure 12A In the first region 282, the CPODE structure is isolated, while in the second region 284, the CPOED structure is dense. Each CPODE structure also electrically isolates the source / drain region on one side from the source / drain region on the other side. For example... Figure 12C As shown, wall 268 can be considered as one of the longitudinal sidewalls in a dense short trench. As a result, a set of isolated long dielectric structures and a set of dense short dielectric structures are formed.

[0137] exist Figure 4 In optional step 136 (not shown), the warpage of substrate 202 can be measured. Similarly, this specific step may be useful in continuous manufacturing processes to measure substrate warpage, including the effect of the CPODE structure on the final warpage. This information can provide feedback to the tools performing the hard mask deposition step 105, allowing for better tuning of the hard mask layer formulation deposited on subsequent substrates to achieve the desired effect.

[0138] Continue, then Figure 4 In step 140, the substrate is planarized to remove overfilled dielectric material and hard masking layer 280. The resulting structure is as follows: Figures 13A to 13C As shown. The remaining dummy gate regions 212 in the first region 282 and the second region 284 are now exposed. For example, the primary dummy gate 214 in the first region is exposed, as is the secondary dummy gate 216 in the second region.

[0139] Next, in Figure 4 In step 145, dummy gate regions, such as the main dummy gate 214 and the secondary dummy gate 216, are removed. Any remaining dummy oxide 228 (see...) Figure 13B and Figure 13C The sacrificial layer 274 is also removed. Next, in step 150, the sacrificial layer 274 in the semiconductor fin is removed. These two steps are typically performed by etching. It should be noted that the sacrificial layer is removed after the CPODE structure is formed. The resulting structure is as follows: Figures 14A to 14C As shown. The spaces remaining after removing the dummy gate material are referred to as the gate volume. (See reference...) Figure 14B and Figure 14C The semiconductor nanosheet 272 consists of adjacent source / drain regions 210 (in Figure 14A (Visible in the middle) support, also known as a semiconductor channel. (Reference) Figure 14C Wall 268 has been removed and no longer exists.

[0140] Next, in Figure 4 In step 155, such as Figures 15A to 15DAs shown, a gate oxide layer 230 is applied to the semiconductor nanosheet / channel 272. This can be accomplished, for example, using an ALD. Next, in step 160, a conductive gate material is applied to fill the gate volume and form the gate electrode 250. Any suitable conductive material can be used. In a specific embodiment, metals such as W, TiN, TiAl, Pt, Co, Rh, Pd, Ti, Ta, and the like are used. Thus, a gate-all-around (GAA) transistor 292 is formed in both the first region 282 and the second region 284.

[0141] like Figure 15A As shown, the first region 282 can be considered as comprising a group of isolated long dielectric structures (e.g., CPODEs) 294. Only one isolated long dielectric structure is illustrated in the first region. The second region 284 can be considered as comprising a group of dense short dielectric structures 296. Four dense short dielectric structures are illustrated in a 2x2 array.

[0142] like Figure 15B As shown, the first region 282 has five source / drain regions 210 and four gates 250, and therefore can be considered to have four transistors. Conversely, the second region 284 has two source / drain regions 210 and one gate 250, and therefore can be considered to have one transistor.

[0143] As previously stated, depth load is the difference between the etch depth of a CPODE structure in a set of isolated long trenches / structures and the etch depth of a CPODE structure in a set of dense short trenches / structures. In short, depth load is ((isolated long trench depth) minus (dense short trench depth)). Therefore, depth load can be positive or negative, and ideally zero. Using the methods disclosed herein, in specific embodiments, the depth load of the dielectric structure is within 60 nanometers of zero, i.e., ±60 nanometers. In some more specific embodiments, the depth load of the dielectric structure is ±40 nanometers.

[0144] Furthermore, the average critical size of a set of isolated long dielectric structures can be 20 nanometers or smaller. Similarly, the average critical size of a set of dense short dielectric structures can be 20 nanometers or smaller. The average depth of a set of isolated long dielectric structures can be at least 180 nanometers. The average depth of a set of dense short dielectric structures can also be at least 180 nanometers.

[0145] Figure 16This is an enlarged X-axis view showing a dummy gate region 212 with two dielectric spacers 224 and two CESLs 226 on either side. Each dielectric spacer has a width 225. The side of each CESL (on the side of the ILD 220) has a width 227. In a specific embodiment, the ratio of the dielectric spacer width 225 to the CESL width 227 can be about 8 / 3 or higher. In this respect, a higher ratio results in lower parasitic capacitance.

[0146] As described above, after forming the CPODE structure, the sacrificial layer is removed and the gate electrode is formed. This means that the CPODE structure is formed during the front-end-of-line (FEOL) process, or in other words, the CPODE structure is formed before the gate electrode material is applied to form the finished transistor. However, the method disclosed herein can also be practiced in the middle-end-of-line (MEOL) process after gate deposition and transistor formation.

[0147] Additional processing steps can be performed to obtain a semiconductor device containing a CPODE structure with reduced depth load. The semiconductor device can be used in a variety of applications, such as BCD (Bipolar CMOS DMOS) circuits for driving discrete high-voltage components; drivers for LCD, OLED, AMOLED, or QLED display panels; image sensors for use in systems such as mobile phones and facial recognition systems, or motion sensors for automotive applications, security applications, energy efficiency, etc.; power management devices for controlling the flow and direction of electrical power; and / or image signal processors (ISPs).

[0148] The method disclosed herein improves the depth loading of CPODE structures by reducing the depth gap between isolated dielectric structures and dense dielectric structures. This reduces leakage current and allows for consistent performance.

[0149] Therefore, this disclosure relates, in various embodiments, to a method for reducing the depth load of a dielectric structure on a substrate. A substrate is received, the substrate comprising a plurality of long dummy gate regions extending in a lateral direction. Each dummy gate region has a first dielectric spacer and a second dielectric spacer extending in the lateral direction and directly contacting opposite sides of the dummy gate region. A first continuous etch stop layer extends in the lateral direction and directly contacts the side of the first dielectric spacer opposite to the side of the dummy gate region. A second continuous etch stop layer extends in the lateral direction and directly contacts the side of the second dielectric spacer opposite to the side of the dummy gate region. A pressure-applied hard mask layer is formed over the substrate. The hard mask layer is patterned to define a set of isolated long trenches and a set of dense short trenches over the plurality of long dummy gate regions. Etching is performed through the hard mask layer to form a set of isolated long trenches, wherein each long trench includes longitudinal sidewalls of dummy gate material at opposite ends of the trench. Etching is also performed through the hard mask layer to form a set of dense short trenches. Multiple short trenches form a self-growing dummy gate region, wherein each short trench includes longitudinal sidewalls of dummy gate material and dielectric walls separating adjacent short trenches. Each trench is then filled with at least one dielectric material to form a set of isolated long dielectric structures and a set of dense short dielectric structures on a substrate. According to some embodiments of this disclosure, an average critical size of the set of isolated long dielectric structures and an average critical size of the set of dense short dielectric structures are each 20 nanometers or less. According to some embodiments of this disclosure, an average depth of the set of isolated long dielectric structures and an average depth of the set of dense short dielectric structures are each at least 180 nanometers. According to some embodiments of this disclosure, the depth load is ±60 nanometers. According to some embodiments of this disclosure, the first dielectric spacer and the second dielectric spacer have a Young's modulus of 75 GPa or less. According to some embodiments of this disclosure, the first dielectric spacer and the second dielectric spacer are made of silicon oxynitride. According to some embodiments of this disclosure, the (carbon + nitrogen) content of the first dielectric spacer and the second dielectric spacer is each less than 5 moles. According to some embodiments of this disclosure, the first and second etch-stop layers have a Young's modulus of about 250 GPa or greater. According to some embodiments of this disclosure, the first and second etch-stop layers are made of silicon nitride. According to some embodiments of this disclosure, the ratio of the thickness of the first dielectric spacer to the thickness of the first etch-stop layer is about 8 / 3 or higher. According to some embodiments of this disclosure, the dummy gate material has a Young's modulus of about 140 GPa to about 180 GPa. According to some embodiments of this disclosure, the dummy gate material is polysilicon.

[0150] Other methods for reducing the depth load of dielectric structures on a substrate are also disclosed in various embodiments. A substrate is received, comprising a plurality of long dummy gate regions extending in a lateral direction. Each dummy gate region has a first dielectric spacer and a second dielectric spacer extending in the lateral direction and directly contacting opposite sides of the dummy gate region. A first sequential etch stop layer extends in the lateral direction and directly contacts the side of the first dielectric spacer opposite to the side of the dummy gate region. A second sequential etch stop layer extends in the lateral direction and directly contacts the side of the second dielectric spacer opposite to the side of the dummy gate region. A tensile hard mask layer is formed over the substrate. The hard mask layer is patterned to define a set of isolated long trenches and a set of dense short trenches over the plurality of long dummy gate regions. Etching is performed through the hard mask layer to form a set of isolated long trenches, wherein each long trench includes longitudinal sidewalls of dummy gate material at opposite ends of the trench. Etching is also performed through the hard mask layer to form a set of dense short trenches. Multiple short trenches form a self-growing dummy gate region, wherein each short trench includes longitudinal sidewalls of dummy gate material and dielectric walls separating adjacent short trenches. Each trench is then filled with at least one dielectric material to form a set of isolated long dielectric structures and a set of dense short dielectric structures on a substrate. According to some embodiments of this disclosure, an average critical size of the set of isolated long dielectric structures and an average critical size of the set of dense short dielectric structures are each 20 nanometers or less. According to some embodiments of this disclosure, an average depth of the set of isolated long dielectric structures and an average depth of the set of dense short dielectric structures are each at least 180 nanometers. According to some embodiments of this disclosure, the depth load is ±60 nanometers. According to some embodiments of this disclosure, the first dielectric spacer and the second dielectric spacer have a Young's modulus of 75 GPa or less. According to some embodiments of this disclosure, the first etch stop layer and the second etch stop layer have a Young's modulus of about 250 GPa or greater.

[0151] Various embodiments also disclose a semiconductor device comprising a plurality of dielectric structures on a substrate, the plurality of dielectric structures comprising a set of isolated long dielectric structures and a set of dense short dielectric structures. Each dielectric structure comprises: a dielectric volume filled with at least one dielectric material; a first dielectric spacer and a second dielectric spacer directly contacting opposing lateral sides of the dielectric volume; a first continuous etch stop layer directly contacting a side of the first dielectric spacer opposite to a side of a given dielectric volume; a second continuous etch stop layer directly contacting a side of the second dielectric spacer opposite to a side of a given dielectric volume; and a sidewall of dummy gate material directly contacting opposing longitudinal sides of the dielectric volume. The depth load of the semiconductor device is ±60 nm. According to some embodiments of this disclosure, the depth load is ±40 nm. Various embodiments also disclose a semiconductor device comprising a plurality of dielectric structures on a substrate, the plurality of dielectric structures comprising a set of isolated long dielectric structures and a set of dense short dielectric structures. Each dielectric structure includes: a dielectric volume filled with at least one dielectric material; a first dielectric spacer and a second dielectric spacer directly contacting opposing lateral sides of the dielectric volume; a first etch-stop layer directly contacting the side of the first dielectric spacer opposite to the side of the given dielectric volume; a second etch-stop layer directly contacting the side of the second dielectric spacer opposite to the side of the given dielectric volume; and a sidewall of dummy gate material directly contacting opposing longitudinal sides of the dielectric volume. An average critical size for the set of isolated long dielectric structures and an average critical size for the set of dense short dielectric structures are each 20 nanometers or less. The depth load of the semiconductor device is ±60 nanometers. A semiconductor device comprising a plurality of dielectric structures on a substrate, the plurality of dielectric structures including a set of isolated long dielectric structures and a set of dense short dielectric structures, is also disclosed in various embodiments. Each dielectric structure includes: a dielectric volume filled with at least one dielectric material; a first dielectric spacer and a second dielectric spacer directly contacting opposing lateral sides of the dielectric volume; a first etch-stop layer directly contacting the side of the first dielectric spacer opposite to the side of the given dielectric volume; a second etch-stop layer directly contacting the side of the second dielectric spacer opposite to the side of the given dielectric volume; and a sidewall of dummy gate material directly contacting opposing longitudinal sides of the dielectric volume. The average depth of the set of isolated long dielectric structures and the average depth of the set of dense short dielectric structures are each at least 180 nanometers. The depth load of the semiconductor device is ±60 nanometers. According to some embodiments of this disclosure, the ratio of the thickness of the first dielectric spacer to the thickness of the first etch-stop layer is 8 / 3 or higher. According to some embodiments of this disclosure, the ratio of the thickness of the second dielectric spacer to the thickness of the second etch-stop layer is 8 / 3 or higher. According to some embodiments of this disclosure, the average critical dimension of the set of isolated long dielectric structures is 20 nanometers or less.According to some embodiments of this disclosure, the average critical size of the group of dense short dielectric structures is 20 nanometers or less. According to some embodiments of this disclosure, the average depth of the group of isolated long dielectric structures is at least 180 nanometers. According to some embodiments of this disclosure, the average depth of the group of dense short dielectric structures is at least 180 nanometers.

[0152] Various embodiments further disclose alternative methods for reducing the depth load of dielectric structures on a substrate. A substrate is received, comprising a plurality of long dummy gate regions extending in a lateral direction. Each dummy gate region has a first dielectric spacer and a second dielectric spacer extending in the lateral direction and directly contacting opposite sides of the dummy gate region. A first sequential etch stop layer extends in the lateral direction and directly contacts the side of the first dielectric spacer opposite to the side of the dummy gate region. A second sequential etch stop layer extends in the lateral direction and directly contacts the side of the second dielectric spacer opposite to the side of the dummy gate region. A tensile hard mask layer is formed over the substrate. The hard mask layer is patterned to define a set of isolated long trenches and a set of dense long trenches over the plurality of long dummy gate regions. Etching is performed through the hard mask layer to form a set of long trenches, wherein each long trench includes longitudinal sidewalls of dummy gate material at opposite ends of the trench. Each trench is then filled with at least one dielectric material to form a set of isolated long dielectric structures and a set of dense long dielectric structures on the substrate. The hard mask is removed, and the remaining dummy gate region is removed and filled with gate material to form the gate electrode. Then, a cut metal gate (CMG) structure is formed, which extends through the dense long dielectric structure and transforms it into a dense short dielectric structure.

[0153] The methods, systems, and apparatus disclosed herein are further illustrated in the following non-limiting working examples. It should be understood that these examples are intended to be illustrative only, and this disclosure is not intended to limit the materials, conditions, process parameters, and the like described herein.

[0154] Example

[0155] Example 1

[0156] Several wafers were fabricated using the CPODE structure fabricated by applying compressive stress via a hard masking layer according to the method disclosed herein. Isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches were fabricated. The long trenches have a length of 1000 nm, while the short trenches have a length of 150 nm. The isolated (ISO) trenches have a spacing of 10000 nm, while the dense trenches have a spacing of 100 nm.

[0157] Figure 17This is a line graph of an isolated long trench. The semiconductor channel is formed by three nanosheets. The critical dimension (CD) of the CPODE structure at the top nanosheet level is denoted by the letter a1. The critical dimension of the CPODE structure at the middle nanosheet level is denoted by the letter a2. The critical dimension of the CPODE structure at the bottom nanosheet level is denoted by the letter a3. The depth of the CPODE structure is denoted by the letter b.

[0158] The CD (i.e., a1, a2, a3) of the CPODE should not exceed 20 nm; otherwise, the epitaxial silicon (i.e., source / drain) region may be damaged. The depth b of each CPODE structure should be at least 180 nanometers (nm).

[0159] The CPODE structure was measured, and the results are shown in the table below:

[0160] Table B.

[0161]

[0162]

[0163] The CD and depth requirements are met. The depth load calculated as the difference between the ISO long pattern and the dense short pattern is (166-200) = -34nm.

[0164] Example 2

[0165] Several wafers were fabricated using the CPODE structure prepared by applying tensile stress via a hard masking layer according to the method disclosed herein. Isolated long trenches, isolated short trenches, dense long trenches, and dense short trenches were fabricated using the same parameters as in Example 1. Measurements of the CPODE structure were performed, and the results are shown in the following table:

[0166] Table C.

[0167]

[0168]

[0169] The CD and depth requirements are met. The depth load is (228-206) = +22nm.

[0170] Example 3

[0171] Several wafers were fabricated using the CPODE structure fabricated by applying tensile stress via a hard masking layer according to the method disclosed herein. Isolated long trenches and dense short trenches were fabricated using the same parameters as in Example 1. In Examples 1 and 2, SiCON was used to fabricate the dielectric spacers, while in Example 3, silicon oxide was used. Measurements of the CPODE structure were performed, and the results are shown in the following table:

[0172] Table D.

[0173]

[0174] The CD and depth requirements are met. The depth load is (153-210) = -57nm.

[0175] Example 4

[0176] Several wafers were prepared using the CPODE structure fabricated according to the method disclosed herein. Figure 18 This is a line graph of isolated long trenches and densely packed short trenches. The curvature of the CESL or ILD area next to the CPODE trench is measured, and the curvature angle is the difference from the vertical direction. For example... Figure 18 As shown, the curvature angle of the CESL or ILD region in long ISO patterns is greater than 4°. The curvature angle of the CESL or ILD region in dense short patterns is less than 1°.

[0177] In a well-controlled process, batch CD variation can be within + / -2nm, and trench depth can be controlled within + / -5nm.

[0178] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The plurality of dielectric structures thereon include a set of isolated long dielectric structures and a set of dense short dielectric structures; Each dielectric structure contains: Dielectric volume; A first dielectric spacer and a second dielectric spacer directly contact a plurality of opposite lateral sides of the dielectric volume; A first continuous etch stop layer, directly contacting a side of the first dielectric spacer opposite to the side of the dielectric volume; and A second continuous etch stop layer directly contacts a side of the second dielectric spacer opposite to the side of the dielectric volume; The depth of the plurality of dielectric structures is ±60 nanometers.

2. The semiconductor device as claimed in claim 1, characterized in that, The depth of the load is ±40 nanometers.

3. The semiconductor device as claimed in claim 1, characterized in that, The average critical size of this group of isolated long dielectric structures is 20 nanometers or smaller.

4. The semiconductor device as claimed in claim 1, characterized in that, The average critical size of this group of dense short dielectric structures is 20 nanometers or smaller.

5. The semiconductor device as claimed in claim 1, characterized in that, The average depth of this group of isolated long dielectric structures is at least 180 nanometers.

6. The semiconductor device as claimed in claim 1, characterized in that, The average depth of this group of dense short dielectric structures is at least 180 nanometers.

7. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the thickness of the first dielectric spacer to the thickness of the first continuous etch stop layer is 8 / 3 or higher.

8. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the thickness of the second dielectric spacer to the thickness of the second continuous etch stop layer is 8 / 3 or higher.

9. A semiconductor device, characterized in that, Includes a plurality of dielectric structures thereon, the plurality of dielectric structures comprising a set of isolated long dielectric structures and a set of dense short dielectric structures, wherein each dielectric structure comprises: Dielectric volume; A first dielectric spacer and a second dielectric spacer directly contact a plurality of opposite lateral sides of the dielectric volume; A first continuous etch stop layer, directly contacting a side of the first dielectric spacer opposite to the side of the dielectric volume; and A second continuous etch stop layer directly contacts a side of the second dielectric spacer opposite to the side of the dielectric volume; The average critical size of the isolated long dielectric structure and the average critical size of the dense short dielectric structure are both 20 nanometers or smaller. The depth of the plurality of dielectric structures is ±60 nanometers.

10. A semiconductor device, characterized in that, Includes a plurality of dielectric structures thereon, the plurality of dielectric structures comprising a set of isolated long dielectric structures and a set of dense short dielectric structures, wherein each dielectric structure comprises: Dielectric volume; A first dielectric spacer and a second dielectric spacer directly contact multiple opposite lateral sides of the dielectric volume; A first continuous etch stop layer, directly contacting a side of the first dielectric spacer opposite to the side of the dielectric volume; and A second continuous etch stop layer directly contacts a side of the second dielectric spacer opposite to the side of the dielectric volume; The average depth of the isolated long dielectric structure and the average depth of the dense short dielectric structure are each at least 180 nanometers. The depth load of the plurality of dielectric structures is ±60 nanometers.

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