Detection device

Abstract

A detection device comprises a detection unit, a source line, a first bit line and a second bit line. The detection unit comprises an n-type transistor, a p-type transistor and an energy sensing pad. Each of the n-type transistor and the p-type transistor includes a gate electrode, a first source / drain node, and a second source / drain node. The energy sensing pad is coupled to a gate electrode of the n-type transistor and a gate electrode of the p-type transistor. The source line is coupled to a first source / drain node of the n-type transistor and a first source / electrode node of the p-type transistor of the detection unit. The first bit line is coupled with the second source / drain node of the p-type transistor of the detection unit. The second bit line is coupled to the second source / drain node of the n-type transistor of the detection unit.

Description

Technical Field

[0001] This disclosure concerns a detection device. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Technological advancements in semiconductor materials and design have enabled the production of increasingly smaller and more complex circuits. These advancements in materials and design have been made possible by advancements in processing and manufacturing technologies. In the evolution of semiconductors, the size of the smallest reliably achievable component has decreased, while the number of interconnect devices per unit area has increased.

[0003] As the size has decreased, maintaining reliability and yield in patterning processes has become more challenging. In some cases, optical proximity corrections and adjustments to lithography parameters such as process duration, wavelength, focal length, and the intensity of light used can mitigate some defects. However, the current and systems used for material layers in patterned semiconductor wafers are not yet entirely satisfactory. Utility Model Content

[0004] According to some embodiments, the detection device includes an n-type transistor and a p-type transistor; a multilayer interconnect structure located on the n-type transistor and the p-type transistor, wherein the multilayer interconnect structure includes a first conductive feature and a second conductive feature, the first conductive feature being coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; and an energy sensing pad located on the multilayer interconnect structure, wherein the second conductive feature is coupled to the energy sensing pad, a gate electrode of the n-type transistor, and a gate electrode of the p-type transistor.

[0005] According to some embodiments, a detection device includes an n-type transistor and a p-type transistor; a first conductive feature coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; a second conductive feature coupled to a gate electrode of the n-type transistor and a gate electrode of the p-type transistor; and an energy sensing pad coupled to the second conductive feature, wherein an upper surface of the energy sensing pad is higher than an upper surface of the second conductive feature.

[0006] According to some embodiments, a detection device includes at least one detection unit, a source line, a first bit line, and a second bit line. The detection unit includes an n-type transistor, a p-type transistor, and an energy-sensing pad. Each of the n-type transistor and the p-type transistor includes a gate electrode, a first source / drain node, and a second source / drain node. The energy-sensing pad is coupled to the gate electrode of the n-type transistor and the gate electrode of the p-type transistor. The source line is coupled to the first source / drain node of the n-type transistor and the first source / drain node of the p-type transistor of the detection unit. The first bit line is coupled to the second source / drain node of the p-type transistor of the detection unit. The second bit line is coupled to the second source / drain node of the n-type transistor of the detection unit. Attached Figure Description

[0007] The features disclosed herein are best understood when read in conjunction with the accompanying drawings from the following detailed description. Please note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0008] Figure 1A Here is a circuit diagram of a detection device according to some embodiments of this disclosure;

[0009] Figure 1B for Figure 1A A schematic cross-sectional view of the detection unit in the image;

[0010] Figure 1C The layout of a detection device including multiple detection units according to some embodiments of the present disclosure;

[0011] Figure 1D For the detection unit along Figure 1C An illustrative cross-sectional view of line DD in the diagram;

[0012] Figure 2 This is a flowchart of a method for operating a detection unit according to some embodiments of the present disclosure;

[0013] Figure 3 This is a diagram of signal sequences for operating a detection unit according to some embodiments of this disclosure;

[0014] Figure 4A The illustrations are schematic cross-sectional views of an exemplary detection unit under energy exposure operation for EUV / DUV light, according to some embodiments of this disclosure.

[0015] Figure 4B A curve showing the IV characteristics measured via bit lines connected to p-type transistors in an exemplary detection unit before and after energy exposure operations for EUV / DUV light.

[0016] Figure 4C A curve showing the IV characteristics measured via bit lines connected to p-type transistors in an exemplary detection unit before and after energy exposure operations for EUV / DUV light.

[0017] Figure 5A The illustrations are schematic cross-sectional views of an exemplary detection unit under energy exposure operation for an electron beam, according to some embodiments of the present disclosure.

[0018] Figure 5B A curve showing the IV characteristics measured via bit lines connected to p-type transistors in an exemplary detection unit before and after energy exposure operation against an electron beam.

[0019] Figure 6A The illustrations are schematic cross-sectional views of an exemplary detection unit under substance exposure operation to gases, plasmas, and / or ions, according to some embodiments of this disclosure.

[0020] Figure 6B This is a circuit diagram of a gas detection unit according to some embodiments of the present disclosure;

[0021] Figure 6C This is a circuit diagram of a detection unit for detecting ions in a solution according to some embodiments of the present disclosure;

[0022] Figure 7 A block diagram of a detection device according to some embodiments of this disclosure;

[0023] Figure 8 This is a diagram of signal sequences for operating a detection unit according to some embodiments of this disclosure.

[0024]

Explanation of symbols

[0025] 10: Detection device

[0026] 12: Line Decoder

[0027] 14P, 14N: Column decoders

[0028] 16P, 16N: Multiplexers

[0029] 18S, 18P, 18N: Address buffers

[0030] 100: Detection Unit

[0031] 110:Substrate

[0032] 120: Gate structure

[0033] 122: Gate Dielectric

[0034] 124: Gate electrode

[0035] 130: Interlayer Dielectric (ILD) Layer

[0036] 140B: Contact embolism

[0037] 140S: Contact embolism

[0038] 150: Contact embolism

[0039] 160: Multilayer Interconnect (MLI) architecture

[0040] 162: Electrical conductivity characteristics

[0041] 162M: Wiring

[0042] 162V: Metallic Through Hole

[0043] 164: Dielectric Structure

[0044] 170: Energy Sensing Pad

[0045] 172: Conductive electrode

[0046] 174: Sensing film

[0047] 190: Reference electrode

[0048] 910: EUV Exposure Equipment

[0049] 920: Electron Beam Exposure Equipment

[0050] 930: Gas Supply System

[0051] 940: Plasma Generator

[0052] 950: Solution Supply System

[0053] A1: Array

[0054] BLN0~BLN3: Bit lines

[0055] BLN: Bitline

[0056] BLP0~BLP3: Bit lines

[0057] BLP: Bitline

[0058] CAS: Column Address Stochastic

[0059] CY1, CY2: Cycle

[0060] E1: EUV / DUV light

[0061] E2: Electron Beam

[0062] E3: Gas mixture

[0063] E4: Plasma

[0064] E5: ion

[0065] GND: Grounding

[0066] HV: High Voltage

[0067] IA: Input Address Node

[0068] INS: Initialization Operation

[0069] M: Method for operating the detection unit

[0070] NC: Passage Area

[0071] NT: n-type transistor

[0072] NV: Negative voltage

[0073] NW: Well area, well

[0074] ODN: Active Zone

[0075] ODP: Active Zone

[0076] OUT: Sensor output node

[0077] PC: Channel Area

[0078] PT: p-type transistor

[0079] RAS: Row Address Stochastic

[0080] RBP, RBN, NBP: Operations

[0081] REF: Reference Unit

[0082] RP, RN: Operations

[0083] RV: Read voltage

[0084] S1~S7: Steps

[0085] SDN: Source / Drain Region

[0086] SDP: Source / Drain Region

[0087] SL0~SL3: Source lines

[0088] SL: Source Line

[0089] V BIAS Bias voltage

[0090] V T Threshold voltage Detailed Implementation

[0091] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0092] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0093] As used herein, “approximately,” “about,” “around,” or “substantially” should generally mean within 20%, 10%, or 5% of a given value or range. The quantities given herein are approximate values, thus meaning that the terms “approximately,” “about,” “around,” or “substantially” may be interpreted without explicit statement.

[0094] The advanced lithography processes, methods, and materials described in the present disclosure can be used in many applications, including fin-type field-effect transistors (FinFETs). For example, fins can be patterned to create a relatively tight spacing between features that is well-suited to the above disclosure. Furthermore, the spacers used to form the fins of the FinFET can be processed according to the above disclosure.

[0095] This disclosure relates to a detection device and a method of operating the detection device. More specifically, some embodiments of this disclosure relate to a high-density and power-free detection device for ions in extreme ultraviolet (EUV) light, deep ultraviolet (DUV) light, electron beams (e-beams), gases, plasmas, and / or solutions. In some embodiments, the detection device may be implemented on a device including a planar device, a multi-gate device, a FinFET, a nanosheet gate FET, and a full-around FET.

[0096] Figure 1A This is a circuit diagram of a detection device 10 according to some embodiments of the present disclosure. The detection device 10 may include a plurality of detection units 100, bit lines BLP0 to BLP3, bit lines BLN0 to BLN3, and source lines SL0 to SL3. The detection units 100 are arranged in an array. Each of the detection units 100 may be coupled to one of the bit lines BLP0 to BLP3, one of the bit lines BLN0 to BLN3, and one of the source lines SL0 to SL3. Each of the detection units 100 for detecting light intensity includes an n-type transistor NT, a p-type transistor PT, and an energy sensing pad 170. The n-type transistor NT may be an n-type metal oxide semiconductor (NMOS) field-effect transistor (FET). The p-type transistor PT may be a p-type metal oxide semiconductor (PMOS) FET. The n-type transistor NT and the p-type transistor PT are connected / coupled. In some embodiments, bit lines BLP0 to BLP3 and BLN0 to BLN3 are parallel and interleaved, and bit lines BLP0 to BLP3 and BLN0 to BLN3 may extend in a direction different from the direction along which source lines SL0 to SL3 extend. For example, in Figure 1A In the diagram, bit lines BLP0 to BLP3 and BLN0 to BLN3 extend substantially along the row direction, while source lines SL0 to SL3 extend substantially along the column direction, which is substantially perpendicular to the row direction. Note that the array diagram of detection unit 100 is shown with four columns and rows, and the array of detection unit 100 can be configured to have any suitable number of columns and rows.

[0097] Figure 1B for Figure 1AA schematic cross-sectional view of the detection unit 100. An n-type transistor NT and a p-type transistor PT are formed above a semiconductor substrate 110. The n-type transistor NT includes a channel region NC, a gate structure 120 above the channel region NC, and a source / drain region SDN on the opposite side of the channel region NC. The p-type transistor PT includes a channel region PC, a gate structure 120 above the channel region PC, and a source / drain region SDP on the opposite side of the channel region PC. The channel regions PC / NC may be a portion of the semiconductor substrate 110 or semiconductor material deposited above the semiconductor substrate 110. The gate structure 120 may include a gate dielectric 122 above the channel regions PC / NC and a gate electrode 124 above the gate dielectric 122. In some embodiments, the semiconductor substrate 110 is a p-type substrate doped to have an n-type doped well NW, the p-type transistor PT is above the n-type doped well NW, and the n-type transistor NT is above the p-type substrate away from the n-type doped well.

[0098] See Figure 1A and Figure 1B For each of the detection units 100, the gates of the n-type transistor NT and the p-type transistor PT (e.g., gate electrodes 124 of the n-type transistor NT and the p-type transistor PT) are electrically connected to the same energy sensing pad 170. The source / drain node of the p-type transistor PT (e.g., the source / drain region SDP of the p-type transistor PT) is coupled to one of the bit lines BLP0 to BLP3 and one of the source lines SL0 to SL3, respectively. The source / drain node of the n-type transistor NT (e.g., the source / drain region SDN of the n-type transistor NT) is coupled to one of the bit lines BLN0 to BLN3 and one of the source lines SL0 to SL3, respectively. In this configuration, for each of the detection units 100, the gates of the n-type transistor NT and the p-type transistor PT (e.g., gate electrodes 124 of the n-type transistor NT and the p-type transistor PT) are electrically coupled to each other. Furthermore, for each of the detection units 100, connected to one of the source lines SL0 to SL3, one of the source / drain nodes of the p-type transistor PT (e.g., the source / drain region SDP of the p-type transistor PT) is electrically coupled to one of the source / drain nodes of the n-type transistor NT (e.g., the source / drain region SDN of the n-type transistor NT).

[0099] In some embodiments, the energy sensing pad 170 can receive external energy (e.g., EUV light, DUV light, electron beam) and generate charge (e.g., electrons) after the external energy. In some embodiments, for detecting light and electron beams, the gate electrodes 124 of the n-type transistor NT and p-type transistor PT can act as floating gates, which are signal storage nodes that store the charges generated by the energy sensing pad 170. The amount of charge stored in the gate electrode 124 can affect the threshold voltage (V) of the n-type transistor NT and p-type transistor PT. T ).

[0100] In some embodiments, the energy sensing pad 170 may interact with a substance (e.g., gas, plasma, and / or ions in solution) and change its resistance after interacting with the substance. Therefore, after exposing the energy sensing pad 170 to the substance, the electrical characteristics of the transistor NT / PT can reflect the level / degree of the characteristics of the external energy / substance (e.g., EUV light intensity and exposure time, DUV light intensity and exposure time, electron beam intensity and exposure time, gas concentration, the amount of plasma-induced charge in the plasma, and / or the particle concentration of ions in the solution). The level / degree of the characteristics of the external energy / substance can be determined by comparing the electrical characteristics of the transistor NT / PT before and after exposing the energy sensing pad 170 to the external energy / substance. For example, the level / degree of the characteristics of the external energy / substance can be determined by comparing the current flowing through the transistor NT / PT before and after exposing the energy sensing pad 170 to the external energy. In some embodiments, the distribution of the level / degree of the characteristics of external energy / matter can be determined via the array of detection units 100, and the uniformity of external energy / matter can also be determined.

[0101] Figure 1C The layout of a detection device 10 including a plurality of detection units 100 according to some embodiments of the present disclosure is shown. Figure 1C It can also serve as a top view of the detection device 10. Figure 1D Along the detection unit 100 Figure 1C An illustrative cross-sectional view taken from line DD in the figure. Isolation regions (not shown) are formed above semiconductor substrate 110 to define a plurality of active regions ODN and ODP. The isolation regions can be formed by etching trenches in semiconductor substrate 110 to define the active regions ODN and ODP, and depositing one or more dielectric materials (e.g., silicon oxide) to fill the trenches around the active regions ODN and ODP. In some embodiments, the isolation regions may be further isolated by recessed shallow trench isolations (STIs) defining fin-type active regions.

[0102] Gate structure 120 is formed over semiconductor substrate 110 and over active regions ODN and ODP. Gate structure 120 may include gate dielectric 122 and gate electrode 124 above gate dielectric 122. Gate dielectric 122 includes, for example, high-k dielectric materials, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti and other metals), silicon nitride, silicon oxide, and the like, or combinations thereof, or multiples thereof. In some embodiments, gate electrode 124 may be a suitable conductive material, such as polysilicon or metal. In some embodiments, gate electrode 124 may be a multilayer metal gate stack comprising, in sequence, formed on top of gate dielectric layer 132, a barrier layer, a work function layer, and a gate fill layer. Examples of barrier layer materials include TiN, TaN, Ti, Ta, or the like, or multiple combinations thereof. The work function layer may include TiN, TaN, Ru, Mo, and Al for p-type FETs, and may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr for n-type FETs. Other suitable work function materials or combinations thereof, or multiples thereof, may be used. The gate fill layer may comprise a metal, such as Cu, Al, W, Co, Ru, or similar materials, or combinations thereof, or multiples thereof.

[0103] The source / drain SDN / SDP is formed through regions of a heavily doped semiconductor substrate. In some embodiments, the source / drain SDN / SDP may include epitaxial growth regions. The source / drain SDN may be doped with n-type dopants, such as phosphorus or arsenic, and the source / drain SDP may be doped with p-type dopants, such as boron, BF2, or gallium.

[0104] Once the source / drain SDN / SDP regions are formed, an interlayer dielectric (ILD) layer 130 is deposited over the source / drain SDN / SDP regions. The ILD layer 130 may comprise silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low-k dielectric such as fluorosilicate glass (FSG), silicon oxide (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., xerogels / aerogels), or similar combinations thereof. The ILD layer 130 may be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or similar combinations thereof. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or similar or combinations thereof) may be deposited prior to the deposition of the ILD layer 130.

[0105] Contact plugs 140B, 140S, and 150 can be formed in the ILD layer 130 using optical lithography, etching, and deposition techniques. For example, a patterned mask can be formed over the ILD layer 130 and used to etch openings extending through the ILD layer 130 to expose the gate structure 120 and the source / drain regions SDN / SDP. Subsequently, conductive material can be formed in the openings in the ILD layer 130. The conductive material can include W, Al, Cu, Ru, Ni, Co, alloys of these metals, combinations thereof, and the like. In some embodiments, contact plugs 140B and 140S can include a metal silicide between the conductive material and the source / drain regions SD. A planarization process (e.g., CMP) can then be used to remove any excess portion of the conductive material from above the surface of the ILD layer 130. The resulting conductive plugs extend into the ILD layer 130 and form contact plugs 140B, 140S and 150, thereby forming a physical and electrical connection to the gate or source / drain node of an electronic device.

[0106] A multilayer interconnect (MLI) structure 160 is disposed above a semiconductor substrate 110. The MLI structure 160 includes various conductive features 162 and dielectric structures 164 surrounding the conductive features 162. The conductive features 162 may include vertical interconnects such as metal vias 162V and / or horizontal interconnects such as wiring 162M. The various conductive features 162 include conductive materials such as aluminum, titanium, titanium nitride, tungsten, polysilicon, copper, copper metallized silicide, copper alloys, tantalum, tantalum nitride, or combinations thereof. The various conductive features 162 may be formed by processes including physical vapor deposition (PVD), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques used to form the conductive features 162 may include optical lithography and etching to pattern the conductive material to form vertical and horizontal interconnects. The MLI structure 160 may include any number of conductive features, materials, sizes, and / or dimensions according to the design requirements of the integrated circuit device 200.

[0107] Some of the wiring 162M in the MLI structure 160 can serve as bit lines BLP in the detection device 10 (e.g., Figure 1C In the bit lines BLP0 to BLP1), bit line BLN (for example, Figure 1C The bit lines BLN0 to BLN1 and the source line SL (e.g., Figure 1C (Source lines SL0 to SL1 in the middle). Figure 1C The diagram illustrates a 2×2 array of detection unit 100. In some embodiments, bit lines BLP0 to BLP1 and BLN0 to BLN1 may extend along a direction different from the direction along which source lines SL0 to SL1 extend. For example, in Figure 1C In this configuration, bit lines BLP0 to BLP1 and BLN0 to BLN1 extend substantially along the Y direction, while source lines SL0 to SL1 extend substantially along a direction X, substantially perpendicular to the Y direction. In the embodiments disclosed herein, the gate structure 120 may extend in the same direction as the source lines SL0 to SL1. For example, the gate structure 120 may extend along the X direction.

[0108] MLI structure 160 includes an energy sensing pad 170 electrically coupled to the gate electrode 124 of an n-type transistor NT and a p-type transistor PT. The energy sensing pad 170 may be made of a suitable material capable of receiving external energy / matter and generating charge based on the received external energy / matter. The energy sensing pad 170 may be made of a material different from that of conductive feature 162. For example, the energy sensing pad 170 may be made of a metal having a different work function than that of conductive feature 162. In some embodiments, the energy sensing pad 170 is exposed from the MLI structure 160 for easy sensing. In some instances, the energy sensing pad 170 may be above the topmost terminal 162M of conductive feature 162, or at the same level as the topmost terminal 162M of conductive feature 162.

[0109] Dielectric structure 164 may surround conductive feature 162 and energy sensing pad 170. Dielectric structure 164 may include an ILD layer and a plurality of etch-stop layers between adjacent ILD layers. The ILD layer may comprise silicon oxide, PSG, BSG, BPSG, USG, a low-k dielectric such as FSG, SiOCH, CDO, flowable oxide or porous oxide (e.g., dry gel / aerogel) or similar, or combinations thereof. In some embodiments, the etch-stop layers may comprise a material different from that of the ILD layers, such as silicon nitride, silicon carbide or similar, or combinations thereof.

[0110] Figure 2 This is a flowchart of a method M for operating a detection unit 100 according to some embodiments of the present disclosure. Method M1 includes steps S1 to S7. In step S1, an initialization operation is performed on a p-type transistor. In step S2, a first pre-exposure readout operation is performed on the p-type transistor, and a second pre-exposure readout operation is performed on the n-type transistor. In step S3, an energy sensing pad is exposed to energy or matter. In step S4, a first post-exposure readout operation is performed on the p-type transistor, and a second post-exposure readout operation is performed on the n-type transistor. In step S5, it is determined whether the sensing of the p-type transistor is saturated. In step S6, if the sensing of the p-type transistor is not yet saturated, the characteristics of the external energy / matter are adjusted based on the data from the first pre-exposure readout operation and the first post-exposure readout operation. In step S7, if the sensing of the p-type transistor is saturated, the characteristics of the external energy / matter are adjusted based on the data from the second pre-exposure readout operation and the second post-exposure readout operation. It should be understood that for additional embodiments of the method, additional operations may be illustrated in the diagram. Figure 2 The steps S1 to S7 are provided before, during, and after the steps described below, and some of the steps S1 to S7 may be replaced or eliminated. The order of operations / processes may be interchangeable.

[0111] Figure 3This is a diagram of signal sequences used to operate the detection unit 100 according to some embodiments of this disclosure. See also... Figure 2 and Figure 3 Both. Method M begins at step S1, where an initialization operation INS is performed on the p-type transistor PT. The initialization operation INS can be performed by providing a high potential difference across the p-type transistor PT. For example, the initialization operation may include: applying a high voltage HV to the first source / drain node (i.e., bit line BLP) and well region NW of the p-type transistor PT, and charging the first source / drain node (i.e., bit line BLN) of the n-type transistor NT and the second source / drain node (i.e., source line SL) of both the n-type transistor NT and the p-type transistor PT to approximately 0V (e.g., ground (GND)). Through the initialization operation INS, a channel hot hole induced hot electron injection (CHHIHEL) effect occurs, and electrons are injected into the gate of the p-type transistor PT. The electrons in the gate of the p-type transistor PT will be used to detect energy (e.g., light / electron beam) or matter in a detection cycle, as will be discussed in more detail below. The high potential difference (e.g., the difference between the high voltage HV and ground) can be in the range of approximately 3.5 volts to approximately 8 volts. If the high voltage HV is below approximately 3.5 volts, the number of electrons in the gate of the p-type transistor PT may not be sufficient to detect the light intensity, or the sensitivity of the detection unit 100 may be low. If the high voltage HV is above approximately 8 volts, the detection unit 100 may be damaged.

[0112] Method M proceeds to step S2, where pre-exposure readout operations RBP and RBN are performed on the p-type transistor PT and the n-type transistor NT, respectively. In some embodiments, pre-exposure readout operation RBP is performed before pre-exposure readout operation RBN. In some alternative embodiments, pre-exposure readout operation RBN may be performed before pre-exposure readout operation RBP.

[0113] In the pre-exposure readout (RBP) operation, a readout voltage RV is applied to the first source / drain node (i.e., bit line BLP) of the p-type transistor PT, and the first source / drain node (i.e., bit line BLN) of the n-type transistor NT, the second source / drain nodes (i.e., source line SL) of the n-type transistor NT and the p-type transistor PT, the well region NW, and the substrate 110 below the p-type transistor PT are charged to approximately 0V (e.g., grounded (GND)). The RBP operation determines the initial data (e.g., initial readout current) of the p-type transistor PT.

[0114] In the pre-exposure readout operation NBP, a readout voltage RV is applied to the first source / drain node (i.e., bit line BLN) of the n-type transistor NT, and the first source / drain node (i.e., bit line BLP) of the p-type transistor PT, the second source / drain nodes (i.e., source line SL) of the n-type transistor NT and the p-type transistor PT, the well region NW, and the substrate 110 below the p-type transistor PT are charged to approximately 0V (e.g., grounded (GND)). The pre-exposure readout operation RBN determines the initial data (e.g., initial readout current) of the n-type transistor NT.

[0115] Method M then proceeds to step S3, where the energy sensing pad 170 is exposed to energy or matter. In the energy / matter exposure operation, the energy sensing pad 170 is exposed to energy (e.g., light / electron beam) or matter (gas mixture / plasma / ions), thereby increasing or decreasing the number of electrons stored in the p-type transistor PT and the gate of the p-type transistor PT. For example, as will be discussed later... Figure 4A As illustrated, the energy sensing pad 170 is exposed to EUV / DUV light E1. For example, as will be discussed later... Figure 5A As illustrated, the energy sensing pad 170 is exposed to the electron beam E2. For example, as will be discussed later... Figure 6A As illustrated, the energy sensing pad 170 is exposed to the gas mixture E3, plasma E4, and / or ions E5.

[0116] Method M then proceeds to step S4, where post-exposure readout operations RP and RN (see...) Figure 2 This is performed on the p-type transistor PT and the n-type transistor NT, respectively. In some embodiments, the post-exposure readout operation RP is performed before the post-exposure readout operation RN. In some alternative embodiments, the post-exposure readout operation RN may be performed before the post-exposure readout operation RP.

[0117] The post-exposure readout operation RP is similar to the pre-exposure readout operation RBP. For example, in the post-exposure readout operation RP, a readout voltage RV is applied to the first source / drain node (i.e., bit line BLP) of the p-type transistor PT, and the first source / drain node (i.e., bit line BLN) of the n-type transistor NT, the second source / drain nodes (i.e., source line SL) of the n-type transistor NT and the p-type transistor PT, the well region NW, and the substrate 110 below the p-type transistor PT are charged to approximately 0V (e.g., grounded (GND)). The post-exposure readout operation RP determines the sensed data (e.g., sensed readout current) of the p-type transistor PT.

[0118] The post-exposure readout operation RN is similar to the pre-exposure readout operation RBN. For example, a readout voltage RV is applied to the first source / drain node (i.e., bit line BLN) of the n-type transistor NT, and the first source / drain node (i.e., bit line BLP) of the p-type transistor PT, the second source / drain nodes (i.e., source lines SL) of the n-type transistor NT and the p-type transistor PT, the well region NW, and the substrate 110 beneath the p-type transistor PT are charged to approximately 0V (e.g., grounded (GND)). The post-exposure readout operation RN determines the sensed data (e.g., sensed readout current) of the n-type transistor NT.

[0119] In some embodiments, the absolute value of the high potential difference across the p-type transistor PT provided by the initialization operation INS is greater than the absolute value of the read potential difference between the two source / drain nodes of the p-type transistor provided by the read operations RBP and RP (or the absolute value of the read potential difference between the two source / drain nodes of the n-type transistor provided by the read operations RBN and RN). For example, the high potential difference (e.g., the difference between the high voltage HV and ground) may be in the range of about 3.5 volts to about 8 volts, while the read potential difference (e.g., the difference between the read voltage RV and ground) may be in the range of about 0.5 volts to about 1.5 volts.

[0120] In some embodiments, the relationship between the current and gate voltage of the p-type transistor PT under the read voltage and the relationship between the current and gate voltage of the n-type transistor NT under the read voltage can be measured and obtained. Therefore, the sensed read current determined by read operations RP, RN, RBP, and RBN under the read voltage can correspond to the gate voltages of the p-type transistor PT and the n-type transistor NT according to these relationships. In other words, the initial read current of the p-type transistor PT is determined by the pre-exposure read operation RBP, and the initial gate voltage of the p-type transistor PT can be further determined, wherein both the initial read current and initial voltage of the gate of the p-type transistor PT can be referred to as the initial data obtained at the pre-exposure read operation RBP. The initial read current of the n-type transistor NT is determined by the pre-exposure read operation RBN, and the initial gate voltage of the n-type transistor NT can be further determined, wherein both the initial read current and initial voltage of the gate of the p-type transistor PT can be referred to as the initial data obtained at the pre-exposure read operation RBN. The post-exposure readout operation RP determines the sensed readout current of the p-type transistor PT and further determines the gate voltage of the p-type transistor PT. Both the sensed readout current and voltage of the p-type transistor PT's gate can be referred to as the sensed data obtained at the post-exposure readout operation RP. Similarly, the post-exposure readout operation NP determines the sensed readout current of the n-type transistor NT and further determines the gate voltage of the n-type transistor NT. Both the sensed readout current and voltage of the n-type transistor NT's gate can be referred to as the sensed data obtained at the post-exposure readout operation RNP.

[0121] In some embodiments, for real-time continuous detection, loop CY1, including the initialization operation INS, pre-exposure readout operations RBP and RBN, energy / material exposure operation, and post-exposure readout operations RP and RN, can be repeated. In some alternative embodiments, loop CY1 can be executed first to obtain data from the pre-exposure readout operations RBP and RBN, and then loop CY2 can be repeated for real-time continuous detection. Loop CY2 omits the pre-exposure readout operations RBP and RBN compared to loop CY1.

[0122] Method M1 proceeds to step S5, where it is determined whether the sensing of the p-type transistor PT is saturated. In some embodiments, increasing / decreasing the amount of sensing data obtained at the post-exposure readout operation RP is tested using exposure time and exposure intensity / density. If increasing / decreasing the amount of sensing data obtained at the post-exposure readout operation RP becomes increasingly smaller as the exposure time passes, the sensing of the p-type transistor PT is considered saturated. For example, the sensing p-type transistor PT is considered saturated when the change in the amount of sensing data per unit time under exposure becomes less than a threshold ratio of the initial change in the amount of sensing data per unit time under exposure. In some embodiments, the threshold ratio may be in the range of about 5% to about 50%. In other words, the sensing p-type transistor PT is considered unsaturated when the change in the amount of sensing data per unit time under exposure is greater than a threshold ratio of the initial change in the amount of sensing data per unit time under exposure.

[0123] If the sensing of the p-type transistor PT is not yet saturated, method M1 proceeds to step S6, wherein the characteristics of the external energy / matter are adjusted based on the initial data of the first pre-exposure readout operation RBP and the sensing data of the first post-exposure readout operation RP performed on the p-type transistor PT. In some embodiments, method M may further include a comparison step performed to compare the sensing data of the obtained post-exposure readout operation RP with the initial data of the obtained pre-exposure readout operation RBP. The comparison may include calculating the difference between the sensing data of the obtained post-exposure readout operation RP and the initial data of the obtained pre-exposure readout operation RBP. In some embodiments, the adjustment of the characteristics of the external energy / matter may be determined based on the comparison result (e.g., the difference) between the sensing data of the obtained post-exposure readout operation RP and the initial data of the obtained pre-exposure readout operation RBP. In some alternative embodiments, the adjustment of the characteristics of the external energy / matter may be determined solely based on the sensing data of the obtained post-exposure readout operation RP.

[0124] In some embodiments, method M may further include a calculation step of calculating the level / degree of the characteristics of the external energy / matter, which may be based on a comparison (e.g., difference) between the sensing data obtained from the post-exposure readout operation RP and the initial data obtained from the pre-exposure readout operation RBP, or calculated solely based on the sensing data from the post-exposure readout operation RP. Furthermore, step S6 of method M includes adjusting the characteristics of the external energy / matter based on the calculated level / degree of the characteristics of the external energy / matter after the calculation step.

[0125] Once the p-type transistor's sensing is saturated, method M1 proceeds to step S7, where the characteristics of the external energy / matter are adjusted based on the initial data of the second pre-exposure readout operation RBN and the sensing data of the second post-exposure readout operation RN of the n-type transistor NT. In some embodiments, method M may further include a comparison step performed to compare the sensing data of the post-exposure readout operation RN with the initial data of the pre-exposure readout operation RBN. The comparison may include calculating the difference between the sensing data of the post-exposure readout operation RN and the initial data of the pre-exposure readout operation RBN. In some embodiments, the adjustment of the external energy / matter characteristics may be determined based on the comparison result (e.g., the difference) between the sensing data of the post-exposure readout operation RN and the initial data of the pre-exposure readout operation RBN. In some alternative embodiments, the adjustment of the external energy / matter characteristics may be determined solely based on the sensing data of the post-exposure readout operation RN.

[0126] In some embodiments, method M may further include a calculation step of calculating the level / degree of the properties of the external energy / matter, which may be based on a comparison (e.g., difference) between the sensing data obtained after the self-exposure readout operation RN and the initial data obtained before the self-exposure readout operation RBN, or calculated solely based on the sensing data of the self-exposure readout operation RN. Furthermore, step S7 of method M includes adjusting the properties of the external energy / matter based on the calculated level / degree of the properties of the external energy / matter after the calculation step.

[0127] The p-type transistor PT and the n-type transistor NT can have different sensing ranges corresponding to the number of electrons on the gates of the p-type transistor PT and the n-type transistor NT, respectively. The saturation sensing determination of the p-type transistor PT indicates that very few electrons remain on the gates of both the p-type transistor PT and the n-type transistor NT, causing the p-type transistor PT to turn off and the n-type transistor NT to turn on. Therefore, in the configuration of the n-type transistor NT, the sensing range of the p-type transistor PT can be compensated by the n-type transistor NT, thereby widening the sensing range of the detection unit 100.

[0128] In some embodiments, at steps S6 and S7, if the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the sensing data of the post-exposure readout operation RP / RN or the calculated level / degree of the characteristics of the external energy / matter) is not entirely satisfactory, then an adjustment to the characteristics of the external energy / matter is performed. The operator or controller may change the equipment (e.g., Figure 4A EUV exposure equipment 910 in Figure 5A The electron beam exposure equipment 920, gas supply system 930, and plasma generator 940 are included. Figure 6A The solution in the system (950) provides parameters of the components to adjust the characteristics of the external energy / matter based on the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the calculated level / degree of the external energy / matter characteristics is not entirely satisfactory).

[0129] For example, in EUV light or electron beams (illustrated later) Figure 4A and Figure 5A In some embodiments of the (Chinese) method, if the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the sensing data of the post-exposure readout operation RP / RN or the calculated level / level of the characteristics of external energy / matter) in the dark area is greater than the intensity of the threshold value at which the photoresist becomes undevelopable, then the EUV light or electron beam is determined to be unsatisfactory; and if the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the sensing data of the post-exposure readout operation RP / RN or the calculated level / level of the characteristics of external energy / matter) in the dark area is less than the intensity of the threshold value at which the photoresist becomes developable, then the EUV light or electron beam is determined to be satisfactory. On the other hand, if the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the sensing data of the post-exposure readout operation RP / RN or the calculated level / level of the characteristics of external energy / matter) in the bright area is less than the intensity of the photoresist becoming developable, then the EUV light or electron beam is determined to be unsatisfactory; and if the difference between the initial data of the pre-exposure readout operation RBP / RBN and the sensing data of the post-exposure readout operation RP / RN (or the sensing data of the post-exposure readout operation RP / RN or the calculated level / level of the characteristics of external energy / matter) in the bright area is greater than the intensity of the photoresist becoming developable, then the EUV light or electron beam is determined to be satisfactory.

[0130] In some embodiments, with the arrayed detection unit 100 configured, the level / degree of the characteristics of external energy / matter can be calculated at multiple regions, resulting in a two-dimensional spatial distribution, such as an image. In some embodiments, at steps S6 and S7, if the calculated two-dimensional spatial distribution is not entirely satisfactory, the operator or controller can change the device (e.g., Figure 4A EUV exposure equipment 910 in Figure 5A The electron beam exposure equipment 920, gas supply system 930, and plasma generator 940 are included. Figure 6A The solution in the system (950) provides parameters to adjust the level / degree of the properties of external energy / matter at the regions based on the calculated two-dimensional spatial distribution. For example, in some embodiments of EUV light / electron beam or gas mixture / plasma / ion, if the uniformity of the calculated two-dimensional spatial distribution of intensity / concentration at multiple regions is less than a threshold value, for example, in the range of about 10% to about 90%, then the EUV light / electron beam or gas mixture / plasma / ion is determined to be unsatisfactory; and if the uniformity of the calculated two-dimensional spatial distribution of intensity / concentration at multiple regions is greater than a threshold value, then the EUV light / electron beam or gas mixture / plasma / ion is determined to be satisfactory.

[0131] Figure 4A The illustrations provided are schematic cross-sectional views of an exemplary detection unit 100 under energy exposure operation for EUV / DUV light E1, according to some embodiments of this disclosure. For light detection, the energy sensing pad 170 may comprise a metal exhibiting the photoelectric effect with light. The photoelectric effect is a phenomenon where electric charge (e.g., electrons) can be emitted from the surface of a metal when light flashes on it. The metal of the energy sensing pad 170 may be selected based on the wavelength of the light to be detected. For example, the energy sensing pad 170 may have a work function between about 3.5 eV and about 6.5 eV for detecting EUV / DUV light E1.

[0132] In some embodiments, the energy sensing pad 170 is made of copper, which has a work function of approximately 4.65 eV. Therefore, when the energy sensing pad 170 is irradiated with light of a wavelength less than approximately 267 nanometers, electrons will leave due to the photoelectric effect. Since the energy sensing pad 170 is connected to the floating gate electrode 124 of the n-type transistor NT and the p-type transistor PT, it can directly affect the amount of charge in the floating gate electrode 124. In some alternative embodiments, the energy sensing pad 170 is made of platinum. In such embodiments, when the energy sensing pad 170 is irradiated with light of a wavelength less than approximately 220 nanometers, electrons will leave the platinum energy sensing pad 170 due to the photoelectric effect. In some alternative embodiments, the energy sensing pad 170 is made of aluminum. In such embodiments, when the energy sensing pad 170 is irradiated with light of a wavelength less than approximately 296 nanometers, electrons will leave the aluminum energy sensing pad 170 due to the photoelectric effect. In some alternative embodiments, the energy sensing pad 170 is made of magnesium. In such embodiments, when the energy sensing pad 170 is irradiated with light of a wavelength less than about 337 nanometers, electrons will leave the magnesium energy sensing pad 170 due to the photoelectric effect. Figure 4A In the diagram, the EUV / DUV exposure equipment 910 also generates EUV / DUV light E1 for use in lithography.

[0133] Figure 4B The curves represent the IV characteristics measured via the bit line BLP connected to the p-type transistor PT in the exemplary detection unit 100 before and after energy exposure operations for EUV / DUV light. During the initialization operation INS (see... Figure 3 Afterward, the gate of the p-type transistor PT is filled with electrons. When the detection unit 100 is exposed to EUV / DUV light, the stored electrons gain sufficient energy from the EUV / DUV light and can escape from the gate of the p-type transistor PT, for example, into the dielectric material in the MLI structure 160. Therefore, during this energy exposure operation, the stored electrons are removed or erased without any battery or power. The amount of escaped charge will be proportional to the light intensity and exposure time, and can be measured by measuring the Vt of the p-type transistor PT before and after exposure. T To determine.

[0134] In the absence of an n-type transistor (NT), for a p-type transistor (PT), with more exposure, more stored electrons escape, causing the PT to turn off, and the change in the IV curve will gradually saturate. The IV curve will shift less in response to more exposure, making the change in the IV curve difficult to observe.

[0135] Figure 4CThis is a curve showing the IV characteristic measured via bit line BLN connected to the n-type transistor NT in the exemplary detection unit 100 before and after energy exposure operation for EUV / DUV light. For the n-type transistor NT, with more exposure, the n-type transistor NT is turned on, and the IV curve can shift upward without reducing the amount of shift. Therefore, the operable sensing range of the detection device 10 can be greatly expanded.

[0136] Therefore, in order to expand the operable sensing range of the detection device 10, it is beneficial to determine the level / degree of the characteristics of external energy / matter based on: obtaining the self-exposure readout operation RP (see... Figure 3 The sensing data and the data obtained from the energy / matter exposure operation RN (see) Figure 3 Both of these can be obtained from the sensor data, or from the sensor data obtained from the self-exposure readout operation RP (see [link]). Figure 3 ) and obtain the initial data for the readout operation RBP before self-exposure (see Figure 3 The comparison results between the two and the sensing data obtained from the energy / matter exposure operation RN (see) Figure 3 ) and obtain the initial data of the readout operation RBN before self-exposure (see Figure 3 Comparison between ).

[0137] Figure 5A This is a schematic cross-sectional view of an exemplary detection unit 100 under energy exposure operation for electron beam E2, illustrating some embodiments of this disclosure. Figure 5A In the diagram, electron beam exposure equipment 920 is also shown to generate an electron beam E2 for use in lithography. Figure 5B A curve representing the IV characteristic measured via a bit line connected to a p-type transistor in an exemplary detection unit before and after energy exposure operation against an electron beam. When electrons from the electron beam are projected onto an empty or neutral floating gate electrode 124, the electrons are collected by the floating gate electrode 124, thereby causing the V value of the corresponding detection unit 100 to... T Shift. Similarly, quantization threshold voltage (V T Changes will reflect intensity and exposure time, and can be readings from offline measurements (similar to wafer acceptance test (WAT)).

[0138] Figure 6A This is a schematic cross-sectional view of an exemplary detection unit under material exposure operation of a needle gas mixture E3, plasma E4, and / or ions E5 according to some embodiments of this disclosure. The size, structure, and design of the energy sensing pad 170 may vary as required for different applications. Figure 6AThe diagram also shows a gas supply system 930 for supplying gas mixture E3; a plasma generator 940 for generating plasma E4; and a solution supply system 950 for providing a solution containing ions E5.

[0139] In some embodiments, the energy sensing pad 170 may be exposed to the gas mixture E3 for gas sensing. In such embodiments, the energy sensing pad 170 may be a sensing film comprising a variable-resistivity material having a resistance that varies according to the concentration of the gas. For example, the sensing film may be made of SnSe2. Figure 6B This is a circuit diagram of a detection unit 100 for detecting gas mixture E3 according to some embodiments of this disclosure. The energy sensing pad 170 is biased at voltage V. BIAS A reference resistor is connected in series with the ground potential. Using a variable-resistance material, the voltages on the gates of the n-type transistor NT and the p-type transistor PT will change with the gas concentration. When the resistance of the energy sensing pad 170 changes according to the gas concentration, the gate voltages of the n-type transistor NT and the p-type transistor PT will change. Therefore, reading the current flowing through the n-type transistor NT and the p-type transistor PT will reveal the gas concentration.

[0140] In some embodiments, the energy sensing pad 170 may be exposed to plasma E4 for plasma sensing. In such embodiments, the energy sensing pad 170 may include a sensing film made of copper. When sensing plasma E4, the size of the energy sensing pad 170 may be adjusted to vary the amount of charge collected. By collecting the charge passing through the energy sensing pad 170 and the gate electrode 124, it is possible to measure the plasma charge induced charge caused by charge impairment effects during the plasma process. For plasma sensing, the energy sensing pad 170 may be floating (e.g., Figure 1A (The circuit in the middle) or supplied with a bias voltage V BIAS The bias voltage (e.g., connected in series with the reference resistor between the ground potential and the reference potential) Figure 6B (circuit).

[0141] In some embodiments, the energy sensing pad 170 can be used for ion sensing. Figure 6CThis is a circuit diagram of a detection unit 100 for detecting ions in a solution according to some embodiments of this disclosure. In such embodiments, an energy sensing pad 170 may include a conductive electrode 172, and a dielectric sensing film 174 may be formed on the conductive electrode 172. The conductive electrode 172 is coupled to the floating gate electrode 124 of an n-type transistor NT and a p-type transistor PT. The dielectric sensing film 174 is exposed to ions E5. The dielectric sensing film 174 may be a silicon oxide film or an aluminum oxide film. A conductive reference electrode 190 connected to a reference potential is also coupled to the floating gate electrode 124 of the n-type transistor NT and the p-type transistor PT. By using the sensing film 174 to chemically react with ions and integrated into the structure together with the reference electrode 190, the ion concentration in the solution can be measured via the charge stored in the floating gate electrode 124 of the n-type transistor NT and the p-type transistor PT.

[0142] Figure 7 This is a block diagram of a detection device 10 according to some embodiments of the present disclosure. A layout design of a compact detection device 10 is shown. The detection device 10 may include a pixel array A1, bit lines BLP and BLN, source lines SL, a row decoder 12, column decoders 14P and 14N, multiplexers 16P and 16N, address buffers 18S, 18P and 18N, a row address strobe RAS, and a column address strobe CAS.

[0143] Array A1 may include multiple pixels, each of which corresponds to detection unit 100 (see...) Figure 1A and Figure 1B The bit lines BLP and BLN, and the source line SL can correspond to bit lines BLP0 to BLP3, bit lines BLN0 to BLN3, and source lines SL0 to SL3, respectively (see...). Figure 1A and Figure 1B The pixels of array A1 are electrically connected to the bit lines BLP and BLN and the source line SL. Address buffers 18S, 18P, and 18N receive signals from the input address node IA. Row decoder 12 is electrically connected between the source line SL and the address buffer 18S, which provides row address strobe RAS. Column decoder 14P is electrically connected between the bit line BLP and the address buffer 18P, which provides column address strobe CAS. Column decoder 14N is electrically connected between the bit line BLN and the address buffer 18N, which provides column address strobe CAS. Multiplexer 16P is connected between column decoder 14P and the bit line BLP, and multiplexer 16N is connected between column decoder 14N and the bit line BLN. In some embodiments, the sensing output node OUT may be electrically connected to multiplexers 16P and 16N. In some embodiments, the detection device 10 may further include a reference unit REF connected to multiplexers 16P and 16N.

[0144] Through layout design, initialize operations INS and read operations RP, RN, RBP, RBN (see...) Figure 3 This can be performed on each pixel of array A1. In some embodiments, by integrating with peripheral circuitry such as sense amplifiers and decoders, it is possible to amplify signals generated by the elements or control the on / off state of specific units, thereby allowing the array to drive other circuitry and providing more applications.

[0145] A controller that changes the parameters of a device's components may include a computer-readable storage medium and a processor coupled to the computer-readable storage medium. The computer-readable storage medium stores a program that performs the steps of method M (see...). Figure 2 The controller performs various steps of method M by using a processor to read and execute a program stored in a storage medium. For example, the processor may send signals / commands as input address nodes IA to address buffers 18S, 18P, and 18N, thereby controlling row decoder 12 and column decoders 14P and 14N. The program may be a program already stored in a computer-readable storage medium or a program installed on a storage medium to the controller.

[0146] Figure 8 This is a diagram of signal sequences for operating a detection unit according to some embodiments of this disclosure. The details of the embodiments disclosed are similar to... Figure 3 The details, besides the initialization operation INS including: charging the first source / drain node (i.e., bit line BLP) and well region NW of the p-type transistor PT to approximately 0V (e.g., ground (GND)), and applying a negative voltage NV to the first source / drain node (i.e., bit line BLN) of the n-type transistor NT and the second source / drain node (i.e., source line SL) of both the n-type transistor NT and the p-type transistor PT, provide a high potential difference across the p-type transistor PT throughout the configuration. Through the initialization operation, a channel hot hole induced hot electron injection (CHHIHEL) effect occurs, and electrons are injected into the gate of the p-type transistor PT. The electrons in the gate of the p-type transistor PT will be used to detect energy (e.g., light / electron beam) or matter in the detection cycle. Other details of the embodiments disclosed herein are similar. Figure 2 The details illustrated in the embodiments are therefore not repeated herein.

[0147] Based on the foregoing discussion, it is evident that this disclosure offers several advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage claimed for all embodiments. One advantage is that a detector comprising n-type and p-type transistors is designed to detect and record the intensity and spatial distribution of EUV, DUV, and electron beams projected onto a wafer, and the detector features broadened sensing range and full compatibility with CMOS logic processes. Another advantage is that the detector is designed with selectivity for the wavelength of the target sensing light or the concentration of the target sensing substance. Yet another advantage is that the detector is designed with compact complementary 2-transistor (2T) pixels for higher spatial resolution. A further advantage is that the detector can be completely battery-free or power-free when sensing and recording EUV / DUV / electron beam signals. Yet another advantage is that data can be read out from the in-line WAT for timely feedback optimized for scanner settings.

[0148] According to some embodiments, a method for operating a detection device includes: directing an exposure energy from an exposure apparatus to the detection device, wherein the detection device includes a plurality of detection units, each of the plurality of detection units including an n-type transistor, a p-type transistor, and an energy sensing pad coupled to a plurality of gates of the n-type transistor and the p-type transistor; performing a first post-exposure readout operation on the p-type transistor of one of the plurality of detection units; and performing a second post-exposure readout operation on the n-type transistor of the one of the plurality of detection units.

[0149] In some embodiments, the method further includes adjusting the exposure device based on one of the data from the first post-exposure readout operation and the data from the second post-exposure readout operation.

[0150] In some embodiments, the energy sensing pad and the plurality of gates of the n-type transistor and the p-type transistor are electrically floating.

[0151] In some embodiments, the method further includes performing an initialization operation before directing the exposure energy of the exposure device to the detection device, wherein the initialization operation includes the step of providing a potential difference between two source / drain nodes of the p-type transistor of one of the plurality of detection units.

[0152] In some embodiments, the method further includes performing a first pre-exposure readout operation on the p-type transistor of one of the plurality of detection units after the initialization operation; comparing the data of the first pre-exposure readout operation with the data of the first post-exposure readout operation; and adjusting the exposure device based on a comparison result between the data of the first pre-exposure readout operation and the data of the first post-exposure readout operation.

[0153] In some embodiments, the method further includes performing a second pre-exposure readout operation on the n-type transistor of one of the plurality of detection units after the initialization operation; comparing the data of the second pre-exposure readout operation with the data of the second post-exposure readout operation; and adjusting the exposure device based on a comparison result between the data of the second pre-exposure readout operation and the data of the second post-exposure readout operation.

[0154] In some embodiments, the absolute value of the potential difference between the two source / drain nodes of the p-type transistor provided by the initialization operation is greater than the absolute value of a readout potential difference between the two source / drain nodes of the p-type transistor provided by the first post-exposure readout operation.

[0155] According to some embodiments, a method for operating a detection device includes: providing the detection device comprising a plurality of detection units, each of the plurality of detection units comprising an n-type transistor, a p-type transistor, and an energy-sensing pad coupled to a plurality of gates of the n-type transistor and the p-type transistor; exposing the energy-sensing pad of the plurality of detection units to a material; performing a first post-exposure readout operation on the p-type transistor of one of the plurality of detection units; and performing a second post-exposure readout operation on the n-type transistor of the one of the plurality of detection units.

[0156] In some embodiments, the method further includes adjusting a distribution of the substance based on one of the data from the first post-exposure readout operation and the data from the second post-exposure readout operation.

[0157] In some embodiments, the substance is a gas mixture, a plasma, or a plurality of ions in a solution.

[0158] In some embodiments, the method further includes supplying a bias voltage to the energy sensing pad of one of the plurality of detection units when the energy sensing pad of the plurality of detection units is exposed to the material.

[0159] In some embodiments, when the energy sensing pads of the plurality of detection units are exposed to the material, the energy sensing pads and the plurality of gates of the n-type transistor and the p-type transistor are electrically floating.

[0160] According to some embodiments, a detection device includes at least one detection unit, a source line, a first bit line, and a second bit line. The detection unit includes an n-type transistor, a p-type transistor, and an energy-sensing pad. Each of the n-type transistor and the p-type transistor includes a gate electrode, a first source / drain node, and a second source / drain node. The energy-sensing pad is coupled to the gate electrode of the n-type transistor and the gate electrode of the p-type transistor. The source line is coupled to the first source / drain node of the n-type transistor and the first source / drain node of the p-type transistor of the detection unit. The first bit line is coupled to the second source / drain node of the p-type transistor of the detection unit. The second bit line is coupled to the second source / drain node of the n-type transistor of the detection unit.

[0161] In some embodiments, the detection device further includes an interconnect structure above the n-type transistor and the p-type transistor, wherein the interconnect structure includes a plurality of conductive features, and a portion of the plurality of conductive features connects the gate electrode of the n-type transistor and the gate electrode of the p-type transistor to the energy sensing pad.

[0162] In some embodiments, the energy sensing pad is exposed from the interconnect structure.

[0163] In some embodiments, a material of the energy sensing pad is different from a material of the plurality of conductive features.

[0164] In some embodiments, the energy sensing pad is higher than the plurality of conductive features.

[0165] In some embodiments, the energy sensing pad is made of a metal having a work function between about 3.5 eV and about 6.5 eV.

[0166] In some embodiments, the energy sensing pad is a sensing film made of SnSe2.

[0167] In some embodiments, the energy sensing pad includes an electrode and a dielectric sensing film above the electrode.

[0168] According to some embodiments, the detection device includes an n-type transistor and a p-type transistor; a multilayer interconnect structure located on the n-type transistor and the p-type transistor, wherein the multilayer interconnect structure includes a first conductive feature and a second conductive feature, the first conductive feature being coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; and an energy sensing pad located on the multilayer interconnect structure, wherein the second conductive feature is coupled to the energy sensing pad, a gate electrode of the n-type transistor, and a gate electrode of the p-type transistor.

[0169] In some embodiments, the multilayer interconnect structure further includes a dielectric layer that separates the first conductive feature from the second conductive feature.

[0170] In some embodiments, the multilayer interconnect structure further includes a third conductive feature coupled to a second source / drain region of the n-type transistor; and a fourth conductive feature coupled to a second source / drain region of the p-type transistor, wherein the dielectric layer separates the first to fourth conductive features.

[0171] According to some embodiments, a detection device includes an n-type transistor and a p-type transistor; a first conductive feature coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; a second conductive feature coupled to a gate electrode of the n-type transistor and a gate electrode of the p-type transistor; and an energy sensing pad coupled to the second conductive feature, wherein an upper surface of the energy sensing pad is higher than an upper surface of the second conductive feature.

[0172] In some embodiments, the upper surface of the second conductive feature is higher than an upper surface of the first conductive feature.

[0173] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A detection device, characterized in that, Include: An n-type transistor and a p-type transistor; A multilayer interconnect structure is located on the n-type transistor and the p-type transistor, wherein the multilayer interconnect structure includes a first conductive feature and a second conductive feature, the first conductive feature being coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; as well as An energy sensing pad is located on the multilayer interconnect structure, wherein the second conductive feature is coupled to the energy sensing pad, a gate electrode of the n-type transistor and a gate electrode of the p-type transistor.

2. The detection device as described in claim 1, characterized in that, The multilayer interconnect structure also includes a dielectric layer that separates the first conductive feature from the second conductive feature.

3. The detection device as described in claim 2, characterized in that, The multilayer interconnect structure also includes: A third conductive feature is coupled to a second source / drain region of the n-type transistor; and A fourth conductive feature is coupled to a second source / drain region of the p-type transistor, wherein the dielectric layer separates the first conductive feature from the fourth conductive feature.

4. A detection device, characterized in that, Include: An n-type transistor and a p-type transistor; A first conductive feature is coupled to a first source / drain region of the n-type transistor and a first source / drain region of the p-type transistor; A second conductive feature is coupled to a gate electrode of the n-type transistor and a gate electrode of the p-type transistor; An energy sensing pad is coupled to the second conductive feature, wherein an upper surface of the energy sensing pad is higher than an upper surface of the second conductive feature.

5. The detection device as described in claim 4, characterized in that, The upper surface of the second conductive feature is higher than the upper surface of the first conductive feature.

6. A detection device, characterized in that, Include: At least one detection unit, wherein the detection unit comprises: An n-type transistor and a p-type transistor, wherein each of the n-type transistor and the p-type transistor includes a gate electrode, a first source / drain node, and a second source / drain node; and An energy sensing pad is coupled to the gate electrode of the n-type transistor and the gate electrode of the p-type transistor; A source line is coupled to the first source / drain node of the n-type transistor and the first source / drain node of the p-type transistor in the detection unit. A first element line, which is coupled to the second source / drain node of the p-type transistor of the detection unit; and A second bit line is coupled to the second source / drain node of the n-type transistor of the detection unit.

7. The detection device as described in claim 6, characterized in that, Further includes: An interconnect structure above the n-type transistor and the p-type transistor, wherein the interconnect structure includes a plurality of conductive features, and a portion of the plurality of conductive features connects the gate electrode of the n-type transistor and the gate electrode of the p-type transistor to the energy sensing pad.

8. The detection device as described in claim 7, characterized in that, The energy sensing pad is exposed from the interconnect structure.

9. The detection device as described in claim 7 or 8, characterized in that, The energy sensing pad is higher than the plurality of conductive features.

10. The detection device according to any one of claims 6 to 8, characterized in that, The energy sensing pad includes an electrode and a dielectric sensing film above the electrode.

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