Back contact solar cell, cell module and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system, the back contact solar cell comprises a silicon wafer, the back surface of the silicon wafer comprises P regions and N regions which are alternately arranged in sequence; the first fine grid line is arranged in the P region; the second fine grid line is arranged in the N region; a first height difference exists between the maximum height of the second thin grid lines and the minimum height of the second thin grid lines, a second height difference exists between the maximum height of the first thin grid lines and the minimum height of the first thin grid lines, and the first height difference is smaller than the second height difference. The heights of the second fine grid lines in the N region of the back contact solar cell are more uniform, the resistance of the second fine grid lines can be reduced, the current transmission lower limit value of the second fine grid lines is improved, and the cell filling factor is improved, so that the cell conversion efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically to a back-contact solar cell, a battery module, and a photovoltaic system. Background Technology

[0002] Back-contact solar cells, as one of the current high-efficiency cell structures, are characterized by the absence of grid lines on the front. Instead, the positive and negative electrodes and PN junctions are all placed on the back of the cell in an interdigitated arrangement. This structure prevents the front from being affected by the shading of the grid lines, while maximizing the size range of the metal grid lines on the back of the cell, optimizing the arrangement, and reducing the series resistance on the back of the cell, thereby improving the fill factor and conversion efficiency.

[0003] In the prior art, fine grid lines are printed on both the P-region and N-region of the back contact solar cell. However, since the impact of the height uniformity of the fine grid lines in the P-region and N-region of the back contact solar cell on the cell performance is usually not considered, the resistance of the fine grid lines in the N-region is relatively large, which affects the cell conversion efficiency. Utility Model Content

[0004] This invention provides a back-contact solar cell, which aims to solve the problem that the fine grid line resistance in the N-region of existing back-contact solar cells is relatively high, thus affecting the cell conversion efficiency.

[0005] This invention is implemented by providing a back-contact solar cell, comprising:

[0006] A silicon wafer, the back side of which includes P-regions and N-regions arranged alternately in sequence;

[0007] The first fine grid line is located in the P region;

[0008] The second fine gate line is located in the N region;

[0009] Wherein, the maximum height of the second fine gate line and the minimum height of the second fine gate line have a first height difference, the maximum height of the first fine gate line and the minimum height of the first fine gate line have a second height difference, and the first height difference is less than the second height difference.

[0010] The present invention provides a back-contact solar cell in which the maximum height of the second fine grid line in the N region has a first height difference with the minimum height of the second fine grid line, and the maximum height of the first fine grid line in the P region has a second height difference with the minimum height of the first fine grid line, and the first height difference is less than the second height difference. This makes the height of the second fine grid line in the N region more uniform, which can reduce the resistance of the second fine grid line, increase the lower limit of current transmission of the second fine grid line, improve the cell fill factor, and thus improve the cell conversion efficiency.

[0011] Preferably, the first height difference is less than or equal to 1 micrometer; the second height difference is less than or equal to 2.1 micrometers.

[0012] This invention controls the first height difference to be less than or equal to 1 micrometer and the second height difference to be less than or equal to 2.1 micrometers, that is, controls the first height difference to be within 1 micrometer and the second height difference to be within 2.1 micrometers, so that the height variation of the second fine grid line is smaller than that of the first fine grid line, and the height of the second fine grid line is more uniform than that of the first fine grid line.

[0013] Preferably, the height of the first fine gate line is 5.6 to 7.7 micrometers, and the height of the second fine gate line is 5.8 to 6.8 micrometers.

[0014] Preferably, the difference in maximum height between two adjacent second fine grid lines is less than the difference in maximum height between two adjacent first fine grid lines, and the difference in minimum height between two adjacent second fine grid lines is less than the difference in minimum height between two adjacent first fine grid lines.

[0015] Because the difference in maximum height between two adjacent second fine gate lines is less than the difference in maximum height between two adjacent first fine gate lines, and the difference in minimum height between two adjacent second fine gate lines is less than the difference in minimum height between two adjacent first fine gate lines, the height variation of different second fine gate lines is smaller than the height variation of different first fine gate lines. This makes the height of all second fine gate lines more uniform than that of all first fine gate lines, and can further reduce the resistance of the second fine gate lines.

[0016] Preferably, the width of the first fine gate line is greater than the width of the second fine gate line.

[0017] Preferably, the difference between the width of the first fine gate line and the width of the second fine gate line is 2 to 3 micrometers.

[0018] This invention achieves good contact performance between the first fine gate line and the P-type doped layer by setting the difference between the width of the first fine gate line and the width of the second fine gate line to 2-3 micrometers, while avoiding the need for more paste and thus reducing costs.

[0019] Preferred options also include:

[0020] A P-type doped layer is provided in the P region, and the first fine gate line is provided on the side of the P-type doped layer away from the silicon wafer and in contact with the P-type doped layer;

[0021] An N-type doped layer is disposed in the N region, and the second fine gate line is disposed on the side of the N-type doped layer away from the silicon wafer and in contact with the N-type doped layer.

[0022] Preferred options also include:

[0023] A tunneling oxide layer is disposed between the P-type doped layer and the silicon wafer, and between the N-type doped layer and the silicon wafer.

[0024] In this embodiment, the width of the first fine gate line is increased to be greater than that of the second fine gate line, thereby increasing the contact area between the first fine gate line and the P-type doped layer, improving contact performance, reducing the contact resistance of the P-region, and further improving battery efficiency.

[0025] This invention also provides a battery assembly, including the aforementioned back-contact solar cell.

[0026] This utility model also provides a photovoltaic system, including the above-mentioned battery components. Attached Figure Description

[0027] Figure 1 A schematic diagram of the back structure of a back-contact solar cell provided in an embodiment of this utility model;

[0028] Figure 2 A cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this utility model;

[0029] Figure 3 A schematic diagram of the first fine grid line of a back-contact solar cell provided in an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the second fine grid line of a back-contact solar cell provided in an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0032] The present invention provides a back-contact solar cell in which the maximum height of the second fine grid line in the N region has a first height difference with the minimum height of the second fine grid line, and the maximum height of the first fine grid line in the P region has a second height difference with the minimum height of the first fine grid line, and the first height difference is less than the second height difference. This makes the height of the second fine grid line in the N region more uniform, which can reduce the resistance of the second fine grid line, increase the lower limit of current transmission of the second fine grid line, improve the cell fill factor, and thus improve the cell conversion efficiency.

[0033] Please refer to Figures 1-4 This utility model provides a back-contact solar cell, comprising:

[0034] Silicon wafer 1, the back side of silicon wafer 1 includes P-region 11 and N-region 12 arranged alternately in sequence;

[0035] The first fine grid line 2 is located in region P11;

[0036] The second fine grid line 3 is located in region N, 12;

[0037] Among them, the maximum height H1 of the second fine grid line 3 and the minimum height H2 of the second fine grid line 3 have a first height difference, and the maximum height H3 of the first fine grid line 2 and the minimum height H4 of the first fine grid line 2 have a second height difference, and the first height difference is less than the second height difference.

[0038] In this embodiment of the invention, the silicon wafer 1 can be either a P-type or an N-type silicon wafer, and the specific type is not limited herein. There are multiple P-regions 11 and N-regions 12, which are arranged alternately and at intervals. Optionally, an isolation region is provided between adjacent P-regions 11 and N-regions 12. Figure 1 The dotted lines in the diagram do not actually exist; they are merely used to distinguish between area P11 and area N12.

[0039] In this embodiment of the present invention, the number of first fine gate lines 2 in each P region 11 can be one or more, and the number of second fine gate lines 3 in each N region 12 can also be one or more.

[0040] Please refer to this again. Figure 3 and Figure 4 In this embodiment of the present invention, the second fine gate line 3 includes a first surface 31 disposed away from the silicon wafer 1 and a second surface 32 disposed close to the silicon wafer 1. The height of the second fine gate line 3 is the distance between the first surface 31 and the second surface 32. The maximum height H1 of the second fine gate line 3 is the maximum distance between the first surface 31 and the second surface 32, and the minimum height H2 of the second fine gate line 3 is the minimum distance between the first surface 31 and the second surface 32. The first fine gate line 2 includes a third surface 21 disposed away from the silicon wafer 1 and a fourth surface 22 disposed close to the silicon wafer 1. The height of the first fine gate line 2 is the distance between the third surface 21 and the fourth surface 22. The maximum height H3 of the first fine gate line 2 is the maximum distance between the third surface 21 and the fourth surface 22, and the minimum height H4 of the first fine gate line 2 is the minimum distance between the third surface 21 and the fourth surface 22.

[0041] In this embodiment of the present invention, the maximum height H1 and minimum height H2 of the second fine grid line 3 in the N region 12 of a back-contact solar cell have a first height difference, and the maximum height H3 and minimum height H4 of the first fine grid line 2 in the P region 11 have a second height difference. The first height difference is less than the first height difference. This can be understood as follows: the maximum height H1 of any second fine grid line 3 has a first height difference with its minimum height H2; similarly, the maximum height H3 of any first fine grid line 2 has a second height difference with its minimum height H4. Since the difference between the maximum and minimum height of any second fine grid line 3 is less than the difference between the maximum and minimum height of any first fine grid line 2, the height of the second fine grid line 3 is more uniform than that of the first fine grid line 2, meaning the height variation of the second fine grid line 3 is smaller. This reduces the resistance of the second fine grid line 3 in the N region 12, increases the lower limit of current transmission, improves the fill factor, and thus improves the cell conversion efficiency. In some embodiments, the first height difference of the second fine grid line 3 being less than the second height difference of the first fine grid line 2 can mean that the first height difference between the maximum height H1 and the minimum height H2 of any second fine grid line 3 is less than the second height difference between the maximum height H3 and the minimum height H4 of any first fine grid line 2, or that the difference in the maximum height of two adjacent second fine grid lines 3 is less than the difference in the maximum height of two adjacent first fine grid lines 2, and the difference in the minimum height of two adjacent second fine grid lines 3 is less than the difference in the minimum height of two adjacent first fine grid lines 2. That is, comparing the height difference between the first fine grid line 2 and the second fine grid line 3 can be comparing the height difference between one first fine grid line 2 and the second fine grid line 3, or it can be comparing the height difference between two adjacent first fine grid lines 2 and two adjacent second fine grid lines 3; this invention does not limit this.

[0042] In this embodiment of the present invention, the second fine grid line 3 of the N region 12 can be printed in one go, and the first fine grid line 2 of the P region 11 can be printed in one go. The second fine grid line 3 is coated by the printing squeegee twice, so that the height of the second fine grid line 3 of the N region 12 is more uniform.

[0043] As one embodiment of this utility model, the first height difference is less than or equal to 1 micrometer; the second height difference is less than or equal to 2.1 micrometers.

[0044] In this embodiment, the difference between the maximum height and the minimum height of the second fine gate line 3 is less than 1 micrometer, and the difference between the maximum height and the minimum height of the first fine gate line 2 is less than 2.1 micrometers. That is, the difference between the maximum height and the minimum height of the second fine gate line 3 is controlled within 1 micrometer, and the difference between the maximum height and the minimum height of the first fine gate line 2 is controlled within 2.1 micrometers, so that the height variation of the second fine gate line 3 is smaller than that of the first fine gate line 2, and the height of the second fine gate line 3 is more uniform than that of the first fine gate line 2.

[0045] For example, the first height difference can be any value among 0.1 micrometer, 0.2 micrometer, 0.3 micrometer, 0.4 micrometer, 0.5 micrometer, 0.6 micrometer, 0.7 micrometer, 0.8 micrometer, 0.9 micrometer, and 1.0 micrometer; the second height difference can be any value among 1.1 micrometer, 1.2 micrometer, 1.4 micrometer, 1.6 micrometer, 1.7 micrometer, 1.8 micrometer, 1.9 micrometer, 2.0 micrometer, and 2.1 micrometer.

[0046] In one embodiment of this utility model, the height of the first fine grid line 2 is 5.6 to 7.7 micrometers, and the height of the second fine grid line 3 is 5.8 to 6.8 micrometers.

[0047] The height of each first fine gate line 2 is 5.6–7.7 micrometers. This can be understood as the height of each first fine gate line 2 at any position being 5.6–7.7 micrometers, with a minimum height of 5.6 micrometers and a maximum height of 7.7 micrometers. For example, the height of the first fine gate line 2 at any position could be 5.6 micrometers, 5.7 micrometers, 5.9 micrometers, 6.0 micrometers, 6.1 micrometers, 6.3 micrometers, 6.5 micrometers, 6.8 micrometers, 6.9 micrometers, 7.0 micrometers, 7.1 micrometers, 7.2 micrometers, 7.3 micrometers, 7.4 micrometers, 7.6 micrometers, or 7.7 micrometers.

[0048] The height of each second fine gate line 3 is 5.8–6.8 micrometers. This can be understood as the height of each second fine gate line 3 at any given position being 5.8–6.8 micrometers, with a minimum height of 5.8 micrometers and a maximum height of 6.8 micrometers. For example, the height of the second fine gate line 3 at any given position could be 5.8 micrometers, 5.9 micrometers, 6.0 micrometers, 6.1 micrometers, 6.2 micrometers, 6.4 micrometers, 6.5 micrometers, 6.6 micrometers, 6.7 micrometers, or 6.8 micrometers.

[0049] For example, when the maximum height H3 of the first fine gate line 2 is 7.7 micrometers and the minimum height H4 of the first fine gate line 2 is 5.6 micrometers, the second height difference between the maximum height H3 and the minimum height H4 of the first fine gate line 2 is 2.1 micrometers; when the maximum height H1 of the second fine gate line 3 is 6.8 micrometers and the minimum height H2 of the second fine gate line 3 is 5.8 micrometers, the second height difference between the maximum height H1 and the minimum height H2 of the second fine gate line 3 is 1.0 micrometers.

[0050] In one embodiment of this utility model, the difference in maximum height between two adjacent second fine grid lines 3 is less than the difference in maximum height between two adjacent first fine grid lines 2, and the difference in minimum height between two adjacent second fine grid lines 3 is less than the difference in minimum height between two adjacent first fine grid lines 2.

[0051] In some embodiments, when multiple first fine grid lines 2 and multiple second fine grid lines 3 are arranged, comparing the height difference between two adjacent second fine grid lines 3 and the height difference between two adjacent first fine grid lines 2 can be comparing two adjacent grid lines or comparing two grid lines arranged at intervals.

[0052] For example, when multiple first fine grid lines 2 are arranged sequentially, the arrangement order can be the first first fine grid line 2, the second first fine grid line 2, the third first fine grid line 2, the fourth first fine grid line 2, the fifth first fine grid line 2, etc. Similarly, when multiple second fine grid lines 3 are arranged sequentially, the arrangement order can be the first second fine grid line 3, the second second fine grid line 3, the third second fine grid line 3, the fourth second fine grid line 3, the fifth second fine grid line 3, etc. For instance, comparing the difference in maximum height between the first and second first fine grid lines 2 and the difference in maximum height between the first and second second fine grid lines 3, the difference in maximum height between the first and second second fine grid lines 3 is less than the difference in maximum height between the first and second first fine grid lines 2, and the difference in minimum height between the first and second second fine grid lines 3 is less than the difference in minimum height between the first and second first fine grid lines 2.

[0053] Alternatively, the height difference between the first and third fine grid lines 2 and the first and third fine grid lines 3 can be compared, or the height difference between the third and fifth fine grid lines 2 and the third and fifth fine grid lines 3 can be compared. This invention does not limit the comparison in this way. Depending on actual needs, the height values ​​of any two grid lines in the first fine grid lines 2 and any two grid lines in the second fine grid lines 3 can also be compared.

[0054] In this embodiment, since the difference in maximum height between two adjacent second fine gate lines 3 is less than the difference in maximum height between two adjacent first fine gate lines 2, and the difference in minimum height between two adjacent second fine gate lines 3 is less than the difference in minimum height between two adjacent first fine gate lines 2, the height variation of different second fine gate lines 3 is smaller than the height variation of different first fine gate lines 2. This makes the height of all second fine gate lines 3 more uniform than that of all first fine gate lines 2, which can further reduce the resistance of the second fine gate lines 3.

[0055] As one embodiment of this utility model, it also includes:

[0056] A P-type doped layer 4 is provided in P region 11, and a first fine gate line 2 is provided on the side of the P-type doped layer 4 away from the silicon wafer and in contact with the P-type doped layer 4.

[0057] An N-type doped layer 5 is disposed in N region 12, and a second fine gate line 3 is disposed on the side of the N-type doped layer 5 away from the silicon wafer 1 and in contact with the N-type doped layer 5.

[0058] Among them, the P-type doped layer 4 and the N-type doped layer 5 are one or a combination of at least two of the following: doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, and doped amorphous silicon.

[0059] The materials of the P-type doped layer 4 and the N-type doped layer 5 can be the same or different, depending on actual needs. The P-type doped layer 4 and the N-type doped layer 5 can be doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, or doped amorphous silicon. Preferably, both the P-type doped layer 4 and the N-type doped layer 5 are doped polycrystalline silicon. The P-type doped layer 4 is a P-type doped layer 4 doped with a P-type dopant, and the N-type doped layer 5 is an N-type doped layer 5 doped with an N-type dopant. The P-type dopant is a Group IIIA element dopant, and the N-type dopant is a Group VA element dopant. For example, the P-type dopant can be a boron dopant, and the N-type dopant can be a phosphorus dopant.

[0060] Please refer to this again. Figure 2 As an embodiment of the present invention, the width D1 of the first fine grid line 2 is greater than the width D2 of the second fine grid line 3.

[0061] In this embodiment, the width of the first fine gate line 2 is increased so that the width D1 of the first fine gate line 2 is greater than the width D2 of the second fine gate line 3. This increases the contact area between the first fine gate line 2 and the P-type doped layer 4, improves the contact performance, reduces the contact resistance of the P region 11, and further improves the battery efficiency.

[0062] In one embodiment of this utility model, the difference between the width D1 of the first fine gate line 2 and the width D2 of the second fine gate line 3 is 2 to 3 micrometers.

[0063] The specific widths of the first fine gate line 2 and the second fine gate line 3 can be set according to actual conditions. In this embodiment, by setting the difference between the width of the first fine gate line 2 and the width of the second fine gate line 3 to 2-3 micrometers, good contact performance between the first fine gate line 2 and the P-type doped layer 4 can be achieved, while avoiding the need for more paste and achieving lower costs.

[0064] As one embodiment of this utility model, it also includes:

[0065] The first main grid line 8 is connected to each of the first fine grid lines 2;

[0066] The second main grid line 9 is connected to each of the second fine grid lines 3.

[0067] In this embodiment, the first main gate line 8 is simultaneously arranged perpendicular to each of the first fine gate lines 2, and the first main gate line 8 collects the current of each of the first fine gate lines 2; the second main gate line 9 is simultaneously arranged perpendicular to each of the second fine gate lines 3, and the second main gate line 9 collects the current of each of the second fine gate lines 3, which facilitates current collection.

[0068] Specifically, the first fine grid line 2 and the second fine grid line 3 can be silver grid lines, aluminum grid lines, or copper grid lines. The first main grid line 8 and the second main grid line 9 can be silver grid lines, aluminum grid lines, or copper grid lines.

[0069] As one embodiment of this utility model, it also includes:

[0070] The tunneling oxide layer 6 is disposed between the P-type doped layer 4 and the silicon wafer 1 and between the N-type doped layer 5 and the silicon wafer 1.

[0071] In this embodiment, the tunneling oxide layer 6 acts as a tunneling and passivation layer on the surface of the silicon wafer 1, which can further improve the battery efficiency. The tunneling oxide layer 6 can be one or a combination of silicon oxide, aluminum oxide, and silicon oxynitride.

[0072] As one embodiment of this utility model, it also includes:

[0073] The back passivation film 7 is disposed on the side of the P-type doped layer 4 away from the silicon wafer 1 and the side of the N-type doped layer 5 away from the silicon wafer 1. The first fine gate line 2 passes through the back passivation film 7 and contacts the P-type doped layer 4, and the second fine gate line 3 passes through the back passivation film 7 and contacts the N-type doped layer 5.

[0074] In this embodiment, the back passivation film 7 is used to passivate and protect the back of the P-type doped layer and the N-type doped layer, which helps to further improve the battery efficiency. The back passivation film 7 can be a stack of one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide. For example, the back passivation film 7 may include aluminum oxide and silicon nitride stacked sequentially from the silicon wafer 1 away from the silicon wafer 1.

[0075] This utility model embodiment also provides a battery assembly, which includes the back-contact solar cell of the above embodiment. It should be noted that the battery assembly has the same or similar beneficial effects as the back-contact solar cell, and the related parts between the two can be referred to each other. To avoid repetition, they will not be described again here.

[0076] In this embodiment, multiple back-contact solar cells in the battery module can be connected in series to form a battery string, thereby achieving series current output. For example, the battery cells can be connected in series by setting solder strips (busbars, interconnecting strips), conductive backplates, etc.

[0077] It is understood that in such embodiments, the battery assembly may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back of the back-contact solar cell, the photovoltaic glass, adjacent cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0078] Photovoltaic glass can be applied to the encapsulating film on the front side of the back-contact solar cell. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cell while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the back-contact solar cell together, providing sealing, insulation, and waterproofing.

[0079] The backsheet can be attached to the adhesive film on the back of the back-contact solar cell. The backsheet protects and supports the back-contact solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, aluminum alloy TPT composite film, etc., and the specific choice depends on the specific circumstances and is not limited here. The backsheet, back-contact solar cell, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire solar cell module, providing stable support and installation. For example, the solar cell module can be installed at the desired location using the metal frame.

[0080] This utility model embodiment also provides a photovoltaic system, which includes the battery module of the above embodiment. It should be noted that this photovoltaic system has the same or similar beneficial effects as the back-contact solar cell described above, and the related parts between the two can be referred to each other. To avoid repetition, they will not be described again here.

[0081] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple solar cell modules; for example, multiple solar cell modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0082] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon wafer, the back side of which includes P-regions and N-regions arranged alternately in sequence; The first fine grid line is located in the P region; The second fine gate line is located in the N region; Wherein, the maximum height of the second fine gate line and the minimum height of the second fine gate line have a first height difference, the maximum height of the first fine gate line and the minimum height of the first fine gate line have a second height difference, and the first height difference is less than the second height difference.

2. The back-contact solar cell according to claim 1, characterized in that, The first height difference is less than or equal to 1 micrometer; the second height difference is less than or equal to 2.1 micrometers.

3. The back-contact solar cell according to claim 1, characterized in that, The height of the first fine gate line is 5.6 to 7.7 micrometers, and the height of the second fine gate line is 5.8 to 6.8 micrometers.

4. The back-contact solar cell according to claim 1, characterized in that, The difference in maximum height between two adjacent second fine grid lines is less than the difference in maximum height between two adjacent first fine grid lines, and the difference in minimum height between two adjacent second fine grid lines is less than the difference in minimum height between two adjacent first fine grid lines.

5. The back-contact solar cell according to claim 1, characterized in that, The width of the first fine gate line is greater than the width of the second fine gate line.

6. The back-contact solar cell according to claim 5, characterized in that, The difference between the width of the first fine gate line and the width of the second fine gate line is 2 to 3 micrometers.

7. The back-contact solar cell according to claim 1, characterized in that, Also includes: A P-type doped layer is provided in the P region, and the first fine gate line is provided on the side of the P-type doped layer away from the silicon wafer and in contact with the P-type doped layer; An N-type doped layer is disposed in the N region, and the second fine gate line is disposed on the side of the N-type doped layer away from the silicon wafer and in contact with the N-type doped layer.

8. The back-contact solar cell according to claim 7, characterized in that, Also includes: A tunneling oxide layer is disposed between the P-type doped layer and the silicon wafer, and between the N-type doped layer and the silicon wafer.

9. A battery assembly, characterized in that, Including the back-contact solar cell as described in any one of claims 1 to 8.

10. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 9.

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