Pixel circuit

Abstract

The utility model discloses a pixel circuit. The pixel circuit comprises a first light-emitting control module used for being switched on or switched off according to a first light-emitting control signal; the second light-emitting control module is used for being switched on or switched off according to the second light-emitting control signal; the threshold compensation module is used for compensating the threshold voltage of the driving module according to the first scanning signal; the data voltage write-in module is used for transmitting data voltage to the first end of the first storage module through the first leakage suppression module according to a second scanning signal; the first initialization module is used for resetting the voltage of the first end of the first electric leakage suppression module to a first initialization voltage according to a first scanning signal; the reset module is also used for resetting the voltage of the first end of the second leakage suppression module to a second initialization voltage according to a third scanning signal; the first electric leakage suppression module and the second electric leakage suppression module are used for being switched on or switched off according to the fourth scanning signal. According to the utility model, a lower screen refresh rate and a higher screen refresh rate can be compatible.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a pixel circuit. Background Technology

[0002] Organic light-emitting diode (OLED) display technology, as a new type of display technology, has many advantages that other display technologies cannot match, such as wide viewing angle, wide color gamut, high contrast, low power consumption, and foldability, making it highly competitive in the display field.

[0003] With the continuous development of display technology, the market demand for screen refresh rates is getting higher and higher. Low refresh rates and high refresh rates have different applicable scenarios. Currently, the pixel circuits in display technology can only be compatible with one or a few refresh rates, which cannot meet market demand. Utility Model Content

[0004] This invention provides a pixel circuit to solve the problem that current pixel circuits can only be compatible with a single or a few refresh rates, thus failing to meet market demands.

[0005] According to one aspect of the present invention, a pixel circuit is provided, the pixel circuit comprising: a first light emission control module, a driving module, a second light emission control module, a light emission module, a first initialization module, a data voltage writing module, a threshold compensation module, a first storage module, a second storage module, a first leakage current suppression module, and a second leakage current suppression module;

[0006] The first light-emitting control module is connected to the first power line and the first end of the drive module, and is used to turn on or off according to the first light-emitting control signal; the second light-emitting control module is connected to the second end of the drive module and the first end of the light-emitting module, and is used to turn on or off according to the second light-emitting control signal; the light-emitting module is connected between the second light-emitting control module and the second power line.

[0007] The threshold compensation module is connected to the second terminal of the drive module and the first terminal of the second leakage current suppression module, and is used to compensate the threshold voltage of the drive module according to the first scan signal.

[0008] The data voltage writing module is connected to the first end of the first leakage current suppression module and the data line. The second end of the first leakage current suppression module is connected to the first end of the first storage module. The second end of the first storage module is connected to the first power line. The data voltage writing module is used to transmit the data voltage through the first leakage current suppression module to the first end of the first storage module according to the second scan signal.

[0009] The first initialization module is connected to the first terminal of the first leakage current suppression module, the first terminal of the second leakage current suppression module, the first initialization signal line, and the second initialization signal line. It is used to reset the voltage of the first terminal of the first leakage current suppression module to the first initialization voltage according to the first scan signal; and is also used to reset the voltage of the first terminal of the second leakage current suppression module to the second initialization voltage according to the third scan signal.

[0010] The second end of the second leakage current suppression module is connected to the first end of the second storage module and the control end of the drive module, and the second end of the second storage module is connected to the first end of the first storage module; the first leakage current suppression module and the second leakage current suppression module are used to turn on or off according to the fourth scan signal.

[0011] The technical solution of this utility model separates the threshold voltage compensation stage and the data voltage writing stage of the pixel circuit, and the duration of the threshold voltage compensation stage is longer than the scanning time of one line, increasing the charging time of the second storage module and achieving a higher screen refresh rate. Furthermore, the first and second leakage current suppression modules can effectively reduce the leakage current of the pixel circuit, achieving a lower screen refresh rate. The pixel circuit provided by this utility model is compatible with both lower and higher screen refresh rates, meeting market demands for screen refresh rates.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0022] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0024] Figure 11 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the pixel circuit includes: a first light-emitting control module 1, a driving module 2, a second light-emitting control module 3, a light-emitting module 4, a first initialization module 9, a data voltage writing module 8, a threshold compensation module 5, a first storage module 10, a second storage module 11, a first leakage current suppression module 6, and a second leakage current suppression module 7. The first light-emitting control module 1 is connected to the first power line ELVDD and the first end of the driving module 2, and is used to turn on or off according to the first light-emitting control signal. The second light-emitting control module 3 is connected to the second end of the driving module 2 and the first end of the light-emitting module 4, and is used to turn on or off according to the second light-emitting control signal. The light-emitting module 4 is connected between the second light-emitting control module 3 and the second power line ELVSS. The threshold compensation module 5 is connected to the second end of the driving module 2 and the first end of the second leakage current suppression module 6, and is used to compensate the threshold voltage of the driving module 2 according to the first scan signal. The data voltage writing module 8 is connected to the first terminal of the first leakage current suppression module 7 and the data line Data. The second terminal of the first leakage current suppression module 7 is connected to the first terminal of the first storage module 10. The second terminal of the first storage module 10 is connected to the first power line ELVDD. The data voltage writing module 8 is used to transmit the data voltage through the first leakage current suppression module 7 to the first terminal of the first storage module 10 according to the second scan signal. The first initialization module 9 is connected to the first terminal of the first leakage current suppression module 7, the first terminal of the second leakage current suppression module 6, the first initialization signal line Vint1, and the second initialization signal line Vint2. It is used to reset the voltage of the first terminal of the first leakage current suppression module 7 to the first initialization voltage according to the first scan signal; it is also used to reset the voltage of the first terminal of the second leakage current suppression module 6 to the second initialization voltage according to the third scan signal. The second terminal of the second leakage current suppression module 6 is connected to the first terminal of the second storage module 11 and the control terminal G of the drive module 2. The second terminal of the second storage module 11 is connected to the first terminal of the first storage module 10. The first leakage current suppression module 7 and the second leakage current suppression module 6 are used to turn on or off according to the fourth scan signal.

[0028] Specifically, the operation of the pixel circuit provided in this embodiment of the present invention may include a first initialization stage, a threshold voltage compensation stage, a data voltage writing stage, and a light emission stage. In the first initialization stage, the first initialization module 9 responds to the third scan signal on the third scan line SN_2 of its second control terminal being turned on, resetting the voltage at the first terminal of the second leakage current suppression module 6 to the second initialization voltage on the second initialization signal line Vint2. At the same time, the second leakage current suppression module 6 responds to the fourth scan signal on the fourth scan line EM_OX of its control terminal being turned on, resetting the voltage at the first terminal of the second storage module 11 and the voltage at the control terminal G of the driving module 2 to the second initialization voltage.

[0029] During the threshold voltage compensation phase, the first initialization module 9 responds to the first scan signal on the first scan line SN_1 of its first control terminal being turned on, resetting the voltage at the first terminal of the first leakage current suppression module 7 to the first initialization voltage on the first initialization signal line Vint1. Simultaneously, the first leakage current suppression module 7 responds to the fourth scan signal on the fourth scan line EM_OX of its control terminal being turned on, resetting the voltage at the first terminal of the first storage module 10 to the first initialization voltage on the first initialization signal line Vint1. The first light emission control module 1 responds to the first light emission control signal on the first light emission control line EM_T4 of its control terminal being turned on. Since the control terminal G of the driving module 2 is reset to the second initialization voltage, the driving module 2 is turned on. The threshold compensation module 5 is activated in response to the first scan voltage on the first scan line SN_1 of its control terminal, and the second leakage suppression module 6 is activated in response to the fourth scan signal on the fourth scan line EM_OX of its control terminal. The first power supply voltage on the first power line ELVDD is charged to the first terminal of the second storage module 11 through the first light emission control module 1, the driving module 2, the threshold compensation module 5, and the second leakage suppression module 6. The voltage charged to the first terminal of the second storage module 11 is the sum of the first power supply voltage and the threshold voltage Vth. The duration of the threshold voltage compensation stage is longer than the scan time of one line, which increases the charging time of the second storage module 11 and enables a high refresh rate for the screen. For example, a high refresh rate of not less than 240Hz can be achieved.

[0030] During the data voltage writing phase, the data voltage writing module 8 is activated in response to the second scan signal on the second scan line SN_T1 of its control terminal, and the first leakage current suppression module 7 is activated in response to the fourth scan signal on the fourth scan line EM_OX of its control terminal. The data voltage writing module 8 transmits the data voltage on the data line Data to the first terminal of the first storage module 10 through the first leakage current suppression module 7. The voltage at the first terminal of the first storage module 10 changes from the first initialization voltage to the data voltage, causing the voltage at the first terminal of the second storage module 11 to become the first power supply voltage plus the threshold voltage Vth, plus the data voltage, minus the first initialization voltage.

[0031] During the light-emitting phase, the first light-emitting control module 1 is activated in response to the first light-emitting control signal on its first light-emitting control line EM_T4. The voltage at the first terminal of the second storage module 11 is maintained at the control terminal G of the driving module 2, and the driving module 2 is activated. The second light-emitting control module 3 is activated in response to the second light-emitting control signal on its second light-emitting control line EM_T5. The light-emitting module 4 can be a current-driven element. A path is formed between the first power line ELVDD and the second power line ELVSS. The driving current output by the driving module 2 flows through the light-emitting module 4, and the light-emitting module 4 emits light normally, realizing the display of the image. The first power supply voltage on the first power line ELVDD can be a positive voltage, and the second power supply voltage on the second power line ELVSS can be a negative voltage. The formula for calculating the driving current output by the driving module 2 is:

[0032]

[0033] Where I is the drive current output by drive module 2, Vgs is the voltage difference between the control terminal G of drive module 2 and the first terminal of drive module 2, and V G V1 is the voltage at the control terminal G of drive module 2, Vth is the first power supply voltage, and Vth is the threshold voltage of drive module 2. Data The data voltage is Vin1, which is the first initialization voltage.

[0034] The first leakage current suppression module 6 and the second leakage current suppression module 7 can effectively reduce the leakage current of the pixel circuit during the first initialization stage, the threshold voltage compensation stage, the data voltage writing stage, and the light emission stage.

[0035] The technical solution of this embodiment separates the threshold voltage compensation stage and the data voltage writing stage of the pixel circuit, and the duration of the threshold voltage compensation stage is longer than the scan time of one line, increasing the charging time of the second storage module and achieving a higher screen refresh rate. Furthermore, the first and second leakage current suppression modules can effectively reduce the leakage current of the pixel circuit, achieving a lower screen refresh rate. The pixel circuit provided by this embodiment can be compatible with both lower and higher screen refresh rates, meeting market demands for screen refresh rates.

[0036] Optionally, based on the above embodiments, Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 2As shown, the pixel circuit also includes a voltage reset module 12 and a second initialization module 13. The voltage reset module 12 is connected to the first terminal of the driving module 2 and the first voltage signal line Vint3, and is used to reset the voltage at the first terminal of the driving module 2 to the first voltage according to the fifth scan signal. The second initialization module 13 is connected to the first terminal of the light-emitting module 4 and the third initialization signal line Vint4, and is used to reset the voltage at the first terminal of the light-emitting module 4 to the third initialization voltage according to the fifth scan signal.

[0037] Specifically, between the data voltage writing stage and the light emission stage, the pixel circuit operation also includes a voltage reset stage and a second initialization stage, which are performed simultaneously. The second initialization module 13 responds to the fifth scan signal on its control terminal's fifth scan line SN+1 by resetting the voltage at the first terminal of the light emission module 4 to the third initialization voltage on the third initialization signal line Vint4. For example, the light emission module 4 can be a light-emitting diode (LED), and the first terminal of the light emission module 4 can be the anode of the LED. The second initialization module 13 initializes the anode of the LED.

[0038] The voltage reset module 12 responds to the fifth scan signal on the fifth scan line SN+1 of its control terminal being turned on, resetting the voltage at the first terminal of the drive module 2 to the first voltage on the first voltage signal line Vint3, thereby resetting the difference between the voltage at the first terminal of the drive module 2 and the voltage at the control terminal G. By setting the voltage reset module 12, the first leakage suppression module 7, and the second leakage suppression module 6, a lower screen refresh rate can be achieved. For example, the pixel circuit provided in this embodiment can achieve a screen refresh rate of 1Hz.

[0039] Optionally, based on the above embodiments, Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the first leakage current suppression module 7 includes a first transistor T1, and the second leakage current suppression module 6 includes a second transistor T2. The gate of the first transistor T1 is connected to a fourth scan signal. The first terminal of the first transistor T1 is connected to the first terminal of the data voltage writing module 8 and the first terminal of the first initialization module 9. The second terminal of the first transistor T1 is connected to the first terminal of the first storage module 10. The gate of the second transistor T2 is connected to the fourth scan signal. The first terminal of the second transistor T2 is connected to the first terminal of the threshold compensation module 5 and the second terminal of the first initialization module 9. The second terminal of the second transistor T2 is connected to the first terminal of the second storage module 11 and the control terminal G of the driving module 2. Both the first transistor T1 and the second transistor T2 are N-type transistors.

[0040] Specifically, the first leakage current suppression module 7 includes a first transistor T1, and the second leakage current suppression module 6 includes a second transistor T2, both of which are N-type transistors. For example, the first transistor T1 can be an indium gallium zinc oxide (IGZO) N-type transistor, and the second transistor T2 can also be an indium gallium zinc oxide (IGZO) N-type transistor. By setting the first transistor T1 and the second transistor T2 to N-type transistors, the leakage current of the pixel circuit can be effectively reduced during the first initialization stage, the threshold voltage compensation stage, the data voltage writing stage, and the light emission stage, thus achieving a lower screen refresh rate.

[0041] Optionally, based on the above embodiments, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the first light-emitting control module 1 includes a third transistor T3, the driving module 2 includes a fourth transistor T4, the second light-emitting control module 3 includes a fifth transistor T5, and the light-emitting module 4 includes a light-emitting diode D1. The gate of the third transistor T3 is connected to a first light-emitting control signal, the first terminal of the third transistor T3 is connected to the first power line ELVDD, and the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4. The gate of the fourth transistor T4 is connected to the second terminal of the second leakage suppression module 6 and the first terminal of the second storage module 11. The gate of the fifth transistor T5 is connected to a second light-emitting control signal, the first terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5 is connected to the anode of the light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second power line ELVSS.

[0042] Specifically, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors. The control terminal of the driving module 2 is the gate of the fourth transistor T4, and the gate of the fourth transistor T4 is connected to the second terminal of the second transistor T2 and the first terminal of the second storage module 11. The first terminal of the driving module 2 is the first terminal of the fourth transistor T4, which can be the source of the fourth transistor T4. The second terminal of the driving module 2 is the second terminal of the fourth transistor T4, which can be the drain of the fourth transistor T4.

[0043] During the luminescence stage, such as Figure 4As shown, the third transistor T3 and the fifth transistor T5 are both P-type transistors. The first light-emitting control signal on the first light-emitting control line EM_T4 is at a low level, and the second light-emitting control signal on the second light-emitting control line EM_T5 is also at a low level. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned on, and a path is formed between the first power line ELVDD and the second power line ELVSS. The driving current output by the fourth transistor T4 flows through the light-emitting diode D1, and the light-emitting diode D1 emits light normally, realizing the display of the image.

[0044] Optionally, based on the above embodiments, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the data voltage writing module 8 includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the second scan signal, the first terminal of the sixth transistor T6 is connected to the first terminal of the first leakage suppression module 7, and the second terminal of the sixth transistor T6 is connected to the data line Data.

[0045] Specifically, the data voltage writing module 8 includes a sixth transistor T6, which can be a P-type transistor. The gate of the sixth transistor T6 is connected to the second scan line SN_T1, the first terminal of the sixth transistor T6 is connected to the first terminal of the first transistor T1, and the second terminal of the sixth transistor T6 is connected to the data line Data.

[0046] During the data voltage writing phase, such as Figure 5 As shown, the sixth transistor T6 is a P-type transistor. When the second scan signal on the second scan line SN_T1 is low, the sixth transistor T6 is turned on. When the fourth scan signal on the fourth scan line EM_OX is high, the first transistor T1 is turned on. The data voltage on the data line Data is transmitted to the first terminal of the first storage module 10 through the sixth transistor T6 and the first transistor T1.

[0047] Optionally, based on the above embodiments, Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the threshold compensation module 5 includes a seventh transistor T7. The gate of the seventh transistor T7 is connected to the first scan signal, the first terminal of the seventh transistor T7 is connected to the second terminal of the driving module 2, and the second terminal of the seventh transistor T7 is connected to the first terminal of the second leakage suppression module 6.

[0048] Specifically, the threshold compensation module 5 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the first scan line SN_1, the first terminal of the seventh transistor T7 is connected to the second terminal of the fourth transistor T4, and the second terminal of the seventh transistor T7 is connected to the first terminal of the second transistor T2.

[0049] During the threshold voltage compensation stage, such as Figure 6 As shown, the seventh transistor T7 is a P-type transistor. When the first scan line SN_1 is at a low level, the seventh transistor T7 is turned on. At the same time, the first light emission control signal on the first light emission control line EM_T4 is at a low level, and the fourth scan signal on the fourth scan line EM_OX is at a high level. The gate of the fourth transistor T4 is reset to the second initialization voltage during the first initialization phase. Therefore, the third transistor T3, the fourth transistor body T4, and the second transistor T2 are also turned on. The first power supply voltage on the first power supply line ELVDD charges the first terminal of the second storage module 11 through the third transistor T3, the fourth transistor body T4, the seventh transistor T7, and the second transistor T2. The voltage charged into the first terminal of the second storage module 11 is the sum of the first power supply voltage and the threshold voltage Vth.

[0050] Optionally, based on the above embodiments, Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the first initialization module 9 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is connected to a first scan signal, the first terminal of the eighth transistor T8 is connected to the first terminal of the first leakage current suppression module 7, and the second terminal of the eighth transistor T8 is connected to the first initialization signal line Vint1. The gate of the ninth transistor T9 is connected to a third scan signal, the first terminal of the ninth transistor T9 is connected to the first terminal of the second leakage current suppression module 6, and the second terminal of the ninth transistor T9 is connected to the second initialization signal line Vint2.

[0051] Specifically, the eighth transistor T8 and the ninth transistor T9 can both be P-type transistors. The gate of the eighth transistor T8 is connected to the first scan line SN_1, and the first terminal of the eighth transistor T8 is connected to the first terminal of the first transistor T1. The gate of the ninth transistor T9 is connected to the third scan line SN_2, and the first terminal of the ninth transistor T9 is connected to the first terminal of the second transistor T2.

[0052] In the first initialization phase, such as Figure 7 As shown, the ninth transistor T9 is a P-type transistor. When the third scan signal on the third scan line SN_2 is low, the ninth transistor T9 is turned on. At the same time, when the fourth scan signal on the fourth scan line EM_OX is high, the second transistor T2 is turned on. The voltage at the first terminal of the second storage module 11 and the voltage at the control terminal G of the fourth transistor T4 are reset to the second initialization voltage on the second initialization signal line Vint2.

[0053] During the threshold voltage compensation stage, such as Figure 7As shown, the eighth transistor T8 is a P-type transistor. When the first scan signal on the first scan line SN_1 is low, the eighth transistor T8 is turned on. At the same time, when the fourth scan signal on the fourth scan line EM_OX is high, the first transistor T1 is turned on, resetting the voltage at the first terminal of the first storage module 10 to the first initialization voltage on the first initialization signal line Vint1.

[0054] Optionally, based on the above embodiments, Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the first storage module 10 includes a first capacitor C1, and the second storage module 11 includes a second capacitor C2. The first terminal of the first capacitor C1 is connected to the second terminal of the first leakage current suppression module 7, and the second terminal of the first capacitor C1 is connected to the first power line ELVDD. The first terminal of the second capacitor C2 is connected to the second terminal of the second leakage current suppression module 6, and the second terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1.

[0055] Specifically, the first capacitor C1 is connected between the first power line ELVDD and the second terminal of the first transistor T1, and the second capacitor C2 is connected between the first terminal of the first capacitor C1 and the second terminal of the second transistor T2. The second capacitor C2 is used to store the voltage of the control terminal G of the drive module 2, that is, to store the voltage of the gate of the fourth transistor T4.

[0056] Optionally, based on the above embodiments, Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the voltage reset module 12 includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the fifth scan signal, the first terminal of the tenth transistor T10 is connected to the first terminal of the drive module 2, and the second terminal of the tenth transistor T10 is connected to the first voltage signal line Vint3.

[0057] Specifically, the voltage reset module 12 includes a tenth transistor T10, which can be a P-type transistor. The gate of the tenth transistor T10 is connected to the fifth scan line SN+1, the first terminal of the tenth transistor T10 is connected to the first terminal of the fourth transistor T4, and the second terminal of the tenth transistor T10 is connected to the first voltage signal line Vint3.

[0058] During the voltage reset phase, such as Figure 9As shown, the tenth transistor T10 is a P-type transistor. When the fifth scan signal on the fifth scan line SN+1 is low, the tenth transistor T10 is turned on, resetting the voltage at the first terminal of the fourth transistor T4 to the first voltage on the first voltage signal line Vint3. This resets the difference between the voltage at the first terminal and the gate voltage of the fourth transistor T4, i.e., resets the voltage difference between the gate and source of the fourth transistor T4. By setting the tenth transistor T10, the first transistor T1, and the second transistor T2, a lower screen refresh rate can be achieved. For example, the pixel circuit provided in this embodiment can achieve a screen refresh rate of 1Hz.

[0059] Optionally, based on the above embodiments, Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 10 As shown, the second initialization module 13 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is connected to the fifth scan signal, the first terminal of the eleventh transistor T11 is connected to the first terminal of the light-emitting module 4, and the second terminal of the eleventh transistor T11 is connected to the third initialization signal line Vint4.

[0060] Specifically, the eleventh transistor T11 can be a P-type transistor. The gate of the eleventh transistor T11 is connected to the fifth scan line SN+1, the first terminal of the eleventh transistor T11 is connected to the anode of the light-emitting diode D1, and the second terminal of the eleventh transistor T11 is connected to the third initialization signal line Vint4.

[0061] During the second initialization phase, the fifth scan signal on the fifth scan line SN+1 is at a low level, and the eleventh transistor T11 is turned on, resetting the voltage at the anode of the light-emitting diode D1 to the third initialization voltage on the third initialization signal line Vint4.

[0062] Figure 11 This is a driving timing diagram for a pixel circuit provided in an embodiment of the present invention, which can be applied to... Figure 10 The pixel circuit shown, combined with Figure 10 and Figure 11 right Figure 10 The working process of the pixel circuit will be explained:

[0063] During the first initialization phase t1, the first scan signal on the third scan line SN_2 and the first light emission control signal on the first light emission control line EM_T4 are at low levels, while the first scan signal on the first scan line SN_1, the second scan signal on the second scan line SN_T1, the fourth scan signal on the fourth scan line EM_OX, the fifth scan signal on the fifth scan line SN+1, and the second light emission control signal on the second light emission control line EM_T5 are at high levels. Therefore, the ninth transistor T9, the third transistor T3, the first transistor T1, and the second transistor T2 are turned on, and the remaining transistors are turned off, resetting the voltage at the first terminal of the second capacitor C2 and the voltage at the gate of the fourth transistor T4 to the second initialization voltage.

[0064] During the threshold voltage compensation stage t2, the first scan signal on the first scan line SN_1 and the first light emission control signal on the first light emission control line EM_T4 are at low levels, while the first scan signal on the third scan line SN_2, the second scan signal on the second scan line SN_T1, the fourth scan signal on the fourth scan line EM_OX, the fifth scan signal on the fifth scan line SN+1, and the second light emission control signal on the second light emission control line EM_T5 are at high levels. Therefore, the first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, the third transistor T3, and the fourth transistor T4 are turned on, and the remaining transistors are turned off. The voltage at the first terminal of the first capacitor C1 is reset to the first initialization voltage on the first initialization signal line Vint1. The first power supply voltage on the first power supply line ELVDD charges the first terminal of the second capacitor C2 through the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the second transistor T2. The voltage charged into the first terminal of the second capacitor C2 is the sum of the first power supply voltage and the threshold voltage Vth.

[0065] During the data voltage writing phase t3, the second scan signal on the second scan line SN_T1 and the first light emission control signal on the first light emission control line EM_T4 are at low levels, while the first scan signal on the first scan line SN_1, the first scan signal on the third scan line SN_2, the fourth scan signal on the fourth scan line EM_OX, the fifth scan signal on the fifth scan line SN+1, and the second light emission control signal on the second light emission control line EM_T5 are at high levels. Therefore, the first transistor T1, the second transistor T2, the sixth transistor T6, the third transistor T3, and the fourth transistor T4 are turned on, and the remaining transistors are turned off. The data voltage on the data line Data is transmitted to the first terminal of the first capacitor C1 through the first transistor T1. The voltage at the first terminal of the first capacitor C1 changes from the first initialization voltage to the data voltage, causing the voltage at the first terminal of the second capacitor C2 and the gate voltage of the fourth transistor T4 to become the first power supply voltage plus the threshold voltage Vth, plus the data voltage, and minus the first initialization voltage.

[0066] During the voltage reset phase and the second initialization phase t4, the fifth scan signal on the fifth scan line SN+1 and the fourth scan signal on the fourth scan line EM_OX are at low levels, while the first scan signal on the first scan line SN_1, the first scan signal on the third scan line SN_2, the second scan signal on the second scan line SN_T1, the first light emission control signal on the first light emission control line EM_T4, and the second light emission control signal on the second light emission control line EM_T5 are at high levels. Therefore, the tenth transistor T10, the eleventh transistor T11, and the fourth transistor T4 are turned on, and the remaining transistors are turned off. The voltage at the anode of the light-emitting diode D1 is reset to the third initialization voltage on the third initialization signal line Vint4, and the voltage at the first terminal of the fourth transistor T4 is reset to the first voltage on the first voltage signal line Vint3.

[0067] During the light-emitting stage t5, the first scan signal on the first scan line SN_1, the first scan signal on the third scan line SN_2, the second scan signal on the second scan line SN_T1, and the fifth scan signal on the fifth scan line SN+1 are at high levels. Conversely, the first light-emitting control signal on the first light-emitting control line EM_T4, the second light-emitting control signal on the second light-emitting control line EM_T5, and the fourth scan signal on the fourth scan line EM_OX are at low levels. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, while the remaining transistors are turned off. A path is formed between the first power line ELVDD and the second power line ELVSS. The driving current output by the fourth transistor T4 flows through the light-emitting diode D1, causing D1 to emit light normally, thus displaying the image.

[0068] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A pixel circuit, characterized in that, include: The system comprises a first light-emitting control module, a driving module, a second light-emitting control module, a light-emitting module, a first initialization module, a data voltage writing module, a threshold compensation module, a first storage module, a second storage module, a first leakage current suppression module, and a second leakage current suppression module. The first light-emitting control module is connected to the first power line and the first end of the driving module, and is used to turn on or off according to the first light-emitting control signal; the second light-emitting control module is connected to the second end of the driving module and the first end of the light-emitting module, and is used to turn on or off according to the second light-emitting control signal; the light-emitting module is connected between the second light-emitting control module and the second power line; The threshold compensation module is connected to the second terminal of the drive module and the first terminal of the second leakage current suppression module, and is used to compensate the threshold voltage of the drive module according to the first scan signal; The data voltage writing module is connected to the first end of the first leakage current suppression module and the data line. The second end of the first leakage current suppression module is connected to the first end of the first storage module. The second end of the first storage module is connected to the first power line. The data voltage writing module is used to transmit the data voltage through the first leakage current suppression module to the first end of the first storage module according to the second scan signal. The first initialization module is connected to the first terminal of the first leakage current suppression module, the first terminal of the second leakage current suppression module, the first initialization signal line, and the second initialization signal line, and is used to reset the voltage of the first terminal of the first leakage current suppression module to the first initialization voltage according to the first scan signal; and is also used to reset the voltage of the first terminal of the second leakage current suppression module to the second initialization voltage according to the third scan signal. The second end of the second leakage current suppression module is connected to the first end of the second storage module and the control end of the drive module, and the second end of the second storage module is connected to the first end of the first storage module; the first leakage current suppression module and the second leakage current suppression module are used to turn on or off according to the fourth scan signal.

2. The pixel circuit according to claim 1, characterized in that, Also includes: Voltage reset module and second initialization module; The voltage reset module is connected to the first terminal of the drive module and the first voltage signal line, and is used to reset the voltage of the first terminal of the drive module to the first voltage according to the fifth scan signal; The second initialization module is connected to the first terminal of the light-emitting module and the third initialization signal line, and is used to reset the voltage of the first terminal of the light-emitting module to the third initialization voltage according to the fifth scan signal.

3. The pixel circuit according to claim 1, characterized in that, The first leakage current suppression module includes a first transistor, and the second leakage current suppression module includes a second transistor; The gate of the first transistor is connected to the fourth scan signal, the first terminal of the first transistor is connected to the first terminal of the data voltage writing module and the first terminal of the first initialization module, and the second terminal of the first transistor is connected to the first terminal of the first storage module; the gate of the second transistor is connected to the fourth scan signal, the first terminal of the second transistor is connected to the first terminal of the threshold compensation module and the second terminal of the first initialization module, and the second terminal of the second transistor is connected to the first terminal of the second storage module and the control terminal of the driving module; both the first transistor and the second transistor are N-type transistors.

4. The pixel circuit according to claim 1, characterized in that, The first light-emitting control module includes a third transistor, the driving module includes a fourth transistor, the second light-emitting control module includes a fifth transistor, and the light-emitting module includes a light-emitting diode; The gate of the third transistor is connected to the first light-emitting control signal, the first terminal of the third transistor is connected to the first power line, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the gate of the fourth transistor is connected to the second terminal of the second leakage suppression module and the first terminal of the second storage module. The gate of the fifth transistor is connected to the second light-emitting control signal, the first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, the second terminal of the fifth transistor is connected to the anode of the light-emitting diode, and the cathode of the light-emitting diode is connected to the second power supply line.

5. The pixel circuit according to claim 1, characterized in that, The data voltage writing module includes a sixth transistor; The gate of the sixth transistor is connected to the second scan signal, the first terminal of the sixth transistor is connected to the first terminal of the first leakage current suppression module, and the second terminal of the sixth transistor is connected to the data line.

6. The pixel circuit according to claim 1, characterized in that, The threshold compensation module includes a seventh transistor; The gate of the seventh transistor is connected to the first scan signal, the first terminal of the seventh transistor is connected to the second terminal of the driving module, and the second terminal of the seventh transistor is connected to the first terminal of the second leakage suppression module.

7. The pixel circuit according to claim 1, characterized in that, The first initialization module includes an eighth transistor and a ninth transistor; The gate of the eighth transistor is connected to the first scan signal, the first terminal of the eighth transistor is connected to the first terminal of the first leakage current suppression module, and the second terminal of the eighth transistor is connected to the first initialization signal line; the gate of the ninth transistor is connected to the third scan signal, the first terminal of the ninth transistor is connected to the first terminal of the second leakage current suppression module, and the second terminal of the ninth transistor is connected to the second initialization signal line.

8. The pixel circuit according to claim 1, characterized in that, The first storage module includes a first capacitor, and the second storage module includes a second capacitor; The first terminal of the first capacitor is connected to the second terminal of the first leakage current suppression module, and the second terminal of the first capacitor is connected to the first power line; the first terminal of the second capacitor is connected to the second terminal of the second leakage current suppression module, and the second terminal of the second capacitor is connected to the first terminal of the first capacitor.

9. The pixel circuit according to claim 2, characterized in that, The voltage reset module includes a tenth transistor; The gate of the tenth transistor is connected to the fifth scan signal, the first terminal of the tenth transistor is connected to the first terminal of the driving module, and the second terminal of the tenth transistor is connected to the first voltage signal line.

10. The pixel circuit according to claim 2, characterized in that, The second initialization module includes an eleventh transistor; The gate of the eleventh transistor is connected to the fifth scan signal, the first terminal of the eleventh transistor is connected to the first terminal of the light-emitting module, and the second terminal of the eleventh transistor is connected to the third initialization signal line.

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