Power semiconductor packaging structure

Abstract

The utility model provides a power semiconductor packaging structure. The power semiconductor packaging structure comprises a substrate, a plurality of chip sets, a first terminal and a packaging body. The substrate is provided with a first surface and a second surface which are oppositely arranged; the plurality of chip sets are arranged on the first surface of the substrate, and each chip set comprises a plurality of chips which are arranged at intervals and are connected with the substrate; the first terminal comprises a connecting section and a leading-out section, the connecting section comprises a head end connecting part, a tail end connecting part and a plurality of cantilevers arranged at intervals, the head end connecting part is connected with the leading-out section, and each cantilever is located between the head end connecting part and the tail end connecting part; each cantilever comprises a plurality of concave parts arranged at intervals and a convex part located between every two adjacent concave parts, and the plurality of concave parts of each cantilever are respectively connected with the plurality of chips of the corresponding chip set; the packaging body packages at least part of the substrate, the plurality of chip sets and the connecting sections of the first terminals, and the leading-out sections of the first terminals are exposed out of the packaging body.

Description

Technical Field

[0001] This utility model relates to the field of electronic device technology, and in particular to a power semiconductor packaging structure. Background Technology

[0002] In power semiconductor packaging structures, the package is typically used to house and protect chips with different functions made of different semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). These chips can be configured into various device types, such as microprocessors, discrete devices, amplifiers, controllers, and sensors. In power semiconductor packaging structures, the chip is mounted on a substrate, and the package typically uses electrically insulating encapsulating materials such as plastic, resin, or ceramic to seal and protect the chip from moisture and dust particles, and to connect the conductive terminals to the chip's pads and partially extend out of the package for external access.

[0003] Currently, the power density requirements of commonly used power semiconductor packaging structures are increasing, and the current requirements that a single power semiconductor packaging structure can carry are also increasing. Therefore, higher requirements are placed on the electrical reliability, current carrying capacity, insulation performance and safety performance of power semiconductor packaging structures. Utility Model Content

[0004] In view of this, this utility model embodiment provides a power semiconductor packaging structure in order to effectively improve its current carrying capacity.

[0005] Specifically, an embodiment of this utility model provides a power semiconductor packaging structure, which includes, for example, a substrate, multiple chip groups, a first terminal, a second terminal, and a package body. The substrate has a first surface and a second surface disposed opposite to each other. The multiple chip groups are disposed on the first surface of the substrate, wherein the multiple chip groups are spaced apart in a third direction perpendicular to a first direction, the first direction being the direction from the first surface to the second surface. Each chip group includes M chips spaced apart in a second direction perpendicular to both the first direction and the third direction, where M is an integer greater than 1. The surface of each chip facing away from the first surface of the substrate is provided with a first electrode pad. The first terminal includes a first connecting segment and a first lead-out segment. The first connecting segment includes a head connecting portion, a tail connecting portion, and a plurality of cantilevers spaced apart in the third direction. The head connecting portion is connected to the first lead-out segment. Each cantilever is located between the head connecting portion and the tail connecting portion in the second direction. Each cantilever includes M recesses spaced apart in the second direction and a protrusion located between every two adjacent recesses. Each protrusion connects to two adjacent recesses on opposite sides in the second direction. The plurality of cantilevers correspond one-to-one with the plurality of chipsets. The M recesses of each cantilever are respectively connected to the first electrode pads of the M chips in the corresponding chipset. The recess of each cantilever closest to the head connecting portion is connected to the head connecting portion, and the recess of each cantilever closest to the tail connecting portion is connected to the tail connecting portion. The package encapsulates at least a portion of the substrate, the plurality of chipsets, and the first connecting segment of the first terminal, with the first lead-out segment of the first terminal exposed outside the package.

[0006] The above embodiments of this utility model have the following beneficial effects: The power semiconductor packaging structure of this utility model integrates multiple chipsets into the same package, which can increase the current carrying capacity, especially effective for the current situation of low yield of large-area chips using SiC material; In addition, for the first connection segment of the first terminal, since its multiple cantilever is provided with recessed portions at the connection with each chip and adjacent two recessed portions are connected by protrusions, that is, a sunken design is adopted, which makes the adjacent chips connected in an arch shape, which can effectively avoid the short circuit problem caused by the small distance between the first terminal and the first surface of the substrate under the coplanar connection design; Combined with the configuration of the first end connection portion and the last end connection portion, it increases the structural stability of the first terminal and improves the current sharing effect among multiple chips. In short, by setting multiple chipsets and performing specific structural design on the first terminal, the current carrying capacity of the power semiconductor packaging structure of this utility model is improved and guaranteed, achieving the purpose of effectively improving the current carrying capacity. Attached Figure Description

[0007] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0008] Figure 1 This is a three-dimensional structural diagram of a power semiconductor packaging structure provided in an embodiment of the present utility model.

[0009] Figure 2 for Figure 1 The diagram shows a three-dimensional view of the power semiconductor package structure from another perspective.

[0010] Figure 3A for Figure 1 The diagram shows a three-dimensional structural schematic of one embodiment of the power semiconductor package structure after the package body has been removed.

[0011] Figure 3B for Figure 1 The diagram shows a three-dimensional structural schematic of another embodiment of the power semiconductor package structure after removing the package body.

[0012] Figure 4 for Figure 3A A partial side view of the structure shown.

[0013] Figure 5 for Figure 4 A partially enlarged schematic diagram of the structure shown.

[0014] Figure 6 for Figure 3A A partially enlarged schematic diagram of the structure shown.

[0015] Figure 7 for Figure 1 The diagram shows a top view of the insulating layer and the current-passing layer of the substrate in the power semiconductor package structure.

[0016] Figure 8 for Figure 3A A top view of a portion of the structure shown.

[0017] Figure 9 for Figure 1 The diagram shows a left-side view of the power semiconductor package structure.

[0018] Figure 10 for Figure 1 The diagram shows a rear view of the power semiconductor package structure.

[0019] Figure 11 for Figure 10 A partially enlarged schematic diagram of the structure shown.

[0020] Figure 12 This is a three-dimensional structural diagram of another power semiconductor packaging structure provided in an embodiment of the present invention, omitting the package body.

[0021] [Explanation of Labels in the Attached Image]

[0022] 10-Power semiconductor package structure, 11-Substrate, 110-Insulating layer, 112-Current flow layer, 1121-Power region, 1122-Trench, 1123-Drive region, 1123a, 1123c-Ends, 1123b-Middle portion, 1123u-Recess, 1125-Another drive region, 1125n-Protrusion, 114-Heat dissipation layer, 11T-First surface of substrate, 11B-Second surface of substrate, 12-Resistor, 13-Chip, S-First electrode pad, D-Second electrode pad, G-Third electrode pad, 141, 142, 143-Connecting material, 15-Package body, SW1-First sidewall, SW2-Second sidewall, SW21-First... Side wall section, SW3-third side wall, SW4-fourth side wall, 15T-top surface, 15B-bottom surface, 151-annular boss, 151S-end face of annular boss, 16-first terminal, 161-first connecting section, 1611-first end connecting part, 1612-second inclined connecting part, 1613-cantilever, 1613a-recess, 1613b-protrusion, 1613g-through groove, 1613U-top surface of cantilever, 1613L-bottom surface of cantilever, 1614-first inclined connecting part, 1615-end connecting part, 1616-moisture blocking groove, 1617-intermediate connecting part, 163-first lead-out section, 163B-lower surface of first lead-out section, 16 3S - End face of the first lead-out section, 17 - Second terminal, 171 - Second connecting section, 171T - Upper surface of the second connecting section, 171B - Lower surface of the second connecting section, 1710 - Toothed structure, 1710a - Protruding structure, h1 - Protrusion height, 1710c - Recessed structure, h2 - Recess depth, 1712 - Mold-locking hole, 1716 - Moisture-blocking groove, 173 - Second lead-out section, 173T - Third surface, 173B - Fourth surface, 173a - Front transverse portion, 173b - First bending portion, 173c - Middle transverse portion, 173d - Second bending portion, 173e - Rear transverse portion, 18 - Third terminal, 183 - Second longitudinal portion, 183 a - Second lower parallel portion, 183b - Second arc-shaped portion, 183c - Second upper parallel portion, R - Radius, 19 - Fourth terminal, 193 - First longitudinal portion, 193a - First lower parallel portion, 193b - First arc-shaped portion, 193c - First upper parallel portion, A1 - First direction, A2 - Second direction, A3 - Third direction, BW - Metal bonding line, W0, W1, W2 - Width, t1, t2 - Thickness, W4, W5 - Maximum width, h4 - Height, h3 - Distance, K - Width, L - Width, d1, d2, d3, d4, d5, d6, d7, d8, d10 - Distance, d9 - Width, β - Included angle, θ - Included angle, α - Bending angle. Detailed Implementation

[0023] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0024] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] It should also be noted that the division of multiple embodiments in this utility model is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0027] Specifically, this utility model provides a power semiconductor packaging structure, comprising: a substrate having a first surface and a second surface disposed opposite to each other; a plurality of chip groups disposed on the first surface of the substrate, wherein the plurality of chip groups are spaced apart in a third direction perpendicular to a first direction, the first direction being the direction from the first surface to the second surface, each chip group comprising M chips spaced apart in a second direction perpendicular to both the first direction and the third direction, where M is an integer greater than 1, and a first electrode pad disposed on the surface of each chip facing away from the first surface of the substrate; a first terminal comprising a first connection segment and a first lead segment, the first connection segment comprising a head connection portion, a tail connection portion and a plurality of cantilever arms spaced apart in the third direction, the head connection portion being connected to the first lead segment, and each cantilever arm being positioned in the second direction. Between the first end connection portion and the last end connection portion, each cantilever includes M recesses spaced apart in the second direction and a protrusion located between every two adjacent recesses. Each protrusion connects to two adjacent recesses on opposite sides in the second direction. The plurality of cantilever portions correspond one-to-one with the plurality of chipsets. The M recesses of each cantilever portion are respectively connected to the first electrode pads of the M chips of the corresponding chipset. The recess of each cantilever portion closest to the first end connection portion is connected to the first end connection portion, and the recess of each cantilever portion closest to the last end connection portion is connected to the last end connection portion. A package encapsulates at least a portion of the substrate, the plurality of chipsets, and a first connection segment of the first terminal, with the first lead-out segment of the first terminal exposed outside the package.

[0028] In some embodiments, the end connection portion is spaced apart from the recessed portion closest to the end connection portion of each cantilever in the first direction and the second direction; the first connection segment further includes a plurality of first inclined connection portions, the plurality of first inclined connection portions corresponding one-to-one with the plurality of cantilever, one end of each first inclined connection portion being connected to the recessed portion closest to the end connection portion of the corresponding cantilever, and the other end of each first inclined connection portion extending in a direction away from the first surface of the substrate and being connected to the end connection portion.

[0029] In some embodiments, the first end connection portion is spaced apart from the recessed portion closest to the first end connection portion of each cantilever in the first direction and the second direction; the first connection segment further includes a plurality of second inclined connection portions, the plurality of second inclined connection portions corresponding one-to-one with the plurality of cantilever, one end of each second inclined connection portion is connected to the recessed portion closest to the first end connection portion of the corresponding cantilever, and the other end of each second inclined connection portion extends in a direction away from the first surface of the substrate and is connected to the first end connection portion.

[0030] In some embodiments, the substrate includes an insulating layer and a current-passing layer disposed on the insulating layer, the plurality of chipsets are located on the side of the current-passing layer opposite to the insulating layer; at least one chip in the plurality of chipsets has a third electrode pad disposed on the surface opposite to the substrate; the current-passing layer includes a power region and a driving region spaced apart from each other in the second direction, a single trench is disposed between the power region and the driving region; the area of ​​the power region is larger than the area of ​​the driving region; the plurality of chipsets are disposed in the power region, the driving region has at least one resistor, the power semiconductor package structure further includes a third terminal, the third terminal is connected to the driving region via metal bonding wires, and the third electrode pads of at least one chip are connected one-to-one to the surface of the at least one resistor opposite to the current-passing layer via metal bonding wires.

[0031] In some embodiments, the area ratio of the power region to the driving region is greater than 8.

[0032] In some embodiments, in the second direction, the width of the trench is 0.4 mm to 1.6 mm; in the first direction, the thickness of the flow-through layer is 0.5 mm to 1 mm, and the thickness of the insulating layer is 0.25 mm to 0.64 mm.

[0033] In some embodiments, in the third direction, the drive region includes a middle portion and two ends extending from the middle portion to opposite ends in a gradually widening manner, and the side of the power region closest to the drive region protrudes toward the middle portion of the drive region.

[0034] In some embodiments, the ratio of the maximum width of each end portion to the maximum width of the middle portion is greater than 1.5.

[0035] In some embodiments, the two ends are respectively used as bonding regions; the plurality of chipsets include a first chipset and a second chipset, wherein the third electrode pad is disposed on the surface of each chip in the first chipset that is away from the first surface of the substrate, and the third electrode pad is disposed on the surface of each chip in the second chipset that is away from the first surface of the substrate; in the third direction, the third electrode pad of each chip in the first chipset is located on the side of the first chipset away from the second chipset and is connected to one end of the two ends by a metal bonding wire, and the third electrode pad of each chip in the second chipset is located on the side of the second chipset away from the first chipset and is connected to the other end of the two ends by a metal bonding wire.

[0036] In some embodiments, the power semiconductor package structure further includes a second terminal and a fourth terminal, and the substrate further includes a heat dissipation layer disposed on the side of the insulating layer away from the current-passing layer; the package includes a first sidewall and a second sidewall disposed opposite to and spaced apart in the second direction; the first lead-out segment extends from the first sidewall of the package and is exposed outside the package; the fourth terminal is formed extending from the end of the first connecting segment near the first lead-out segment in a direction away from the first connecting segment and is spaced apart from the first lead-out segment in the third direction; the fourth terminal is integral with the first connecting segment and the first lead-out segment; the second terminal includes a second lead-out segment extending from the second sidewall of the package and exposed outside the package and a second connecting segment encapsulated within the package; the second connecting segment connects to the current-passing layer of the substrate; the package encapsulates the insulating layer, the current-passing layer, a portion of the second terminal, a portion of the third terminal, and a portion of the fourth terminal, and exposes at least a portion of the surface of the heat dissipation layer away from the insulating layer.

[0037] To facilitate a clearer understanding of the power semiconductor packaging structure of this utility model, a more detailed description is provided below in conjunction with the accompanying drawings.

[0038] See Figure 1 , Figure 2 and Figure 3A The present invention provides a power semiconductor packaging structure 10, which includes, for example, a substrate 11, a chip 13, a package body 15, a first terminal 16, and a second terminal 17. The number of chips 13 may be one or more. Figure 3A The four examples shown are merely illustrative.

[0039] In some embodiments, see Figures 1 to 5The substrate 11 has a first surface 11T and a second surface 11B disposed opposite to each other. The chip 13 is disposed on the first surface 11T of the substrate 11. A first electrode pad S is disposed on the surface of the chip 13 facing away from the substrate 11, and a second electrode pad D is disposed on the surface of the chip 13 facing the substrate 11. The second electrode pad D is connected to the first surface 11T of the substrate 11. The package 15 at least encloses the first surface 11T of the substrate 11 and the chip 13. The second surface 11B of the substrate 11 is partially or completely exposed outside the package 15. The first terminal 15 can serve as a current input / output terminal, and for example includes a first connection segment 161 and a first lead segment 163 connected to the first connection segment 161. The first connection segment 161 is enclosed within the package 15 and connected to the first electrode pad S of the chip 13. The first lead segment 163 is exposed outside the package 15. The second terminal 17 can serve as a current lead-out / lead-in terminal, and for example includes a second connection segment 171 and a second lead-out segment 173 connected to the second connection segment 171. The second connection segment 171 is enclosed within the package 15 and connected, for example, to the substrate 11, while the second lead-out segment 173 is exposed outside the package 15. Furthermore, it is worth mentioning that in other embodiments, the second electrode pad D can also be disposed on the surface of the chip 13 facing away from the substrate 11, and the second electrode pad D and the second terminal 17 can be connected accordingly via metal bonding wires.

[0040] In some embodiments, see Figure 3A , Figure 4 and Figure 5 The second electrode pad D is connected to the first surface 11T of the substrate 11 via a connecting material 142. The connecting material 142 can be a welding material, such as high-performance welding materials like SnSb5 or SAC305, which can be welded in the form of solder sheets or solder paste, with a thickness of, for example, 50-200 micrometers (μm); or the connecting material 142 can be a sintering material, such as Ag or Cu, which forms a high-performance connecting layer after sintering, with a thickness of, for example, 20-50 μm.

[0041] In some embodiments, see Figure 3A , Figure 4 and Figure 6The second connecting segment 171 has a lower surface 171B facing the first surface 11T of the substrate 11 and an upper surface 171T facing away from the first surface 11T of the substrate 11. The lower surface 171B of the second connecting segment 171 is connected to the substrate 11 by welding or sintering through a connecting material 143 located between the lower surface 171B of the second connecting segment 171 and the first surface 11T of the substrate 11. The lower surface 171B of the second connecting segment 171 is provided with a protrusion structure 1710a. The connecting material 143 here can be a welding material, such as high-performance welding materials like SnSb5 or SAC305, which can be welded in the form of solder sheets or solder paste, with a thickness of, for example, 50-200 μm; or, the connecting material 143 can be a sintering material, such as Ag or Cu, which forms a high-performance connecting layer after sintering, with a thickness of, for example, 20-50 μm. In this embodiment, the protrusion structure 1710a can provide a certain limiting effect on the connecting material, and the surface area of ​​the protrusion structure 1710a is larger than that of the existing planar structure. Therefore, a higher connection quality can be obtained between the second connecting segment 173 and the first surface 11T of the substrate 11, which is conducive to improving the electrical reliability of the entire power semiconductor packaging structure 10.

[0042] In some embodiments, see Figure 3A , Figure 4 and Figure 6 The upper surface 171T of the second connecting segment 173 has a recessed structure 1710c at a position corresponding to the protrusion structure 1710a. It is worth mentioning that the recessed structure 1710c here can fit with the package body 15, thereby further improving the connection between the second terminal 17 and the substrate 11.

[0043] In some embodiments, see Figure 3A , Figure 4 and Figure 6In the first direction A1, the protrusion height h1 of the protrusion structure 1710a relative to the lower surface 171B of the second connecting segment 171 is equal to the recess depth h2 of the recess structure 1710c relative to the upper surface 171T of the second connecting segment 171. This allows the entire second terminal 17 to have a substantially uniform thickness. The protrusion structure 1710a is formed by pressing from the upper surface 171T of the second connecting segment 171 towards the lower surface 171B. Here, the first direction A1 is the direction from the upper surface 171T of the second connecting segment 171 to the lower surface 171B of the second connecting segment 171, which is typically also the direction from the first surface 11T of the substrate 11 to the second surface 11B of the substrate 11. In this embodiment, the protrusion structure 1710a is formed by pressing, which improves the availability of the protrusion structure 1710a, thereby simplifying the fabrication of the second terminal 17.

[0044] In some embodiments, see Figure 6 The protruding structure 1710a contacts the first surface 11T of the substrate 11, and the end of the protruding structure 1710a near the first surface 11T of the substrate 11 is arc-shaped. Furthermore, in some embodiments, the protruding structure 1710a may not contact the first surface 11T of the substrate 11. In this case, the gap between the protruding structure 1710a and the first surface 11T of the substrate 11 is filled by a connecting material 143 (e.g., a welding material or a sintering material). Additionally, in other embodiments, the end of the protruding structure 1710a near the first surface 11T of the substrate 11 is not limited to an arc shape and may also be planar.

[0045] In some embodiments, see Figure 3A , Figure 4 and Figure 6 In the first direction A1, the protrusion height h1 of the protrusion structure 1710a relative to the lower surface 171B of the second connecting segment 171 is 0.02 mm to 0.1 mm. It is worth noting that if the protrusion height h1 is too large, it can lead to an unnecessary increase in the overall thickness of the power semiconductor package structure 10 in the first direction A1; conversely, if the protrusion height h1 is too small, its limiting effect on the connecting material 143 will be limited.

[0046] In some embodiments, see Figure 1 , Figure 2 , Figure 3A and Figure 6The package 15 includes a first sidewall SW1 and a second sidewall SW2 that are opposite to and spaced apart, and a third sidewall SW3 and a fourth sidewall SW4 that are opposite to and spaced apart. The third sidewall SW3 is located between and connects the first sidewall SW1 and the second sidewall SW2, and the fourth sidewall SW4 is located between and connects the first sidewall SW1 and the second sidewall SW2. The second lead-out section 173 extends, for example, from the second sidewall SW2 and is exposed outside the package 15. In the third direction A3, the second connecting section 171 includes a plurality of mutually spaced toothed junctions. In configuration 1710, each of the tooth-like structures 1710 has a protruding structure 1710a on its surface facing the first surface 11T of the substrate 11 (i.e., a portion of the lower surface 171B of the second connecting segment 171). Each of the tooth-like structures 1710a is connected to the first surface 11T of the substrate 11 by welding or sintering through the connecting material 143. Each of the tooth-like structures 1710 has a locking hole 1712 penetrating the second terminal 17 at one end near the second lead segment 173. The locking hole 1712 can improve the locking capability of the power semiconductor package structure 10. Here, the locking hole 1712 is, for example, a hollow structure, and its shape is not specifically limited. The third direction A3 here refers to the direction from the third sidewall SW3 to the fourth sidewall SW4, which is, for example, perpendicular to the first direction A1. Furthermore, it is worth mentioning that in some other embodiments, the single tooth structure 1710 is not limited to being configured with a single protrusion structure 1710a, but may also be configured with multiple protrusion structures 1710a.

[0047] In some embodiments, see Figure 1 , Figure 2 , Figure 3A and Figure 10 In the second direction A2, the second lead-out segment 173 includes a front transverse portion 173a, a first bent portion 173b, a middle transverse portion 173c, a second bent portion 173d, and a rear transverse portion 173e connected in sequence. The first bent portion 173b, the middle transverse portion 173c, and the second bent portion 173d together form an arched bending structure. In the second direction A2, the distance d1 from the middle transverse portion 173c to the package body 15 is greater than 2mm. Furthermore, the angle β at the connection between the first bent portion 173b and the front transverse portion 173a is 105 degrees to 165 degrees. Here, the second direction A2 is the direction from the first sidewall SW1 to the second sidewall SW2, which is, for example, perpendicular to both the first direction A1 and the third direction A3.

[0048] In some embodiments, see Figures 1 to 5The number of chips 13 is N, and the N chips 13 include multiple chip groups spaced apart in the third direction A3, with each chip group including M chips 13, where M is an integer greater than 1 and less than N; the first connection segment 161 includes multiple cantilever 1613 spaced apart in the third direction A3, each cantilever 1613 including M recesses 1613a spaced apart in the second direction A2 and protrusions 1613b located between every two adjacent recesses 1613a, with each protrusion 1613b connecting to two adjacent recesses 1613a on opposite sides in the second direction A2; the multiple cantilever 1613 corresponds one-to-one with the multiple chip groups, and the M recesses 1613a of each cantilever 1613 are connected one-to-one with each of the first electrode pads S of the M chips 13 in the corresponding chip group. This multi-chip parallel design allows the power semiconductor package structure 10 to have lower thermal resistance. For example, Figure 3A The diagram illustrates four chips 13 (corresponding to N=4), forming two chip groups spaced apart on a third-direction A3. Each chip group includes two chips 13 (corresponding to M=2), and two cantilever arms 1613 are also shown. It should be noted that the value of N is not limited to four; it can be more, such as six. Correspondingly, the number of chips in a single chip group is not limited to two; it can be more, such as three. Furthermore, the number of chip groups is not limited to two; it can be more, such as three. Similarly, the number of cantilever arms 1613 is not limited to two; it can be more, such as three. It is worth mentioning that in other embodiments, N=1, N=2, or N=3, and the number of cantilever arms 1613 can be one.

[0049] In some embodiments, see Figure 3A , Figure 4 and Figure 5 The recessed portion 1613a of the cantilever 1613 is connected to the first electrode pad S of the corresponding chip 13 through a connecting material 141. The connecting material 141 can be a welding material, such as high-performance welding materials like SnSb5 or SAC305, which can be welded in the form of solder sheets or solder paste, with a thickness of, for example, 50-200 μm; or the connecting material 141 can be a sintering material, such as Ag or Cu, which forms a high-performance connecting layer after sintering, with a thickness of, for example, 20-50 μm.

[0050] In some embodiments, see Figure 3A and Figure 4The first connecting segment 161 further includes a head end connecting portion 1611 and an end connecting portion 1615; the head end connecting portion 1611 is connected to the first lead-out segment 163, each cantilever 1613 is located between the head end connecting portion 1611 and the end connecting portion 1615 in the first direction A2, the recess 1613a of each cantilever 1613 closest to the head end connecting portion 1611 is connected to the head end connecting portion 1611, and the recess 1613a of each cantilever 1613 closest to the end connecting portion 1615 is connected to the head end connecting portion 1611. The recessed portion 1613a of the connecting portion 1615 is connected to the end connecting portion 1615; and the package 15 encapsulates at least a portion of the substrate 11, the plurality of chipsets, the first connecting segment 161 of the first terminal 16 (e.g., the head connecting portion 1611, the plurality of cantilevers 1613 and the end connecting portion 1615) and a portion of the second terminal 17 (e.g., the second connecting segment 171), and the first lead-out segment 163 of the first terminal 16 is exposed outside the package 15. In this embodiment, the first connecting segment 161 of the first terminal 16 has multiple cantilever 1613s with recessed portions 1613a at the connection points with each chip 13, and adjacent recessed portions 1613a are connected by protrusions 1613b, i.e., a sunken design. This makes the adjacent chips 13 connected in an arched shape, which can effectively avoid the short circuit problem caused by the small distance between the first terminal 16 and the substrate 11 under the coplanar connection design. Combined with the configuration of the first end connecting portion 1611 and the last end connecting portion 1615, it increases the structural stability of the first terminal 16 and improves the current sharing effect among multiple chips.

[0051] In some embodiments, see Figure 3A and Figure 4 The end connection portion 1615 is spaced apart from the recess 1613a closest to the end connection portion 1615 of each cantilever 1613 in the first direction A1 and the second direction A2. The first connection segment 161 also includes, for example, a plurality of first inclined connection portions 1614, which correspond one-to-one with the plurality of cantilever 1613. One end of each first inclined connection portion 1614 is connected to the recess 1613a closest to the end connection portion 1615 of the corresponding cantilever 1613, and the other end of each first inclined connection portion 1614 extends in a direction away from the first surface 11T of the substrate 11 and is connected to the end connection portion 1615.

[0052] In some embodiments, see Figure 3A and Figure 4The first end connecting portion 1611 is spaced apart from the recess 1613a closest to the first end connecting portion 1611 of each cantilever 1613 in the first direction A1 and the second direction A2. The first connecting segment 161 also includes, for example, a plurality of second inclined connecting portions 1612, which correspond one-to-one with the plurality of cantilever 1613. One end of each second inclined connecting portion 1612 is connected to the recess 1613a closest to the first end connecting portion 1611 of the corresponding cantilever 1613, and the other end of each second inclined connecting portion 1612 extends in a direction away from the first surface 11T of the substrate 11 and is connected to the first end connecting portion 1611.

[0053] In some embodiments, each chip 13 may be a chip with different functions made of semiconductor materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc., such as metal oxide semiconductor field-effect transistor (MOSFET), insulated gate bipolar transistor (IGBT), Schottky barrier diode (SBD), fast recovery diode (FRD), etc.

[0054] In some embodiments, see Figure 1 , Figure 2 and Figure 3A The first lead-out segment 163 extends from the first sidewall SW1 and is exposed outside the package 15, for example. The power semiconductor package structure 10 also includes a third terminal 18. At least one of the chip 13 has a third electrode pad G (e.g., a gate pad) disposed on the surface opposite to the substrate 11. The third terminal 18 is connected to the third electrode pad G via a metal bonding wire BW. A portion of the third terminal 18 extends from the first sidewall SW1 and is exposed outside the package 15. The power semiconductor package structure 10 also includes a fourth terminal 19, which is located on the third direction A3 between the first lead-out segment 163 and the third terminal 18, and the fourth terminal 19 is spaced apart from the first lead-out segment 163 and the third terminal 18 on the third direction A3.

[0055] In some embodiments, see Figure 3A and Figure 4The substrate 11 includes, for example, an insulating layer 110 and a current-passing layer 112 and a heat-dissipating layer 114 located on opposite sides of the insulating layer 110. The surface of the current-passing layer 112 facing away from the insulating layer 110 is, for example, the first surface 11T, and the surface of the heat-dissipating layer 114 facing away from the insulating layer 110 is, for example, the second surface 11B. The second connecting segment 171 is connected to the current-passing layer 112 via the connecting material 143. For example, the current-passing layer 112 can be made of metal materials such as Cu or Al, and as a conductive circuit, it can connect the chip 13, the first terminal 16, and the second terminal 17, etc. The heat-dissipating layer 114 can be made of metal materials such as Cu or Al, and it can provide large-area heat dissipation conditions. The insulating layer 110 can be made of various ceramic materials with high insulation, thermal conductivity, and mechanical strength, such as Al2O3, Si3N4, AlN, etc.

[0056] In some embodiments, see Figure 1 and Figure 3A The fourth terminal 19 extends from the end of the first connecting segment 161 near the first lead-out segment 163 in a direction away from the first connecting segment 161. The fourth terminal 19, the first connecting segment 161, and the first lead-out segment 163 are an integral structure. The fourth terminal 19, as a branch terminal extending from the first terminal 16, can serve as a separate drive source terminal. This design can reduce drive voltage fluctuations in the main circuit inductor. It is worth noting that in some embodiments, the fourth terminal 19 and the first terminal 16 can also be independent of each other rather than being an integral structure.

[0057] In some embodiments, see Figure 3A and Figure 7 The first surface 11T of the substrate 11, such as the upper surface of the current-passing layer 112, includes a power region 1121 and a driving region 1123 spaced apart in the second direction A2. The area of ​​the power region 1121 is larger than the area of ​​the driving region 1123. The chip 30 is disposed in the power region 1121. The third terminal 18 is connected to the driving region 1123 via a metal bonding wire BW. The third electrode pad G is also connected to the driving region 1123 via a metal bonding wire BW. Here, the power region 1121 has a large solid area, which can provide a larger chip placement space for multiple chips 13 to conduct current in parallel, thereby obtaining a higher current level.

[0058] In some embodiments, see Figure 3B and Figure 7A single trench 1122 is configured between the power region 1121 and the driving region 1123. Since the current-carrying layer 112 uses only a single trench 1122 to separate the power region 1121 and the driving region 1123, it reduces the shape / area mismatch between the metal layers (i.e., the current-carrying layer 112 and the heat dissipation layer 114) on opposite sides of the insulating layer 110, reducing the deformation of the insulating layer 110 under high-temperature conditions, thereby improving the reliability of the power semiconductor package structure 10. Furthermore, multiple chipsets are disposed in the power region 1121, the driving region 1123 is provided with at least one resistor 12, a third terminal 18 is connected to the driving region 1123 via a metal bonding wire BW, and at least one third electrode pad G of the chip 13 is connected one-to-one to the surface of the at least one resistor 12 facing away from the current-carrying layer 112 via a metal bonding wire BW. For example, Figure 3B The diagram shows four resistors 12 and four chips 13. The four chips 13 are divided into two chip groups and disposed in the power region 1121. Each chip 13 is equipped with a third electrode pad G, and each third electrode pad G is connected to a resistor 12. It is worth mentioning that in some embodiments, only some of the third electrode pads G of the chips 13 may be connected to the surface of the resistor 12 facing away from the current-passing layer 112, while the third electrode pads G of other chips 13 may be connected to the surface of the driving region 1123 of the current-passing layer 112, or even some chips 13 may not be equipped with third electrode pads G.

[0059] As described above, the resistor 12 is, for example, a resistor with two electrodes on its upper and lower surfaces, exhibiting a fixed resistance value between the electrodes. Its resistance value is, for example, 1-20 ohms (Ω), its length and width dimensions are, for example, 0.5*0.5-2*2 mm, and its thickness is, for example, 0.1-1 mm. It is worth noting that in actual production, the inherent parameters between chips may differ. For example, the internal resistance of the chip may vary in its gate parameters. In practical use, these parameter differences can lead to significant differences in the turn-on / turn-off characteristics of different chips within the same device, resulting in a bottleneck effect. Therefore, by adding resistor 12 to provide a resistance between the external device and chip 13, this difference can be reduced, and the current sharing effect between chips can be improved.

[0060] In some embodiments, see Figure 7 The area ratio of the power region 1121 to the driving region 1123 is greater than 8. This allows the current-passing layer 112 to provide a large area for current flow, supporting a larger total chip area. This enables higher current ratings and lower resistance, and ensures sufficient placement area for multiple chips in a small package. For example, in a design using four chips 13, the total chip area is greater than 80 mm². 2 This effectively improves the current carrying capacity of the power semiconductor package structure 10.

[0061] In some embodiments, see Figure 7 In the second direction A2, the width W0 of the trench 1122 is, for example, 0.4-1.6 mm, which ensures sufficient placement area for multiple chips in a small-size package. See also Figure 6 In the first direction A1, the thickness t1 of the current-carrying layer 112 is, for example, 0.5-1 mm, and the thickness t2 of the insulating layer 110 is, for example, 0.25-0.64 mm. The thickness t1 of the current-carrying layer 112 is designed to increase the cross-sectional area of ​​the conductive path and reduce the resistance; the thickness t2 of the insulating layer 110 is designed to ensure sufficient insulation capability. Furthermore, the thickness of the heat dissipation layer 114 in the first direction A1 is, for example, equal to the thickness t1 of the current-carrying layer 112.

[0062] In some embodiments, see Figure 7 On the third direction A3, the driving region 1123 includes a middle portion 1123b and two end portions 1123a and 1123c extending from the middle portion 1123b to opposite ends in a gradually widening manner. The power region 1121 protrudes towards the middle portion 1123b of the driving region 1123 on the side closest to the driving region 1123. In this embodiment, by designing the two end portions 1123a and 1123c of the driving region 1123 to be thicker and reducing the width of the space portion 1123b, the area of ​​the power region 1121 can be further increased.

[0063] In some embodiments, see Figure 7 The ratio of the maximum width W4 of each of the ends 1123a and 1123c to the maximum width W5 of the middle portion 1123b is greater than 1.5.

[0064] In some embodiments, see Figure 3A and Figure 7The two ends 1123 serve as bonding regions, and the plurality of chipsets include a first chipset and a second chipset. A third electrode pad G is disposed on the surface of each chip 13 in the first chipset that faces away from the first surface 11T of the substrate 11. The third electrode pad G is also disposed on the surface of each chip 13 in the second chipset that faces away from the first surface 11T of the substrate 11. On the third direction A3, the third electrode pad G of each chip 13 in the first chipset is located on the side of the first chipset away from the second chipset and is connected to one end of the two ends, for example, 1123a, via a metal bonding line BW. Similarly, the third electrode pad G of each chip 13 in the second chipset is located on the side of the second chipset away from the first chipset and is connected to the other end of the two ends, for example, 1123c, via a metal bonding line BW. Figure 3A Taking the four chips 13 shown as an example, the four chips 13 are arranged in a rectangular arrangement and divided into two chip groups. On the third direction A3, the two chip groups are placed with the third electrode pads G facing outwards, which is beneficial for the arrangement of the metal bonding lines BW connecting each third electrode pad G to the driving area 1123.

[0065] In some embodiments, see Figure 1 , Figure 2 , Figure 9 and Figure 10 The package 15 further includes, for example, a top surface 15T and a bottom surface 15B disposed opposite to each other. The first sidewall SW1, the second sidewall SW2, the third sidewall SW3, and the fourth sidewall SW4 are respectively connected to the top surface 15T and the bottom surface 15B. The second surface 11B of the substrate 11 is partially or completely exposed outside the package 15 on the side where the bottom surface 15B of the package 15 is located. The portion of the fourth terminal 19 exposed outside the package 15 is bent along a direction away from the bottom surface 15B of the package 15 to form a first longitudinal portion 193. The portion of the third terminal 18 exposed outside the package 15 is bent along a direction away from the bottom surface 15B of the package 15 to form a first longitudinal portion 193. The bottom surface 15B of the package 15 is bent to form a second longitudinal portion 183; in the second direction A2, the distance d3 from each of the first longitudinal portion 193 and the second longitudinal portion 183 to the package 15 is greater than 2.8 mm, and the distance d2 between the end face 163S of the first lead-out segment 163 away from the package 15 and each of the first longitudinal portion 193 and the second longitudinal portion 183 is greater than 0.3 mm; and, in the direction away from the bottom surface 15B of the package 15, the first longitudinal portion 193 and the second longitudinal portion 183 are first parallel to each other, then move away from each other, and then become parallel to each other again (e.g., ...). Figure 9 (As shown).

[0066] In some embodiments, see Figure 2 and Figure 11 The bottom surface 15B of the package 15 is provided with an annular boss 151 protruding from the bottom surface 15B. The height h4 of the annular boss 151 relative to the bottom surface 15B in the first direction A1 is greater than or equal to 0.2 mm, for example, 0.2 mm, 0.5 mm, or 1 mm. The second surface 11B of the substrate 11 is exposed outside the package 15 through the annular boss 151. In this embodiment, by configuring the annular boss 151 at the bottom of the package 15, the annular boss 151 provides a connection interface between the heat dissipation surface of the power semiconductor package structure 10 (i.e., the part of the second surface 11B of the substrate 11 exposed outside the package 15) and the heat sink (not shown). On the other hand, the raised distance also provides a larger creepage distance, thereby increasing the insulation capability of the device under high voltage conditions.

[0067] In some embodiments, see Figure 2 and Figure 11 The height h4 of the annular boss 151 relative to the bottom surface 15B of the package body 15 in the first direction A1 is 0.2-0.5mm; the second surface 11B of the substrate 11 and the end face 151S of the annular boss 151 away from the bottom surface 15B of the package body 15 are in the same plane.

[0068] In some embodiments, see Figure 11 In the second direction A2, the distance d5 from the outer side of the annular boss 151 to the second surface 11B of the substrate 11 is greater than 0.5 mm, so as to increase the creepage distance and electrical clearance from the second lead-out section 173 to the heat dissipation surface (i.e., at least a portion of the second surface 11B of the substrate 11).

[0069] In some embodiments, see Figure 11The second lead-out segment 173 has a third surface 173T and a fourth surface 173B disposed opposite to each other in a first direction A1. The fourth surface 173B is located between the third surface 173T and the bottom surface 15B of the package 15 in the first direction A1. In the second direction A2, the distance d4 between the third surface 173T of the second lead-out segment 173 and the outer side surface of the annular boss 151 is greater than 3.6 mm, or the distance between the fourth surface 173B of the second lead-out segment 173 and the outer side surface of the annular boss 151 is greater than 3.6 mm, so as to increase the creepage distance and electrical clearance from the second lead-out segment 173 to the heat dissipation surface (i.e., at least a portion of the second surface 11B of the substrate 11). In the first direction A1, the distance h3 from the fourth surface 173B of the second lead-out section 173 to the bottom surface 15B of the package 15 is greater than 1.5 mm, so as to increase the creepage distance and electrical clearance from the second lead-out section 173 to the heat dissipation surface (i.e., at least a portion of the second surface 11B of the substrate 11).

[0070] In some embodiments, see Figure 10 In the first direction A1, the distance between the lower surface 163B of the first lead-out section 163 of the first terminal 16 and the fourth surface 173B of the second lead-out section 173 of the second terminal 17 is, for example, 0mm-0.1mm.

[0071] In some embodiments, see Figure 11 In the second direction A2, the second lead-out section 173 is spaced apart from the bottom surface 15B of the package 15. The second sidewall SW2 includes a first sidewall section SW21 located in the first direction A1 between the second lead-out section 173 and the bottom surface 15B of the package 15. The angle θ between the first sidewall section SW21 and the first direction A1 is, for example, 3 degrees to 10 degrees. It is worth mentioning that the package 15 serves two purposes: firstly, it protects the internal chip 13 and substrate 11; secondly, it acts as a seal to prevent external moisture, dust, corrosive gases, etc., from entering the interior, increasing device reliability; and thirdly, it increases the insulation distance, further enhancing device reliability. During the formation of the package 15, a well-designed mold is used, for example, to... Figure 3A After the structure shown is placed, the encapsulating material, such as molding compound, is melted and injected into the mold using injection molding. The molten molding compound fills the gap between the mold and the structure to be encapsulated. After cooling, the molding compound hardens and solidifies, and finally, demolding is performed. In this embodiment, the included angle θ is designed to be 3-10 degrees, which is beneficial for demolding; therefore, the included angle θ can also be called the demolding angle.

[0072] In some embodiments, see Figure 3A , Figure 4 and Figure 8 The width of the second terminal 17 in the third direction A3 decreases from the outside of the encapsulation body 15 towards the inside of the encapsulation body 15, for example, W2 < W1. The width W2 of one end of the second connection segment 171 connected to the first surface 11T of the substrate 11 in the third direction A3 is less than the width K of the substrate 11 in the third direction A3, that is, W2 < K. Multiple tooth-shaped structures 1710 spaced from each other in the third direction A3 are provided at one end of the second connection segment 171 connected to the first surface 11T of the substrate 11. Each of the tooth-shaped structures 1710 is connected to the substrate 11 by a connecting material 143 in a welding or sintering manner. A mold locking hole 1712 penetrating the second terminal 17 is provided at one end of each of the tooth-shaped structures 1710 close to the second lead-out segment 173.

[0073] In some embodiments, referring to Figure 8 the multiple tooth-shaped structures 1710 provided at one end of the second connection segment 171 connected to the first surface 11T of the substrate 11, for example, have the same width L in the third direction A3. Of course, they may also have different widths. In other embodiments, one end of the second connection segment 171 connected to the first surface 11T of the substrate 11 is a whole structure instead of multiple spaced tooth-shaped structures 1710.

[0074] In some embodiments, referring to Figure 1 、 Figure 2 and Figure 3A the third terminal 18 includes a first part encapsulated in the encapsulation body 15 and a second part extending from the first side wall SW1 of the encapsulation body 15 and exposed outside the encapsulation body 15; the fourth terminal 19 includes a first part encapsulated in the encapsulation body 15 and a second part extending from the first side wall SW1 of the encapsulation body 15 and exposed outside the encapsulation body 15; in the third direction A3, the second part of the fourth terminal 19 is located between the second part of the third terminal 18 and the first lead-out segment 163, and any two of the second part of the fourth terminal 19, the second part of the third terminal 18, and the first lead-out segment 163 are spaced apart. Furthermore, referring to Figure 10The second portion of the third terminal 18 is bent in a direction away from the bottom surface 15B of the package body 15 to form a second longitudinal portion 183, and the bending angle α is, for example, 80 degrees to 100 degrees; the second portion of the fourth terminal 19 is bent in a direction away from the bottom surface 15B of the package body 15 to form a first longitudinal portion 193, and the bending angle α is, for example, 80 degrees to 100 degrees; in the second direction A2, the first longitudinal portion 193 and the second longitudinal portion 183 are both located between the package body 15 and the end face 163S of the first lead-out section 163 away from the package body 15.

[0075] In some embodiments, see Figure 9 The width d9 of the first lead-out segment 163 on the third direction A3 is greater than the distance d8 between the two opposite sides of the third terminal 18 and the fourth terminal 19 on the third direction A3.

[0076] In some embodiments, see Figure 9 In the direction away from the bottom surface 15B of the package 15, the first longitudinal portion 193 includes, for example, a first lower parallel portion 193a, a first arc-shaped portion 193b, and a first upper parallel portion 193c arranged sequentially; in the direction away from the bottom surface 15B of the package 15, the second longitudinal portion 183 includes, for example, a second lower parallel portion 183a, a second arc-shaped portion 183b, and a second upper parallel portion 183c arranged sequentially; the distance d6 between the first lower parallel portion 193a and the second lower parallel portion 183a is less than the distance d7 between the first upper parallel portion 193c and the second upper parallel portion 183c, and the radius R of each of the first arc-shaped portion 193b and the second arc-shaped portion 183b is, for example, 5-8 mm.

[0077] In some embodiments, such as Figure 9 As shown, the curvature of the first arcuate portion 193b is less than the curvature of the second arcuate portion 183b; and, in the first direction A1, the distance d10 from the interface between the first lower parallel portion 193a and the first arcuate portion 193b to the bend of the second part of the fourth terminal 19 (i.e., the part exposed outside the package 15) is, for example, 2-4 mm.

[0078] In some embodiments, see Figure 3AThe first connecting segment 161, near the first lead-out segment 163, has a moisture-blocking groove 1616, such as a V-shaped groove, which prevents moisture from entering the package 15. Similarly, the second connecting segment 171, near the second lead-out segment 173, has a moisture-blocking groove 1716, such as a V-shaped groove, which also prevents moisture from entering the package 15. It is worth noting that the depth and width of the moisture-blocking grooves 1616 and 1716 are not specifically limited.

[0079] In some embodiments, see Figure 12 Each cantilever 1613 has a through groove 1613g extending through its top surface 1613U and bottom surface 1613L. The through groove 1613g extends along a second direction A2, starting from the recess 1613a closest to the first end connection portion 1611, passing through each of the protrusions 1613b of the cantilever 1613, and extending to the recess 1613a closest to the end connection portion 1615. Here, the top surface 1613U of the cantilever 1613 is the surface of the cantilever 1613 facing away from the chip 13, and the bottom surface 1613L of the cantilever 1613 is the surface of the cantilever 1613 facing the chip 13. Because each cantilever 1613 has the through groove 1613g, it helps to prevent the overflow of the bonding material 141, such as soldering material, from the surface of the chip 13 during the soldering process. It also helps to reduce the stress on the first terminal 16 during the manufacturing and use processes, thereby improving the product's reliability. Figure 12 The two chipsets shown have a total of four chips 13 as an illustrative example. Each of the two cantilever arms 1613 is provided with a through groove 1613g. The through groove 1613g is a long and thin strip-shaped through groove. In the second direction A2, it extends from one of the two recesses 1613a, through the protrusion 1613b between the two recesses 1613a, and to the other recess 1613a.

[0080] In some embodiments, see Figure 12The first connecting segment 161 further includes an intermediate connecting portion 1617. The intermediate connecting portion 1617 is located between the first connecting portion 1611 and the last connecting portion 1615 in the second direction A2. In the third direction A3, the intermediate connecting portion 1617 is located between the protrusions 1613b of two adjacent cantilever 1613s, connecting the protrusions 1613b of the two adjacent cantilever 1613s. By providing the intermediate connecting portion 1617 and the last connecting portion 1615, the stability of the first terminal 16 itself can be improved, making it less prone to deformation during product manufacturing. Furthermore, the unevenness of the current flowing through the first electrode pad S of each chip 13 can be effectively reduced. Figure 12 The two chipsets shown, comprising a total of four chips 13, are illustrated as an example. Each of the two cantilever arms 1613 has two recesses 1613a and a protrusion 1613b located between the two recesses 1613a. An intermediate connecting portion 1617 connects the two protrusions 1613b of the two cantilever arms 1613 on a third direction A3. It is worth noting that in some embodiments, the number of intermediate connecting portions 1617 can be multiple, with each pair of adjacent protrusions 1613b of the cantilever arms 1613 connected by one intermediate connecting portion 1617 on the third direction A3.

[0081] In some embodiments, see Figure 12The substrate 11 includes an insulating layer 110 and a current-passing layer 112 disposed on the insulating layer 110. The plurality of chip groups are located on the side of the current-passing layer 112 opposite to the insulating layer 110. Each chip 13 in the plurality of chip groups has a third electrode pad G and a fourth electrode pad K disposed on its surface opposite to the substrate 11. The current-passing layer 112 includes a power region 1121, a driving region 1123, and another driving region 1125 spaced apart from each other in a second direction A2. The driving region 1123 is located between the power region 1121 and the other driving region 1125. The plurality of chip groups are disposed in the power region 1121. The driving region 1123 is provided with a plurality of resistors 12. The power semiconductor package structure further includes a third electrode pad G and a fourth electrode pad K. Three terminals 18 and 19 are provided. The first terminal 16, the third terminal 18, and the fourth terminal 19 are spaced apart on a third-direction A3. The third terminal 18 is connected to the driving area 1123 via a metal bonding wire BW. The third electrode pad G of each chip 13 in the plurality of chipsets is connected one-to-one to the surface of the plurality of resistors 12 facing away from the current-passing layer 112 via metal bonding wire BW. The fourth terminal 19 is connected to another driving area 1125 via a metal bonding wire BW to connect to the fourth electrode pad K of each chip 13 in the plurality of chipsets. That is, the fourth electrode pad K of each chip 13 in the plurality of chipsets is connected to the other driving area 1125 via a metal bonding wire BW. Figure 12 The two chipsets shown represent a total of four chips 13 as an illustrative example. Each chip 13 is connected to a resistor 12 on the surface away from the current-carrying layer 112 via a metal bonding line BW. Different chips 13 are connected to different resistors 12. Furthermore, two chips 13 in each chipset are connected to the other driving region 1125 in a cascaded manner via a metal bonding line BW. For example, a fourth electrode pad K of one of the two chips 13 is connected to a fourth electrode pad K of the other chip 13 via a metal bonding line BW, and the other fourth electrode pad K of the other chip 13 is then connected to the other driving region 1125 via a metal bonding line BW.

[0082] In some embodiments, see Figure 12 The driving area 1123 has a recess 1123u on the side facing the other driving area 1125, and the other driving area 1125 has a protrusion 1125n on the side facing the driving area 1123. The protrusion 1125n corresponds to the recess 1123u.

[0083] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A power semiconductor packaging structure, characterized in that, include: The substrate has a first surface and a second surface disposed opposite to each other; Multiple chip groups are disposed on a first surface of the substrate, wherein the multiple chip groups are spaced apart in a third direction perpendicular to a first direction, the first direction being the direction from the first surface to the second surface, each chip group includes M chips spaced apart in a second direction perpendicular to both the first direction and the third direction, where M is an integer greater than 1, and a first electrode pad is disposed on the surface of each chip facing away from the first surface of the substrate. The first terminal includes a first connecting segment and a first lead-out segment. The first connecting segment includes a head connecting portion, a tail connecting portion, and a plurality of cantilevers spaced apart in the third direction. The head connecting portion is connected to the first lead-out segment. Each cantilever is located between the head connecting portion and the tail connecting portion in the second direction. Each cantilever includes M recesses spaced apart in the second direction and a protrusion located between every two adjacent recesses. Each protrusion is connected to two adjacent recesses on opposite sides in the second direction. The plurality of cantilevers correspond one-to-one with the plurality of chipsets. The M recesses of each cantilever are respectively connected to the first electrode pads of the M chips of the corresponding chipset. The recess of each cantilever closest to the head connecting portion is connected to the head connecting portion, and the recess of each cantilever closest to the tail connecting portion is connected to the tail connecting portion. as well as A package encapsulates at least a portion of the substrate, the plurality of chipsets, and a first connection segment of the first terminal, wherein a first lead-out segment of the first terminal is exposed outside the package.

2. The power semiconductor packaging structure according to claim 1, characterized in that, The end connection portion is spaced apart from the recess portion closest to the end connection portion of each cantilever in the first direction and the second direction; The first connecting segment further includes a plurality of first inclined connecting portions, each of which corresponds to one of the plurality of cantilever arms. One end of each first inclined connecting portion is connected to the recess of the corresponding cantilever arm that is closest to the end connecting portion, and the other end of each first inclined connecting portion extends in a direction away from the first surface of the substrate and is connected to the end connecting portion.

3. The power semiconductor packaging structure according to claim 1, characterized in that, The first end connecting portion is spaced apart from the recessed portion closest to the first end connecting portion of each cantilever in the first direction and the second direction; The first connecting segment further includes a plurality of second inclined connecting portions, each of which corresponds to one of the plurality of cantilever arms. One end of each second inclined connecting portion is connected to the recess of the corresponding cantilever arm that is closest to the first end connecting portion, and the other end of each second inclined connecting portion extends in a direction away from the first surface of the substrate and is connected to the first end connecting portion.

4. The power semiconductor packaging structure according to any one of claims 1 to 3, characterized in that, The substrate includes an insulating layer and a current-passing layer disposed on the insulating layer, and the plurality of chip groups are located on the side of the current-passing layer opposite to the insulating layer; at least one chip in the plurality of chip groups has a third electrode pad disposed on the surface opposite to the substrate. The flow passage layer includes a power region and a drive region spaced apart from each other in the second direction, and a single trench is disposed between the power region and the drive region; the area of ​​the power region is larger than the area of ​​the drive region; The plurality of chipsets are disposed in the power region, the driving region is provided with at least one resistor, the power semiconductor package structure further includes a third terminal, the third terminal is connected to the driving region through metal bonding wires, and the third electrode pads of at least one of the chips are connected one-to-one to the surface of the at least one resistor away from the current-passing layer through metal bonding wires.

5. The power semiconductor packaging structure according to claim 4, characterized in that, The area ratio of the power region to the driving region is greater than 8; and / or, In the second direction, the width of the groove is 0.4 mm to 1.6 mm; and / or, In the first direction, the thickness of the flow-through layer is 0.5 mm to 1 mm, and the thickness of the insulating layer is 0.25 mm to 0.64 mm.

6. The power semiconductor packaging structure according to claim 4, characterized in that, In the third direction, the drive region includes a middle portion and two ends that extend from the middle portion to opposite ends in a gradually widening manner, and the side of the power region closest to the drive region protrudes toward the middle portion of the drive region.

7. The power semiconductor packaging structure according to claim 6, characterized in that, The ratio of the maximum width of each end portion to the maximum width of the middle portion is greater than 1.

5.

8. The power semiconductor packaging structure according to claim 6, characterized in that, The two ends are respectively used as bonding regions; The plurality of chipsets include a first chipset and a second chipset. The third electrode pad is disposed on the surface of each chip in the first chipset that is away from the first surface of the substrate. The third electrode pad is disposed on the surface of each chip in the second chipset that is away from the first surface of the substrate. In the third direction, the third electrode pad of each chip in the first chipset is located on the side of the first chipset away from the second chipset and is connected to one end of the two ends by a metal bonding wire, and the third electrode pad of each chip in the second chipset is located on the side of the second chipset away from the first chipset and is connected to the other end of the two ends by a metal bonding wire.

9. The power semiconductor packaging structure according to claim 4, characterized in that, The power semiconductor package structure further includes a second terminal and a fourth terminal, and the substrate further includes a heat dissipation layer disposed on the side of the insulating layer away from the current-passing layer; the package includes a first sidewall and a second sidewall that are disposed opposite to and spaced apart in the second direction. The first lead-out section extends from the first sidewall of the package and is exposed outside the package. The fourth terminal is formed by extending from the end of the first connecting section near the first lead-out section toward a direction away from the first connecting section and is spaced apart from the first lead-out section in the third direction. The fourth terminal is an integral structure with the first connecting section and the first lead-out section. The second terminal includes a second lead-out section extending from the second sidewall of the package and exposed outside the package body, and a second connection section encapsulated within the package body, the second connection section being connected to the current-passing layer of the substrate; The package encapsulates the insulating layer, the current-passing layer, a portion of the second terminal, a portion of the third terminal, and a portion of the fourth terminal, and exposes at least a portion of the surface of the heat-dissipating layer away from the insulating layer.

10. The power semiconductor packaging structure according to claim 1, characterized in that, Each of the cantilever arms has a through groove extending through the top and bottom surfaces of the cantilever arm, and the through groove extends along the second direction; The through groove extends from the recess closest to the first end connection of the cantilever, through each of the protrusions of the cantilever, and to the recess closest to the end connection of the cantilever.

11. The power semiconductor packaging structure according to claim 1, characterized in that, The first connecting segment further includes an intermediate connecting portion, which is located between the first connecting portion and the last connecting portion in the second direction, and between the protrusions of two adjacent cantilever arms in the third direction, and the intermediate connecting portion connects the protrusions of the two adjacent cantilever arms.

12. The power semiconductor packaging structure according to any one of claims 1-3, 10 and 11, characterized in that, The substrate includes an insulating layer and a current-passing layer disposed on the insulating layer, and the plurality of chip groups are located on the side of the current-passing layer opposite to the insulating layer; each chip in the plurality of chip groups is further provided with a third electrode pad and a fourth electrode pad on the surface opposite to the substrate. The flow layer includes a power region, a driving region, and another driving region spaced apart from each other in the second direction, with the driving region located between the power region and the other driving region; The plurality of chipsets are disposed in the power region, the driving region is provided with a plurality of resistors, and the power semiconductor package structure further includes a third terminal and a fourth terminal. The first terminal, the third terminal and the fourth terminal are disposed at intervals in the third direction. The third terminal is connected to the driving region through metal bonding wires. The third electrode pad of each chip in the plurality of chipsets is connected one-to-one to the surface of the plurality of resistors away from the current-passing layer through metal bonding wires. The fourth terminal is connected to the other driving region through metal bonding wires. The fourth electrode pad of each chip in the plurality of chipsets is connected to the other driving region through metal bonding wires.

13. The power semiconductor packaging structure according to claim 12, characterized in that, The driving area has a recess on the side facing the other driving area, and the other driving area has a protrusion on the side facing the driving area, with the protrusion corresponding to the recess.

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