Novel nine-level H-type inverter device

Abstract

The utility model discloses a novel nine-level H-type inverter device, which comprises a direct-current power supply, a load, five resistors, six capacitors, twelve diodes, nine switch tubes and two inductors, four diodes and one switch tube form a secondary loop, and two inductors and one capacitor form an LCL filter circuit. The four switch tubes form an H-type inverter bridge connection mode, compared with other nine-level inverters, the novel nine-level H-type inverter is simpler in structure, and a secondary loop and a tertiary loop do not influence each other, that is, two levels emitted by the secondary loop and four levels emitted by the tertiary loop do not influence each other. A current and voltage loop is provided through a secondary loop, and the distortion rate of output voltage and current is reduced through an LCL filter circuit. The circuit provided by the utility model guarantees the normal operation of the inverter in an AC power supply system, and reduces the failure rate of electrical equipment and unnecessary loss.

Description

Technical Field

[0001] This utility model relates to the field of inverter power supply, specifically to a novel nine-level H-type inverter device. Background Technology

[0002] An inverter, as a power conversion device, primarily functions to convert DC power into AC power with a fixed frequency and voltage, or adjustable frequency and voltage. This device plays a crucial role in modern electrical applications, particularly in household appliances such as air conditioners, power tools, and refrigerators. Among various inverter types, multilevel inverters, due to their ability to operate in high-voltage environments using fewer power device ratings, have expanded their application range. With the continuous expansion of inverter applications, improving the stability of power supply performance and simplifying equipment structure have become key to industry development. While traditional H-type nine-level inverters can provide multilevel output, their complex structure leads to higher distortion rates in output voltage and current, increasing the risk of electrical equipment failure and additional energy loss. Therefore, a significant direction in current inverter technology development is to reduce or eliminate output voltage and current distortion. This not only improves energy utilization efficiency and reduces energy loss but also lowers equipment failure rates and extends equipment lifespan, thus providing users with a more stable and reliable power supply. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a novel nine-level H-type inverter device, which simplifies the structure of the nine-level inverter and reduces the inverter output voltage and current distortion rate. To achieve the above objectives, this invention adopts the following technical solution:

[0004] The circuit proposed in this utility model includes a DC power supply, a load, twelve diodes, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first inductor L1, a second inductor L2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a ninth switch S9.

[0005] The positive terminal of the DC power supply output is connected to the first resistor R1, the fourth resistor R4, the collector of the first switch S1, and the collector of the second switch S2. The negative terminal of the DC power supply output is connected to the negative terminal of the third capacitor C3, the fifth resistor R5, the emitter of the third switch S3, and the emitter of the fourth switch S4. The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 constitute a conventional H-type inverter bridge connection.

[0006] The first inductor L1, the second inductor L2, and the sixth capacitor C6 constitute an LCL filter circuit.

[0007] The positive terminal of the first capacitor C1 is connected in series with the first resistor R1, and the negative terminal of the first capacitor C1 is connected to the second resistor R2 and the collector of the fifth switch S5.

[0008] The positive terminal of the second capacitor C2 is connected in series with the second resistor R2, and the negative terminal of the second capacitor C2 is connected to the third resistor R3 and the collector of the seventh switch S7.

[0009] The positive terminal of the third capacitor C3 is connected to the third resistor R3.

[0010] The positive terminal of the fourth capacitor C4 is connected to the fourth resistor R4, and the negative terminal of the fourth capacitor C4 is connected to the positive terminal of the fifth capacitor C5, the positive terminal of the first diode D1, and the negative terminal of the third diode D3.

[0011] The negative terminal of the fifth capacitor C5 is connected to the fifth resistor R5.

[0012] The positive terminal of the second diode D2 is connected to the emitter of the first switch S1, the collector of the third switch S3, the collector of the sixth switch S6, the collector of the eighth switch S8, and the negative terminal of the fourth diode D4.

[0013] The collector of the ninth switch S9 is connected to the cathode of the first diode D1 and the cathode of the second diode D2, and the emitter of the ninth switch S9 is connected to the anode of the third diode D3 and the anode of the fourth diode D4.

[0014] The emitter of the sixth switch S6 is connected to the emitter of the fifth switch S5.

[0015] The emitter set of the eighth switch S8 is connected to the emitter set of the seventh switch S7.

[0016] Furthermore, one side of the input terminal of the LCL filter circuit is connected to the emitter of the first switch S1 and the collector of the third switch S3, and the other side is connected to the emitter of the second switch S2 and the collector of the fourth switch S4. The output is connected to the load.

[0017] Furthermore, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, and the ninth switch S9 constitute a secondary circuit.

[0018] Furthermore, the second resistor R2, the second capacitor C2, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 constitute a tertiary circuit.

[0019] Furthermore, secondary and tertiary circuits can provide a path for current to flow.

[0020] Furthermore, the fourth resistor R4 and the fourth capacitor C4, together with the fifth resistor R5 and the fifth capacitor C5, share the DC voltage and provide half of the input voltage at the midpoint M.

[0021] Furthermore, the first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2, the third resistor R3, and the third capacitor C3 share the input voltage at point L in a 1:3 ratio.

[0022] Furthermore, the first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2, and the third resistor R3, the third capacitor C3 share the input voltage at point N in a 3:1 ratio.

[0023] Furthermore, all of the switching transistors are insulated gate bipolar transistors (IGBTs).

[0024] Compared with existing technologies, the advantages of this invention's circuit are as follows: the proposed nine-level H-type inverter device has a simpler structure than other nine-level inverters, and the secondary and tertiary circuits do not affect each other; that is, the two levels generated by the secondary circuit and the four levels generated by the tertiary circuit do not interfere with each other. Furthermore, the addition of an LCL filter circuit on the inverter's output side further reduces the distortion rate of the output voltage and current, thereby reducing the failure rate of electrical equipment and unnecessary losses. Attached Figure Description

[0025] Figure 1 This is a structural diagram of a new type of nine-level H-type inverter device.

[0026] Figure 2-10 This is a modal diagram of a novel nine-level H-type inverter. Detailed Implementation

[0027] The present invention will now be further described with reference to the accompanying drawings. For clarity and brevity, other details that are not closely related to the present invention have been omitted. It should also be noted that, unless otherwise specifically described in detail, the processes or symbols described below are those that can be understood or implemented by those skilled in the art by referring to the prior art.

[0028] The circuit structure of this utility model is as follows: Figure 1 As shown, for ease of analysis, all components in the circuit structure are considered ideal components.

[0029] Figure 2 Provide voltage U to the load in The modal diagram shows that in this mode, only the first switch S1 and the fourth switch S4 are turned on, and the voltage and current flow path is the first switch S1, the LCL filter circuit, the load, and the fourth switch S4.

[0030] Figure 3 Provides 3×U voltage to the load in The modal diagram of / 4 shows that in this mode only the fourth switch S4 and the fifth switch S5 are turned on. The voltage and current flow path is the first resistor R1, the first capacitor C1, the fifth switch S5, the freewheeling diode of the sixth switch S6, the LCL filter inductor, the load, and the fourth switch S4.

[0031] Figure 4 Provide voltage U to the load in The modal diagram of / 2 shows that in this mode only the fourth switch S4 and the ninth switch S9 are conducting. The voltage and current flow path is the fourth resistor R4, the fourth capacitor C4, the first diode D1, the ninth switch S9, the fourth diode D4, the LCL filter circuit, the load, and the fourth switch S4.

[0032] Figure 5 Provide voltage U to the load in The modal diagram of / 4 shows that in this mode only the fourth switch S4 and the seventh switch S7 are turned on. The voltage and current flow path is the first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2, the seventh switch S7, the freewheeling diode of the eighth switch S8, the LCL filter inductor, the load, and the fourth switch S4.

[0033] Figure 6 The mode diagram provides a voltage of 0 to the load. In this mode, only the third switch S3 and the fourth switch S4 are turned on. No current flows through the load at this time.

[0034] Figure 7 Provide voltage -U to the load in The modal diagram of / 4 shows that in this mode only the second switch S2 and the sixth switch S6 are turned on. The voltage and current flow path is the second switch S2, the load, the LCL filter inductor, the sixth switch S6, and the freewheeling diode of the fifth switch S5.

[0035] Figure 8 Provide voltage -U to the load inThe modal diagram is shown in section 2. In this mode, only the second switch S2 and the ninth switch S9 are conducting. The voltage and current flow path is: second switch S2, load, LCL filter circuit, second diode D2, ninth switch S9, third diode D3, second capacitor C2, and second resistor R2.

[0036] Figure 9 Provide voltage to the load -3×U in The modal diagram is shown in section 4. In this mode, only the second switch S2 and the eighth switch S8 are conducting. The voltage and current flow path is: second switch S2, load, LCL filter inductor, eighth switch S8, freewheeling diode of seventh switch S7, fifth resistor R5, and fifth capacitor C5. Figure 10 The modal diagram for providing voltage -Uin to the load shows that in this mode only the second switch S2 and the third switch S3 are turned on. The voltage and current flow path is the second switch S2, the load, the LCL filter circuit, and the third switch S3.

Claims

1. A novel nine-level H-type inverter device, characterized in that, The circuit structure of the novel nine-level H-type inverter device includes a DC power supply, a load, twelve diodes, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first inductor L1, a second inductor L2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a ninth switch S9. The DC power supply output... The positive terminal is connected to the first resistor R1, the fourth resistor R4, the collector of the first switch S1, and the collector of the second switch S2. The negative terminal of the DC power supply output is connected to the negative terminal of the third capacitor C3, the fifth resistor R5, the emitter of the third switch S3, and the emitter of the fourth switch S4. The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 form an H-type inverter bridge. The first inductor L1, the second inductor L2, and the sixth capacitor C6 form an LCL filter circuit. The positive terminal of the first capacitor C1 is connected in series with the first resistor R1, and the negative terminal of the first capacitor C1 is connected to the collector of the fifth switch S5 and the second resistor R5. R2 is connected; the positive terminal of the second capacitor C2 is connected in series with the other end of the second resistor R2; the negative terminal of the second capacitor C2 is connected to the third resistor R3 and the seventh switch S7; the positive terminal of the third capacitor C3 is connected to the third resistor R3; the positive terminal of the fourth capacitor C4 is connected to the fourth resistor R4; the negative terminal of the fourth capacitor C4 is connected to the positive terminal of the fifth capacitor C5, the positive terminal of the first diode D1, and the negative terminal of the third diode D3; the negative terminal of the fifth capacitor C5 is connected to the fifth resistor R5; the positive terminal of the second diode D2 is connected to the emitter of the first switch S1, the collector of the third switch S3, the collector of the sixth switch S6, and the collector of the eighth switch S8. The collector of the ninth switch S9 is connected to the cathode of the first diode D1 and the cathode of the second diode D2. The emitter of the ninth switch S9 is connected to the anode of the third diode D3 and the anode of the fourth diode D4. The emitter of the sixth switch S6 is connected to the emitter of the fifth switch S5. The emitter of the eighth switch S8 is connected to the emitter and collector of the seventh switch S7. One side of the input terminal of the LCL filter circuit is connected to the emitter of the first switch S1 and the collector of the third switch S3, and the other side is connected to the emitter of the second switch S2 and the collector of the fourth switch S4. The output is connected to the load.

2. The novel nine-level H-type inverter device according to claim 1, characterized in that: The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, and the ninth switch S9 form a secondary circuit.

3. A novel nine-level H-type inverter device according to claim 1, characterized in that: The second resistor R2, the second capacitor C2, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 constitute a tertiary circuit.

4. A novel nine-level H-type inverter device according to claim 1, characterized in that: The fourth resistor R4 and the fourth capacitor C4, together with the fifth resistor R5 and the fifth capacitor C5, share the DC voltage and provide half of the input voltage at the midpoint M.

5. A novel nine-level H-type inverter device according to claim 1, characterized in that: The first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2, the third resistor R3, and the third capacitor C3 share the input voltage at point L in a 1:3 ratio.

6. A novel nine-level H-type inverter device according to claim 1, characterized in that: The first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2, and the third resistor R3 and the third capacitor C3 share the input voltage at point N in a 3:1 ratio.

7. A novel nine-level H-type inverter device according to claim 1, characterized in that... The voltages at point M and at points L and N are independent of each other.

8. A novel nine-level H-type inverter device according to claim 1, characterized in that... All switching transistors are insulated gate bipolar transistors (IGBTs).

9. A novel nine-level H-type inverter device according to claim 1, characterized in that: The secondary and tertiary loop circuits in the circuit can provide a path for current to flow.

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