Semiconductor package

Abstract

A semiconductor package includes: a package substrate including a horizontal top surface; an interposer bonded to a top surface of the package substrate; a semiconductor die bonded to the top surface of the interposer, the semiconductor die including a bottom surface facing the top surface of the interposer, and a plurality of chamfers formed in a plurality of corners of the bottom surface of the semiconductor die; and an encapsulant layer surrounding the semiconductor die and filling the chamfer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package, and more particularly to a semiconductor package with chamfers. Background Technology

[0002] The semiconductor industry continues to evolve due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. To a large extent, these improvements in integration density stem from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] Beyond smaller electronic components, improvements in component packaging seek to provide smaller packages that occupy less area than previous packages. Examples of semiconductor packaging types include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer-level packages (WLP), package-on-packages (PoP), system-on-chip (SoC), or system-on-integrated circuit (SoIC) devices. Some 3D devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing wafers on top of each other on a semiconductor wafer level. These 3D devices offer improved integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced interconnect lengths between stacked wafers. However, many challenges exist associated with 3D devices. Utility Model Content

[0004] This disclosure provides a semiconductor package. The semiconductor package includes a package substrate, an interposer, a semiconductor die, and an encapsulating layer. The package substrate includes a top surface extending in a horizontal direction. The interposer is bonded to the top surface of the package substrate. The semiconductor die is bonded to the top surface of the interposer. The semiconductor die includes a bottom surface and a plurality of chamfers, the bottom surface facing the top surface of the interposer, and the chamfers being formed in a plurality of corners of the bottom surface of the semiconductor die. The chamfers include a plurality of chamfered surfaces. The encapsulating layer surrounds the semiconductor die and contacts the chamfered surfaces. In some embodiments, the chamfered surfaces include: an upper surface facing the interposer; and a side surface extending from the upper surface to the bottom surface of the semiconductor die.

[0005] In some embodiments, the side surface extends between a first sidewall and a second sidewall adjacent to the semiconductor grain.

[0006] In some embodiments, the side surface includes: a first side surface defining a first vertical alignment plane; and a second side surface defining a second vertical alignment plane; and an interior angle formed between the first side surface and the second side surface ranging from 179° to 100°.

[0007] In some embodiments, the side surface includes: a first side surface defining a first vertical alignment plane; a second side surface defining a second vertical alignment plane; and a third side surface defining a third vertical alignment plane, wherein an interior angle formed between the first side surface and the second side surface ranges from 179° to 100°, and wherein an interior angle formed between the second side surface and the third side surface ranges from 179° to 100°.

[0008] In some embodiments, each of the chamfers includes an inclined side surface extending from an adjacent first sidewall and a second sidewall of the semiconductor die to the bottom surface of the semiconductor die, the inclined side surface having a slope ranging from 30° to 60°.

[0009] This disclosure provides a semiconductor package. The semiconductor package includes a package substrate, an interposer, a semiconductor die, a bonding layer, and an encapsulating layer. The package substrate includes a top surface extending in a horizontal direction. The interposer is bonded to the top surface of the package substrate. The semiconductor die is disposed on the interposer. The semiconductor die includes a bottom surface and a plurality of chamfers, the bottom surface facing the top surface of the interposer, the chamfers being formed in a plurality of corners of the bottom surface of the semiconductor die. The chamfers include a plurality of chamfered surfaces. The bonding layer bonds the semiconductor die to the interposer. The encapsulating layer is disposed on the bonding layer and surrounds the semiconductor die. The encapsulating layer extends between the semiconductor die and the interposer and contacts the chamfers.

[0010] In some embodiments, wherein: the semiconductor die has a semiconductor die width, a semiconductor die length, and a semiconductor die thickness; the vertical depth of each of the chamfers ranges from 0.5% to 75% of the semiconductor die thickness; the length of each of the chamfers ranges from 0.5% to 50% of the semiconductor die length; and the width of each of the chamfers ranges from 0.5% to 50% of the semiconductor die width.

[0011] In some embodiments, wherein: the vertical depth of each of the chamfers ranges from 0.5% to 20% of the semiconductor die thickness; the length of each of the chamfers ranges from 0.5% to 5% of the semiconductor die length; and the width of each of the chamfers ranges from 0.5% to 5% of the semiconductor die width.

[0012] In some embodiments, each of the above chamfers includes: an upper surface facing the interposer; and a side surface extending from the upper surface to the bottom surface of the semiconductor die, wherein the side surface includes: a first side surface defining a first vertical alignment plane; and a second side surface defining a second vertical alignment plane, and an interior angle formed between the first side surface and the second side surface ranges from 179° to 100°.

[0013] At least one embodiment of this utility model has the following advantages or technical effects:

[0014] A semiconductor package may include multiple semiconductor dies disposed on a package substrate. During the testing and / or assembly of a semiconductor package, the package may be subjected to thermal stress, which may lead to adhesive stress and / or delamination. Specifically, depending on the arrangement of the semiconductor dies on the package substrate, thermal stress may be concentrated at specific locations. Therefore, various embodiments provide semiconductor packages including stress-reducing structures configured to reduce the amount of thermal stress applied to the semiconductor package. Attached Figure Description

[0015] This disclosure of embodiments can be understood in more detail by reading the following detailed description and examples in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various feature components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various feature components can be arbitrarily increased or decreased.

[0016] Figure 1 This is a vertical cross-sectional view of a semiconductor die 100 according to various embodiments of the present disclosure.

[0017] Figure 2A This is a simplified top view of a semiconductor package 200 according to various embodiments of the present disclosure.

[0018] Figure 2B It is along Figure 2A The vertical cross-section of line segment A-A'.

[0019] Figure 2C It is along Figure 2A The vertical cross-section of line segment B-B'.

[0020] Figure 3A , Figure 3B , Figure 3C , Figure 3D ,as well as Figure 3E According to various embodiments of this disclosure Figure 2A A partially transparent magnified top view of the chamfered region Rl of a semiconductor die, showing that it may include... Figure 2C Various embodiments of the chamfer.

[0021] Figure 4 Various embodiments of this disclosure may include, in Figures 2A to 2C Vertical cross-section of an alternative chamfer in a semiconductor die.

[0022] Figure 5 This is a flowchart illustrating a method for forming a packaging substrate according to various embodiments of the present disclosure.

[0023] The annotations in the attached figures are explained as follows:

[0024] 100: Semiconductor die

[0025] 102: Semiconductor substrate

[0026] 104: Dielectric Structure

[0027] 104A: Dielectric layer, substrate oxide layer

[0028] 104B: Dielectric layer

[0029] 104C: Dielectric layer

[0030] 104D: Dielectric layer

[0031] 104E: Dielectric layer

[0032] 104F: Dielectric layer

[0033] 104G: Dielectric layer, passivation layer

[0034] 108: Substrate Electrode

[0035] 110: Interconnection Structure

[0036] 112: Metallic characteristics

[0037] 112A: First connecting line

[0038] 112B: Second connecting line

[0039] 112V: Through-hole structure

[0040] 112L: Wire

[0041] 120: Sealing ring

[0042] 130A: Front bonding layer

[0043] 130B: Backside bonding layer

[0044] 132A: Front-side bonding pad

[0045] 132B: Backside bonding pad

[0046] 140: Dielectric encapsulation layer

[0047] 162: Substrate through-hole structure

[0048] 200: Semiconductor Packaging

[0049] 202: Semiconductor die

[0050] 202p: Peripheral semiconductor die, peripheral die

[0051] 203: First sidewall

[0052] 205: Second sidewall

[0053] 210: Packaging substrate

[0054] 240: Sealing layer

[0055] 244: Bottom Filling Material

[0056] 250: Packaging ring

[0057] 252: Cover

[0058] R1: Chamfered area

[0059] L: Length

[0060] W: Width

[0061] A-A': Line segment

[0062] B-B': line segment

[0063] 207: Bottom surface

[0064] 212: Metal package trace

[0065] 214: Encapsulated ball

[0066] 220: Intermediary Layer

[0067] 222: Silicon substrate

[0068] 224: Redistribution layer

[0069] 226: Metal through-hole structure

[0070] 228: Characteristics of Conductive Metals

[0071] 230: Bonding layer

[0072] 230a: First bonding layer

[0073] 230b: Second bonding layer

[0074] 232: Joint pad structure

[0075] 232a: First bonding pad

[0076] 232b: Second bonding pad

[0077] 246: Substrate bonding structure

[0078] 254: Cyclic Adhesives

[0079] 258: Thermal interface materials

[0080] 300: Chamfer

[0081] 302: Upper surface

[0082] 304: Side surface

[0083] DT: Thickness

[0084] VD: Vertical Depth

[0085] HD: Horizontal Depth

[0086] 304p: Side surface

[0087] 302c: Corner

[0088] L1: Length

[0089] W1: Width

[0090] Δ1:Exterior angle

[0091] 304m: Multi-planar side surface

[0092] 304m1: First side surface

[0093] 304m2: Second side surface

[0094] Δ2:Exterior angle

[0095] θ1: interior angle

[0096] 304m3: Third side surface

[0097] θ2: interior angle

[0098] Δ3:Exterior angle

[0099] 300a: Chamfer

[0100] 304s: Inclined side surface

[0101] 500~512: Operation. Detailed Implementation

[0102] This disclosure provides many different embodiments or examples to implement the various features of this application. The following disclosure describes specific embodiments of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in the different embodiments of this disclosure below. These repetitions are for simplification and clarity and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0103] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the illustration. In addition to the orientations shown in the figures, these spatially related terms are intended to encompass different orientations of the device in use or operation. Furthermore, the device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way. Unless otherwise explicitly stated, each element with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0104] A semiconductor package may include multiple semiconductor dies disposed on a package substrate. During the testing and / or assembly of a semiconductor package, the package may be subjected to thermal stress, which may lead to adhesive stress and / or delamination. Specifically, depending on the arrangement of the semiconductor dies on the package substrate, thermal stress may be concentrated at specific locations. Therefore, various embodiments provide semiconductor packages including stress-reducing structures configured to reduce the amount of thermal stress applied to the semiconductor package.

[0105] Figure 1 This is a vertical cross-sectional view of a semiconductor die 100 according to various embodiments of the present disclosure. Reference Figure 1The semiconductor die 100 may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensing chip, a wireless and radio frequency chip, a voltage regulation chip, a memory chip, etc. In some embodiments, the semiconductor die 100 may include active components and / or passive components. In some embodiments, the semiconductor die 100 may include a planar semiconductor substrate 102, a dielectric structure 104, an interconnect structure 110 formed within the dielectric structure 104, a seal ring 120, and a through-substrate via (TSV) structure 162.

[0106] In some embodiments, the semiconductor substrate 102 may include elemental semiconductors (e.g., silicon or germanium) and / or compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide). In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate. In various embodiments, the semiconductor substrate 102 may be a planar substrate, a substrate with multiple fins, nanowires, or other forms known to those skilled in the art. Depending on the design requirements, the semiconductor substrate 102 may be a P-type substrate or an N-type substrate, and may include doped regions. The doped regions may be configured for N-type or P-type devices.

[0107] In some embodiments, the semiconductor substrate 102 includes an isolation structure defining at least one active region, and a device layer may be disposed on / in the active region. The device layer may include various devices. In some embodiments, the devices may include active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuit devices. This component may be a transistor, capacitor, resistor, diode, photodiode, fuse device, or other similar device. In some embodiments, the device layer includes a gate structure, source / drain regions, spacers, etc.

[0108] The dielectric structure 104 may be disposed on the front side of the semiconductor substrate 102. In some embodiments, the dielectric structure 104 may include silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low k) material, or a combination thereof. Other suitable dielectric materials are within the scope of this disclosure. The dielectric structure 104 may be a single-layer or multi-layer dielectric structure. For example, such as Figure 1As shown, the dielectric structure 104 may include multiple dielectric layers 104A to 104F, which may include a substrate oxide layer 104A, inter-layer dielectric (ILD) layers 104B to 104F, and a passivation layer 104G. However, although Figure 1 Seven dielectric layers are shown, but the various embodiments of this disclosure are not limited to any particular number of layers.

[0109] The dielectric structure 104 can be formed by any suitable deposition process. Here, "suitable deposition process" can include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc.

[0110] Interconnect structure 110 may be formed within dielectric structure 104. Interconnect structure 110 may include metal features 112 disposed in dielectric structure 104. Metal features 112 may be any of various metal lines and via structures electrically connecting metal lines of adjacent ILD layers 104B to 104F. Metal features 112 may include a first connection line 112A that can be used in a die-to-die connection circuit, as discussed in detail below. Metal features 112 may optionally include a second connection line 112B that can be used in a die-to-die connection circuit, also discussed below.

[0111] Interconnect structure 110 can be electrically connected to substrate electrode 108 disposed on semiconductor substrate 102, such that interconnect structure 110 can electrically interconnect semiconductor devices formed on semiconductor substrate 102. In some embodiments, substrate electrode 108 may include the metal gate of a transistor formed in the device layer of semiconductor substrate 102.

[0112] The interconnect structure 110 can be formed of any suitable conductive material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, silver (Ag), and combinations thereof. For example, the interconnect structure 110 may preferably comprise an atomic percentage of copper greater than 80% (e.g., greater than 90% and / or greater than 95%), but a larger or smaller percentage of copper may be used.

[0113] In some embodiments, a barrier layer (not shown) may be disposed between the metal feature 112 and the dielectric layer of the dielectric structure 104 to prevent material migration from the metal feature 112 to the semiconductor substrate 102. For example, the barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other suitable barrier layer materials are within the scope of this disclosure.

[0114] The sealing ring 120 may extend around the periphery of the semiconductor die 100. In other words, the sealing ring 120 may be disposed adjacent to a side surface of the semiconductor die 100. For example, the sealing ring 120 may be disposed in the dielectric structure 104 and may laterally surround the interconnect structure 110. The sealing ring 120 may be configured to protect the interconnect structure 110 from contaminant diffusion and / or physical damage during device processes (e.g., plasma etching and / or deposition processes).

[0115] The sealing ring 120 may comprise copper with an atomic percentage greater than 80%, such as greater than 90% and / or greater than 95%, but a larger or smaller percentage may be used. The sealing ring 120 may include interconnected wires and via structures, and may be formed simultaneously with the wires 112L and via structures 112V of the metal feature 112 of the interconnect structure 110. The sealing ring 120 may be electrically isolated from the metal feature 112.

[0116] In some embodiments, the metallic feature 112 and / or the sealing ring 120 can be formed by a dual damascene process or by multiple single damascene processes. A single damascene process typically forms a single feature at each damascene site and fills it with copper. A dual damascene process typically forms two features simultaneously and fills them with copper; for example, a trench and an overlapping through-hole can both be filled with a single copper deposition using a dual damascene process. In an alternative embodiment, the metallic feature 112 and / or the sealing ring 120 can be formed by an electroplating process.

[0117] For example, the damascene process may include patterning the dielectric structure 104 to form openings, such as trenches and / or vias (e.g., via holes). A deposition process may be performed to deposit a conductive metal (e.g., copper) in the openings. A planarization process (e.g., chemical-mechanical planarization (CMP)) may then be performed to remove excess copper (e.g., overburden) disposed on top of the dielectric structure 104.

[0118] Specifically, patterning, metal deposition, and planarization can be performed on each of the ILD layers 104B to 104F to form the interconnect structure 110 and / or sealing ring 120. For example, ILD layer 104B can be deposited and patterned to form openings. Deposition can then be performed to fill the openings in ILD layer 104B. A planarization process can then be performed to remove the capping layer and form a metal feature 112 in ILD layer 104B. These process operations can be repeated to form ILD layers 104C to 104F and the corresponding metal features 112, thereby completing the interconnect structure 110 and / or sealing ring 120.

[0119] A front bonding layer 130A may be disposed above the dielectric structure 104. The front bonding layer 130A may be formed of a dielectric bonding material. A front bonding pad 132A may be formed in the front bonding layer 130A. A back bonding layer 130B may be formed on the back side of the semiconductor substrate 102. However, in some embodiments, depending on the intended location of the semiconductor die 100, the back bonding layer 130B may be omitted.

[0120] The back bonding pad 132B can be formed in the back bonding layer 130B.

[0121] The front bonding layer 130A and the back bonding layer 130B can be formed by depositing bonding materials using any suitable deposition method. Suitable bonding materials may include silicon dioxide or adhesive polymers as described above, such as epoxy resins, polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO). Other suitable bonding materials are within the scope of this disclosure. The front bonding pad 132A and the back bonding pad 132B may be conductive features formed of the same material as metallic feature 112. For example, the front bonding pad 132A and the back bonding pad 132B may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof.

[0122] A dielectric encapsulation (DE) layer 140 may be formed on the side surface of the semiconductor die 100. The DE layer 140 may be formed of a dielectric material, such as silicon oxide, silicon nitride, or a molding compound including resin and filler. The DE layer 140 may be formed by any suitable deposition process, such as spin coating, lamination, or deposition.

[0123] TSV structure 162 can be disposed in a trench formed in semiconductor substrate 102. TSV structure 162 can be electrically connected to interconnect structure 110 and back bonding pad 132B. TSV structure 162 can be formed of a suitable conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, silver (Ag), tungsten (W), and combinations thereof. For example, TSV structure 162 can preferably include an atomic percentage of copper greater than 80% (e.g., greater than 90% and / or greater than 95%), but a larger or smaller percentage of copper can be used.

[0124] In some embodiments, a barrier layer may be disposed between the TSV structure 162 and the semiconductor substrate 102 and dielectric structure 104. For example, the barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other suitable barrier layer materials are within the scope of this disclosure.

[0125] Semiconductor packages including those with stress-reduction chamfers.

[0126] Figure 2A This is a simplified top view of a semiconductor package 200 according to various embodiments of the present disclosure. Figure 2B It is along Figure 2A The vertical cross-section of line segment A-A'. Figure 2C It is along Figure 2A The vertical cross-section of line segment B-B'.

[0127] refer to Figure 1 , Figure 2A , Figure 2B and Figure 2C The semiconductor package 200 may include a package substrate 210, an interposer 220 disposed on the package substrate 210, and one or more semiconductor dies 202 disposed on the interposer 220 (e.g., those on the package substrate 210). Figure 1 The semiconductor die 100 described herein, the encapsulation ring 250 disposed on the perimeter of the encapsulation substrate 210, the cover 252 disposed on the encapsulation ring 250, the ring adhesive 254 for bonding the encapsulation ring 250 to the encapsulation substrate 210 and / or the cover 252, and the thermal interface material 258 for bonding the semiconductor die 202 to the cover 252.

[0128] The packaging substrate 210 can be any suitable packaging substrate, such as a polymer substrate, an organic resin substrate, a laminated substrate, a printed circuit board, etc. Common laminated substrates include fiberglass-reinforced epoxy-laminated sheet (FR4) substrates and bismaleimide-triazine (BT) substrates. The packaging substrate 210 may include metal packaging traces 212 electrically connected to the corresponding packaging balls 214 (e.g., solder balls).

[0129] In various embodiments, semiconductor die 202 may each include semiconductor die 100, such as Figure 1 As shown. In some embodiments, semiconductor package 200 may include a plurality of vertically stacked and interconnected semiconductor dies 202. Semiconductor dies 202 may be any suitable type of semiconductor device or wafer, depending on the intended function of semiconductor package 200. For example, semiconductor dies 202 may include system-on-a-chip (SoC) dies, flip-chip (FC) dies, 3D integrated circuit (3DIC) dies, wafer-level package (WLP) dies, stacked package (PoP) dies, system-on-a-chip (SoIC) devices, application-specific integrated circuit (ASIC) devices, etc.

[0130] In some embodiments, semiconductor die 202 may include logic devices and memory elements, such as high bandwidth memory (HBM) devices, dynamic random access memory (DRAM) devices, etc. In some embodiments, semiconductor package 200 may include peripheral semiconductor dies 202p disposed around semiconductor die 202. Peripheral semiconductor dies 202p may be electrically connected to package substrate 210 without interposer 220. In some embodiments, semiconductor die 202 may include SoC and / or ASIC devices, and peripheral semiconductor dies 202p may include logic devices and memory devices, such as high bandwidth memory (HBM) devices, dynamic random access memory (DRAM) devices, etc. However, this disclosure is not limited to any particular type of semiconductor die 202 and peripheral semiconductor die 202p.

[0131] Semiconductor die 202 may include opposing first sidewalls 203 extending in the X direction and opposing second sidewalls 205 extending in the Y direction. The X and Y directions may be perpendicular to each other, and both may be horizontal (e.g., disposed in a horizontal plane). The thickness DT of semiconductor die 202 can be measured perpendicularly in the Z direction, which is perpendicular to the horizontal X and Y directions. For example, as... Figure 2CAs shown, the thickness DT of the semiconductor die 202 can be measured in the vertical Z direction. Each semiconductor die 202 may have a length L measured in a first horizontal direction (e.g., the X direction) and a width W measured in a second horizontal direction (e.g., the Y direction). In some embodiments, the length L and width W may be the same. In other embodiments, the width W may be greater than the length L, or the length L may be greater than the width W.

[0132] Interposer 220 can be configured to electrically connect semiconductor die 202 to package substrate 210. For example, interposer 220 can be a silicon interposer, a redistribution layer (RDL) interposer, a chip-on-wafer-on-substrate (CoWoS) interposer (which may include silicon), etc. For example, a CoWoS interposer may include a chip-on-wafer-on-substrate redistribution layer (CoWoS-R) interposer and a chip-on-wafer-on-substrate local silicon interconnect bridge (CoWoS-L) interposer.

[0133] The encapsulation ring 250 may extend around the periphery of the encapsulation substrate 210 to surround the interposer layer 220 and the semiconductor die 202. The encapsulation ring 250 may be formed of a first metal or metal alloy, such as stainless steel (e.g., SUS304 or SUS440).

[0134] The cover 252 (also referred to as the lid) can be formed of a second metal or metal alloy with high thermal conductivity, such as copper, gallium, titanium, and their alloys. The cover 252 can have a thickness T1 ranging from 50 μm to 3500 μm, for example from 100 μm to 3000 μm, but larger or smaller thicknesses can be used.

[0135] The thermal interface material 258 can be formed from any suitable adhesive material with high thermal conductivity. For example, the thermal interface material 258 can be thermal paste, thermal adhesive, thermal gap filler, thermal pad, thermal tape, metal thermal interface material, etc. The thermal interface material 258 and / or the annular adhesive 254 can be applied as a layer with a thickness T3 ranging from 20 μm to 250 μm (e.g., 30 μm to 200 μm), but larger or smaller thicknesses can be used.

[0136] In various embodiments, the semiconductor die 202 may be laterally surrounded by a molding layer 240 (e.g., a dielectric encapsulation layer). The molding layer 240 may be formed of a dielectric material, such as an encapsulation compound comprising resin and fillers. The molding layer 240 may be formed by any suitable deposition process, such as spin coating, lamination, deposition, etc. After deposition, the molding layer 240 may be cured using heat and / or light.

[0137] Interposer 220 and peripheral semiconductor die 202p can be electrically connected to package substrate 210 via substrate bonding structure 246. Underfill material 244 (e.g., resin) can be disposed below interposer 220 and peripheral semiconductor die 202p, surrounding substrate bonding structure 246. In some embodiments, substrate bonding structure 246 may include bonding pads and solder balls or microbumps.

[0138] Semiconductor die 202 can be connected to interposer 220 via bonding layer 230 and bonding pad structure 232. Bonding layer 230 may include a dielectric material, such as silicon oxide. Bonding pad structure 232 may include a metal (such as copper) and may be configured to electrically connect semiconductor die 202 to interposer 220.

[0139] The bonding layer 230 can be formed by bonding a first bonding layer 230a formed on the semiconductor die 202 and a second bonding layer 230b formed on the interposer layer 220. A first bonding pad 232a can be disposed in the first bonding layer 230a, and a second bonding pad 232b can be disposed in the second bonding layer 230b. In various embodiments, a hybrid fusion bonding process can be performed to bond the first bonding layer 230a and the second bonding layer 230b and form the bonding layer 230, and to fuse the first bonding pad 232a and the second bonding pad 232b and form the bonding pad structure 232. In some embodiments, the first bonding layer 232a and the second bonding layer 232b can be formed of silicon oxide, and the first bonding pad 232a and the second bonding pad 232b can be formed of copper or a copper alloy.

[0140] In various embodiments, the interposer 220 may include a silicon substrate 222 and at least one redistribution layer 224 disposed thereon. The silicon substrate 222 may include a metal via structure 226 electrically connected to the substrate bonding structure 246. The redistribution layer 224 may include a conductive metal feature 228 configured to electrically connect the bonding pad structure 232 to the metal via structure 226.

[0141] Stress may accumulate in certain areas of the semiconductor package 200. For example, thermal stress may accumulate due to differences in the coefficient of thermal expansion (CTE) between the interposer 220, bonding layer 230, and / or semiconductor die 202. For example, thermal stress may be concentrated at the corners of the semiconductor die 202 and the portion below the interposer 220 and / or may accumulate below adjacent portions of the encapsulant layer 240.

[0142] like Figure 2C As shown, a chamfer 300 can be formed at the corner of the semiconductor die 202. Specifically, the chamfer 300 can be formed by removing at least a lower portion of one or more corners of the semiconductor die 202, including the corresponding corner portion of the bottom surface 207 of the semiconductor die 202. In other words, the chamfer 300 can be a recess formed in the corner of the bottom surface 207 of the semiconductor die 202, including the corner portions of adjacent first sidewalls 203 and second sidewalls 205 of each semiconductor die 202. The chamfer 300 can be formed using any suitable method, such as cutting at least multiple portions of the corner of the semiconductor die 202 using a die saw or the like. For example, in some embodiments, the chamfer 300 can be formed by cutting at least multiple corners of the semiconductor substrate of the semiconductor die 202.

[0143] In some embodiments, the chamfer 300 may include a side surface 304 and a top surface 302. The top surface 302 may face the interposer 220 and may be horizontally aligned. The side surface 304 may extend from the top surface 302 to the bottom surface 207 of the semiconductor die 202. An encapsulating layer 240 may be disposed in the chamfer 300. For example, after the semiconductor die 202 is bonded to the interposer 220, the chamfer 300 may be filled with the encapsulating material of the encapsulating layer 240.

[0144] The chamfer 300 may have a vertical depth VD and a horizontal depth HD measured in a first vertical direction (e.g., the Z direction). In various embodiments, the vertical depth VD may be greater than zero and less than or equal to the grain thickness DT. For example, the vertical depth VD may range from 0.5% to 75% of the grain thickness DT, such as 1% to 50%, or 10% to 25%. In some embodiments, the vertical depth VD may be limited to 50% or less of the grain thickness DT, such as 25% or less, in order to reduce the amount of stress applied to the bonding layer 230 by the encapsulating layer 240.

[0145] As shown below Figures 3A to 3DIn detail, the horizontal depth HD of the chamfer can represent the horizontal thickness of the semiconductor die 202 obtained from the uncut corner of the semiconductor die 202 above the chamfer 300 to the nearest vertical sidewall of the chamfer 300. In various embodiments, the horizontal depth HD can be greater than zero and less than 7500 μm, for example, from 1 μm to 6000 μm, or from 100 μm to 5000 μm. In some embodiments, the horizontal depth can preferably be in the range of greater than zero to 1000 μm, for example, from about 1 μm to 1000 μm, in order to reduce grain stress while minimizing the volume reduction of the semiconductor die 202.

[0146] Figures 3A to 3E Various embodiments according to this disclosure Figure 2A A partially transparent magnified top view of the chamfered region Rl of the semiconductor die 202, showing that it may include... Figure 2C Different configurations (e.g., shapes) in the chamfer. Figures 3A to 3E Implementations may include similar features. Therefore, the description of these features need not be repeated.

[0147] refer to Figure 3A The chamfer 300 may include a chamfered surface. The chamfered surface may include a side surface 304p of the plane and a top surface 302 of the plane (indicated by dashed lines). The side surface 304p may define a substantially perpendicular plane (e.g., the side surface 304p may be completely parallel to...). Figure 2B The upper surface 302 can define a generally horizontal plane (e.g., the upper surface 302 can be entirely positioned in a plane extending parallel to the X and Y directions). The horizontal depth HD of the chamfer 300 can be measured between the vertical corner 302c of the upper surface 302 (e.g., the corner of the upper surface defined at least partially by the adjacent first sidewall 203 and second sidewall 205 of the semiconductor die 202) and the side surface 304p of the plane. In other words, the horizontal depth HD can represent the minimum distance between the corner 302c and the side surface 304p of the plane.

[0148] The chamfer 300 may have a width W1 cut off in a first horizontal direction (e.g., the X direction) and a length L1 cut off in a second horizontal direction (e.g., the Y direction). The width W1 and the length L1 may be substantially the same (e.g., within + / - 5%). Thus, the exterior angle Δ1 formed between the side surface 304p of the plane and the X direction may be in the range of 30° to 60°, for example, 40° to 50°, or may be about 45°. In some embodiments, the width W1 and the length L1 may be smaller than the semiconductor die 202 (see...). Figure 2AThe width W and length L1 of the semiconductor die 202 can be 50% of its width W and length L. For example, the width W1 can range from 0.5% to 50%, such as 1% to 24%, or 1.5% to 10%, of the width W of the semiconductor die 202, and the length L1 can range from 0.5% to 50%, such as 1% to 24%, or 1.5% to 10%, of the length L of the semiconductor die 202. In some embodiments, the width W1 and length L1 can preferably be 5% of the width W and length L of the semiconductor die 202 or less than the width W and length L of the semiconductor die 202, in order to reduce grain stress while minimizing the volume reduction of the semiconductor die 202. For example, the width W1 can be in the range of 0.5% to 5% of the width W, and the length L1 can be in the range of 0.5% to 5% of the length L.

[0149] refer to Figure 3B The chamfer 300 may include a multi-planar side surface 304m and a planar upper surface 302 (represented by dashed lines). Specifically, the multi-planar side surface 304m may include a first side surface 304m1 that defines a first vertical alignment plane and a second side surface 304m2 that defines a second vertical alignment plane.

[0150] Here, "interior angle" can be an angle formed inside the semiconductor die 202, and "exterior angle" can be an angle formed outside the semiconductor die 202. The range of the interior angle θ1 formed between the first side surface 304m1 and the second side surface 304m2 can be from 179° to 100°, for example, from 150° to 175°. The exterior angle Δ1 formed between the first side surface 304m1 and the X direction and the exterior angle Δ2 formed between the second side surface 304m2 and the X direction can each be less than 90°. In some embodiments, the sum of the exterior angles Δ1 and Δ2 can be less than 90°. In some embodiments, angle Δ1 can be less than angle Δ2. Therefore, with Figure 3A Compared to the planar side surface 304p, the multi-planar side surface 304m can increase stress reduction.

[0151] The width W1 and length L1 of the chamfer 300 can be substantially the same. In some embodiments, the width W1 and length L1 can be smaller than the semiconductor die 202 (see...). Figure 2AThe width W and length L of the semiconductor die 202 are 50%. For example, the width W and length L can be in the range of 0.5% to 50% of the corresponding width W and length L of the semiconductor die 202, such as 1% to 24%, or 1.5% to 10%. The first side surface 304m1 and the second side surface 304m2 can have substantially the same area (e.g., having + / - 5%). In some embodiments, the horizontal distance HD can be measured between the corner 302c of the upper surface 302 and the nearest portion of the multiplanar side surface 304m. In some embodiments, the horizontal distance HD can be measured between the corner 302c and the intersection of the first side surface 304m1 and the second side surface 304m2.

[0152] refer to Figure 3C The chamfer 300 may include a multi-planar side surface 304m and a planar upper surface 302 (indicated by dashed lines). Specifically, the multi-planar side surface 304m may include a first side surface 304m1 defining a first vertical alignment plane and a second side surface 304m2 defining a second vertical alignment plane. The interior angle θ1 formed between the first side surface 304m1 and the second side surface 304m2 may be in the range of about 179° to about 100°, for example, about 150° to about 175°.

[0153] The width W1 and length L1 of the chamfer 300 can be different. For example, the length L1 can be greater than the width W1. As a result, in some embodiments, the first side surface 304m1 can have a smaller area than the second side surface 304m2.

[0154] refer to Figure 3D The chamfer 300 may include a multi-planar side surface 304m and a planar upper surface 302 (indicated by dashed lines). Specifically, the multi-planar side surface 304m may include a first side surface 304m1 defining a first vertical alignment plane and a second side surface 304m2 defining a second vertical alignment plane. The interior angle θ1 formed between the first side surface 304m1 and the second side surface 304m2 may be in the range of about 179° to about 100°, for example, about 150° to about 175°.

[0155] The chamfer 300 may have a width W1 cut along the X direction and a length L1 cut along the Y direction. The width W1 and the length L1 may be different. For example, the length L1 may be less than the width W1. In this way, in some embodiments, the first side surface 304m1 may have a larger area than the second side surface 304m2.

[0156] refer to Figure 3EThe chamfer 300 may include a multi-planar side surface 304m and a planar upper surface 302 (represented by dashed lines). Specifically, the multi-planar side surface 304m may include a first side surface 304m1 defining a first vertical alignment plane, a second side surface 304m2 defining a second vertical alignment plane, and a third side surface 304m3 defining a third vertical alignment plane. The first side surface 304m1, the second side surface 304m2, and the third side surface 304m3 may be at an angle relative to each other.

[0157] For example, the interior angle θ1 formed between the first side surface 304m1 and the second side surface 304m2, and the interior angle θ2 formed between the second side surface 304m2 and the third side surface 304m3, can each be less than 180° and greater than 90°. For example, angles θ2 and θ3 can each be in the range of 179° to 100°, such as 175° to 125°, or 170° to 130°. The exterior angle Δ1 formed between the first side surface 304m1 and the X direction, the exterior angle Δ2 formed between the second side surface 304m2 and the X direction, and the exterior angle Δ3 formed between the third side surface 304m3 and the X direction can each be less than 90°. In some embodiments, the sum of exterior angles Δ1, Δ2, and Δ3 can be less than 90°.

[0158] Therefore, with Figure 3B Compared to the multi-plane side surface of the two planes, 304m Figure 3E The three-plane multi-plane side surface 304m can increase stress reduction. In other embodiments, the chamfer 300 may include a multi-plane side surface having more than three plane surfaces, such as four to ten or more plane surfaces.

[0159] Figure 4 Various embodiments of this disclosure may include, in Figures 2A to 2C A vertical cross-sectional view of the alternative chamfer 300a in semiconductor die 202. (Reference) Figure 4 The chamfer 300a may include an inclined side surface 304s and may omit the top surface. Specifically, the inclined side surface 304s may be inclined relative to the vertical Z direction. For example, in some embodiments, the slope of the inclined side surface 304s relative to the Z direction may be in the range of 30° to 60°, such as 40° to 50°, or may be about 45°. Therefore, depending on the slope of the inclined side surface 304s, the horizontal depth HD and vertical depth VD of the chamfer 300 may be the same or different.

[0160] The inclined side surface 304s can be located on the adjacent first sidewall 203 and second sidewall 205 of the semiconductor die 202 (see...). Figure 2A Extending between ) . The inclined side surface 304s can be planar, such as Figure 3AAs shown. In this way, the chamfer 300a can be formed by a single cut using an angled die saw. Alternatively, the inclined side surface 304s can be multi-planar, such as... Figures 3B to 3E As shown. In such an embodiment, the inclined side surface 304s can be formed by multiple cuts using an angled grain saw.

[0161] In various embodiments, the horizontal depth HD and vertical depth VD of the chamfer 300a may be the same or different. The range of the exterior angle Δ1 formed between the planar side surface 304p and the X direction can be from 30° to 60°, for example from 40° to 50°, or it can be about 45°, depending on the relative dimensions of the horizontal depth HD and the vertical depth VD.

[0162] According to various embodiments, chamfer 300a can be configured to reduce stress accumulation under the corner of semiconductor die 202, which may be caused by CTE differences between the interposer layer 220, semiconductor die 202, and / or encapsulant layer 240. Specifically, chamfer 300a can reduce thermal stress accumulation in the interposer layer 220 adjacent to the corner of semiconductor die 202.

[0163] Figure 5 This is a flowchart illustrating a method for forming a display packaging substrate according to various embodiments of the present disclosure. (See also...) Figure 2A , Figure 2B and Figure 5 In operation 500, the method may include bonding the interposer 220 to the package substrate 210.

[0164] In operation 502, the semiconductor die 202 can be cut to form a chamfer 300 at the corner of the bottom surface of the semiconductor die 202. For example, a die saw can be used to cut the semiconductor die 202 to form the chamfer 300, such as... Figures 3A to 4 As shown.

[0165] In operation 504, the bottom surface of semiconductor die 202 may be bonded to interposer 220. For example, bonding may include using a hybrid fusion bonding process.

[0166] In operation 506, an encapsulating layer 240 may be formed around the semiconductor die 202. In operation 508, the peripheral die 202p may optionally be bonded to the package substrate 210.

[0167] In operation 510, the encapsulation ring 250 may be bonded to the encapsulation substrate 210. The encapsulation ring 250 may surround the semiconductor die 202 and the peripheral die 202p. In operation 512, the cover 252 may be bonded to the encapsulation ring 250. In some embodiments, a thermal interface material 258 may be used to bond the semiconductor die 202 to the cover 252.

[0168] In some embodiments, operation 504 may include cutting a plurality of semiconductor dies 202 to form a chamfer 300, and operation 504 may include bonding the semiconductor dies 202 to an interposer layer 220.

[0169] Various embodiments provide a semiconductor package 200, which may include: a package substrate 210 including a horizontal top surface; an interposer 220 bonded to the top surface of the package substrate 210; a semiconductor die 202 bonded to the interposer 220, the semiconductor die 202 including a bottom surface 207 facing the top surface of the interposer 220 and a chamfer 300 formed in a corner of the bottom surface of the semiconductor die 202, wherein the chamfer 300 includes chamfered surfaces (e.g., 302, 304, 304m1, 304m2); and an encapsulating layer 240 surrounding the semiconductor die 202 and contacting the chamfered surfaces (e.g., 302, 304, 304m1, 304m2).

[0170] In some embodiments, the chamfered surface includes an upper surface 302 facing the interposer layer 220 and a side surface 304 extending from the upper surface 302 to the bottom surface 207 of the semiconductor die 202. In some embodiments, the side surface 304 extends between adjacent first and second sidewalls of the semiconductor die 202. In various embodiments, the side surface 304 defines a single vertical alignment plane.

[0171] In various embodiments, the chamfer 300 may include a multi-planar side surface 304m, which includes a first side surface 304m1 defining a first vertical alignment plane, a second side surface 304m2 defining a second vertical alignment plane, and a third side surface 304m3 defining a third vertical alignment plane. The interior angle formed between the first side surface 304m1 and the second side surface 304m2 may be in the range of 179° to 100°. The interior angle formed between the second side surface 304m2 and the third side surface 304m3 may be in the range of 179° to 100°. The area of ​​the first side surface 304m1 may be larger than the area of ​​the second side surface 304m2.

[0172] In various embodiments, the vertical depth VD of each chamfer 300 ranges from 0.5% to 75% of the thickness DT of the semiconductor die 202. In some embodiments, the vertical depth VD may preferably be 20% of the thickness DT or less than the thickness DT, for example, 0.5% to 20% of the thickness DT, in order to reduce die stress while minimizing volume reduction of the semiconductor die 202. The minimum horizontal distance HD between the vertical corner 302c of the upper surface 302 and the side surface 304 may be less than 5000 micrometers (μm). In various embodiments, each chamfer 300 includes an inclined side surface 304s extending from adjacent first sidewalls 203 and second sidewalls 205 of the semiconductor die to the bottom surface of the semiconductor die, the inclined side surface having a slope ranging from 30° to 60°, in order to reduce wafer stress while minimizing volume reduction of the semiconductor die 202.

[0173] In some embodiments, the semiconductor package 200 may further include: a peripheral die 202p disposed around the semiconductor die 202 and bonded to the package substrate 210; a package ring 250 disposed on the periphery of the package substrate 210 and surrounding the semiconductor die 202 and the peripheral die 202p; and a cover 252 disposed on the package ring 250.

[0174] According to various embodiments, a semiconductor package 200 is provided, comprising: a package substrate 210 including a horizontal top surface; an interposer 220 bonded to the top surface of the package substrate 210; a semiconductor die 202 disposed on the interposer, the semiconductor die 202 including a bottom surface 207 facing the top surface of the interposer 220 and a chamfer 300 formed in a corner of the bottom surface of the semiconductor die 202, wherein the chamfer 300 includes chamfered surfaces (e.g., 302, 304, 304m1, 304m2); a bonding layer 230 bonding the semiconductor die to the interposer; and an encapsulating layer 240 disposed on the bonding layer and surrounding the semiconductor die, the encapsulating layer 240 extending between the semiconductor die 202 and the interposer 220 and contacting the chamfered surfaces.

[0175] According to various embodiments, a semiconductor package 200 is provided, comprising: a package substrate 210 including a horizontal top surface; an interposer layer 220 bonded to the top surface of the package substrate 210; a first semiconductor die 202 bonded to the top surface of the interposer layer 220; a second semiconductor die 202 bonded to the top surface of the interposer layer 220 adjacent to the top surface of the first semiconductor die 202; and an encapsulating layer 240 surrounding the first semiconductor die 202 and the second semiconductor die 202; and a peripheral die 202p bonded to the package substrate 210 adjacent to the interposer layer 220. The first and second semiconductor dies 202 each include: a bottom surface facing the top surface of the interposer layer; and a chamfer 300 formed in a corner of the bottom surface 207, wherein the chamfer 300 includes a chamfered surface, and the encapsulating layer 240 contacts the chamfered surface.

[0176] In one exemplary aspect, this disclosure relates to a semiconductor package. The semiconductor package includes a package substrate, an interposer, a semiconductor die, and an encapsulating layer. The package substrate includes a top surface extending in a horizontal direction. The interposer is bonded to the top surface of the package substrate. The semiconductor die is bonded to the top surface of the interposer. The semiconductor die includes a bottom surface and a plurality of chamfers, the bottom surface facing the top surface of the interposer, the chamfers being formed in a plurality of corners of the bottom surface of the semiconductor die. The chamfers include a plurality of chamfered surfaces. The encapsulating layer surrounds the semiconductor die and contacts the chamfered surfaces.

[0177] In some embodiments, the chamfered surface includes an upper surface facing the interposer and a side surface extending from the upper surface to the bottom surface of the semiconductor die.

[0178] In some embodiments, the side surface extends between adjacent first and second sidewalls of the semiconductor die.

[0179] In some embodiments, the side surface defines a single vertical alignment plane.

[0180] In some embodiments, the side surface includes a first side surface defining a first vertical alignment plane and a second side surface defining a second vertical alignment plane. The interior angle formed between the first side surface and the second side surface ranges from 179° to 100°.

[0181] In some embodiments, the area of ​​the first side surface is greater than the area of ​​the second side surface.

[0182] In some embodiments, the area of ​​the first side surface is equal to the area of ​​the second side surface.

[0183] In some embodiments, the side surface includes a first side surface defining a first vertical alignment plane, a second side surface defining a second vertical alignment plane, and a third side surface defining a third vertical alignment plane. The interior angle formed between the first and second side surfaces ranges from 179° to 100°. The interior angle formed between the second and third side surfaces ranges from 179° to 100°.

[0184] In some embodiments, the vertical depth of each chamfer ranges from 0.5% to 75% of the thickness of the semiconductor die.

[0185] In some embodiments, the minimum horizontal distance between the vertical angle of the upper surface and the side surface is less than 5000 μm.

[0186] In some embodiments, the minimum horizontal distance ranges from 100 μm to 5000 μm.

[0187] In some embodiments, each of the chamfers includes an inclined side surface extending from adjacent first and second sidewalls of the semiconductor die to the bottom surface of the semiconductor die, the inclined side surface having a slope ranging from 30° to 60°.

[0188] In some embodiments, the semiconductor package further includes a plurality of peripheral dies, a package ring, and a cap. The peripheral dies are disposed around the semiconductor dies and bonded to the package substrate. The package ring is disposed on the periphery of the package substrate and surrounds the semiconductor dies and the peripheral dies. The cap is disposed on the package ring.

[0189] In another exemplary aspect, this disclosure relates to a semiconductor package. The semiconductor package includes a package substrate, an interposer, a semiconductor die, a bonding layer, and an encapsulating layer. The package substrate includes a top surface extending in a horizontal direction. The interposer is bonded to the top surface of the package substrate. The semiconductor die is disposed on the interposer. The semiconductor die includes a bottom surface and a plurality of chamfers, the bottom surface facing the top surface of the interposer, the chamfers being formed in a plurality of corners of the bottom surface of the semiconductor die. The chamfers include a plurality of chamfered surfaces. The bonding layer bonds the semiconductor die to the interposer. The encapsulating layer is disposed on the bonding layer and surrounds the semiconductor die. The encapsulating layer extends between the semiconductor die and the interposer and contacts the chamfers.

[0190] In some embodiments, the semiconductor die has a semiconductor die width, a semiconductor die length, and a semiconductor die thickness; the vertical depth of each chamfer ranges from 0.5% to 75% of the semiconductor die thickness; the length of each chamfer ranges from 0.5% to 50% of the semiconductor die length; and the width of each chamfer ranges from 0.5% to 50% of the aforementioned semiconductor die width.

[0191] In some embodiments, the vertical depth of each chamfer ranges from 0.5% to 20% of the semiconductor grain thickness, the length of each chamfer ranges from 0.5% to 5% of the semiconductor grain length, and the width of each chamfer ranges from 0.5% to 5% of the semiconductor grain width.

[0192] In some embodiments, each of the chamfers includes an upper surface facing the interposer and a side surface extending from the upper surface to the bottom surface of the semiconductor die. The side surfaces define a first side surface that defines a first vertical alignment plane and a second side surface that defines a second vertical alignment plane. The interior angle formed between the first and second side surfaces ranges from 179° to 100°.

[0193] In another exemplary aspect, this disclosure relates to a method of forming a semiconductor package. The method of forming a semiconductor package includes bonding an interposer to a top surface of a package substrate; dicing a semiconductor die to form a plurality of chamfers at a plurality of corners of a bottom surface of the semiconductor die; bonding the bottom surface of the semiconductor die to a top surface of the interposer; and forming an encapsulating layer surrounding the semiconductor die and contacting the chamfers.

[0194] In some embodiments, the semiconductor die cutting operation includes using a die saw to cut the aforementioned corners, such that each chamfer includes an upper surface facing the interposer and a side surface extending from the upper surface to the bottom surface of the semiconductor die.

[0195] In some embodiments, the method of forming a semiconductor package further includes bonding a plurality of peripheral dies to a package substrate on opposite sides of the semiconductor dies; bonding a package ring to the periphery of the package substrate; and bonding a cover to the package ring, wherein the semiconductor dies are mixed and fused to the package substrate.

[0196] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A semiconductor package, characterized in that, include: A packaging substrate includes a top surface extending in a horizontal direction; An intermediate layer is bonded to the top surface of the aforementioned packaging substrate; A semiconductor die is bonded to a top surface of the aforementioned interposer, the semiconductor die comprising: A bottom surface, facing the top surface of the aforementioned intermediate layer; as well as Multiple chamfers are formed at multiple corners of the bottom surface of the semiconductor die, wherein the chamfers comprise multiple chamfered surfaces; and An adhesive layer surrounds the semiconductor grain and contacts the chamfered surface.

2. The semiconductor package as described in claim 1, characterized in that, The aforementioned chamfered surfaces include: The top surface faces the aforementioned intermediate layer; and One side surface extends from the above-mentioned upper surface to the above-mentioned bottom surface of the above-mentioned semiconductor grain.

3. The semiconductor package as described in claim 2, characterized in that, The aforementioned side surface extends between a first sidewall and a second sidewall adjacent to the semiconductor grain.

4. The semiconductor package as described in claim 3, characterized in that, in: The aforementioned side surface includes: A first side surface, defining a first vertical alignment plane; and A second side surface, defining a second vertical alignment plane; and The range of the interior angle formed between the first side surface and the second side surface is 179° to 100°.

5. The semiconductor package as described in claim 3, characterized in that, The aforementioned side surface includes: A first side surface defines a first vertical alignment plane; A second side surface, defining a second vertical alignment plane; and A third side surface, defining a third vertical alignment plane. The interior angle formed between the first side surface and the second side surface ranges from 179° to 100°. The range of the interior angle formed between the second side surface and the third side surface is 179° to 100°.

6. The semiconductor package as described in claim 1, characterized in that, Each of the aforementioned chamfers includes an inclined side surface extending from an adjacent first sidewall and a second sidewall of the semiconductor grain to the bottom surface of the semiconductor grain, the inclined side surface having a slope ranging from 30° to 60°.

7. A semiconductor package, characterized in that, include: A packaging substrate includes a top surface extending in a horizontal direction; An intermediate layer is bonded to the top surface of the aforementioned packaging substrate; A semiconductor die is disposed on the aforementioned interposer layer, the semiconductor die comprising: A bottom surface, and a top surface facing the aforementioned intermediate layer; and Multiple chamfers are formed at multiple corners of the bottom surface of the semiconductor die, wherein the chamfers include multiple chamfered surfaces; A bonding layer is used to bond the semiconductor die to the interposer layer; and An encapsulating layer is disposed on the bonding layer and surrounding the semiconductor die, the encapsulating layer extending between the semiconductor die and the interposer and contacting the chamfer.

8. The semiconductor package as described in claim 7, characterized in that, in: The aforementioned semiconductor die has a semiconductor die width, a semiconductor die length, and a semiconductor die thickness; The vertical depth of each of the above chamfers ranges from 0.5% to 75% of the thickness of the semiconductor grain; The length of each of the aforementioned chamfers ranges from 0.5% to 50% of the length of the aforementioned semiconductor die; and The width of each of the above chamfers ranges from 0.5% to 50% of the width of the semiconductor die.

9. The semiconductor package as described in claim 8, characterized in that, in: The vertical depth of each of the above chamfers ranges from 0.5% to 20% of the semiconductor grain thickness; The length of each of the aforementioned chamfers ranges from 0.5% to 5% of the length of the aforementioned semiconductor die; and The width of each of the aforementioned chamfers ranges from 0.5% to 5% of the width of the aforementioned semiconductor die.

10. The semiconductor package as claimed in claim 7, characterized in that, Each of the above-mentioned chamfers includes: The top surface faces the aforementioned intermediate layer; and One side surface extends from the aforementioned upper surface to the aforementioned bottom surface of the aforementioned semiconductor grain. The aforementioned side surface includes: A first side surface, defining a first vertical alignment plane; and A second side surface, defining a second vertical alignment plane. The range of the interior angle formed between the first side surface and the second side surface is 179° to 100°.

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