Carrier tape for loading chips

Abstract

The utility model provides a carrier tape for loading a chip, comprising a first structure unit layer comprising a first substrate, a first bonding layer and a dissociable bonding layer which are stacked in sequence; the second structure unit layer comprises a plurality of through holes; the third structural unit layer comprises a second substrate and a second bonding layer which are stacked in sequence, and the first structural unit layer, the through holes and the third structural unit layer form a plurality of spaces; the size of the dissociable bonding layer in the width direction of the first structural unit layer is smaller than that of the first bonding layer in the width direction of the first structural unit layer, so that the two tail ends of the first bonding layer in the width direction of the first structural unit layer are adhered to the second structural unit layer. According to the technical scheme of the utility model, the dissociable bonding layer is arranged to bond and fix the chip, so that the chip, especially the micro convex points of the chip, is prevented from being damaged in the transportation and treatment process, and the chip can be conveniently moved and taken from the bearing belt, thereby simplifying the surface mounting process of the chip.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging and electronic manufacturing technology. Specifically, this utility model provides a carrier tape for loading and accommodating chips. Background Technology

[0002] With the miniaturization of electronic devices becoming a significant trend in the global market, the development of modern technologies such as high-performance computing, 5G, and artificial intelligence has driven the continued growth in demand for semiconductor devices. Among these advanced integrated circuit (IC) packages, 3D ICs and 2.5D ICs are considered the optimal electronic architectures, with micro-bumps providing the best reliability in 3D IC designs. However, damage to micro-bumps can directly or indirectly affect the yield of the final IC assembly. Therefore, how to protect micro-bumps has become a focal point of discussion in the industry.

[0003] During packaging and transportation, contact between microbumps and carrier tape may pose a risk of damage. Additionally, the chip is prone to movement and collisions within the concave receptacle of the carrier tape, potentially causing damage to chip edges and other areas. Traditional protection methods include providing additional support features within the concave receptacle of the carrier tape to prevent microbumps from contacting the bottom of the carrier tape. However, this design is limited by chip size and microbump layout, and has limitations in practical operation. Furthermore, existing solutions propose using adhesives to secure the chip to the bottom of the concave receptacle to prevent chip movement and collisions. While this method offers some protection, adding adhesive to the bottom of the concave receptacle of the carrier tape is technically complex.

[0004] Therefore, it is necessary to develop a new carrier tape that can effectively reduce or even avoid damage to chips, especially their microbumps, during transportation and handling, and that has a simple manufacturing process. Utility Model Content

[0005] Based on the technical problems described above, the purpose of this utility model is to provide a carrier tape for loading chips. The carrier tape is provided with a removable adhesive layer and the chip is bonded and fixed by the removable adhesive layer. While avoiding the risk of damage to microbumps during transportation and handling, the chip can be easily removed from the carrier tape, thereby simplifying the chip mounting process.

[0006] The inventor of this utility model completed this utility model after in-depth and meticulous research.

[0007] Specifically, this utility model provides a carrier strip for loading chips, characterized in that the carrier strip comprises, in sequence:

[0008] The first structural unit layer includes a first substrate, a first adhesive layer and a removable adhesive layer stacked sequentially, wherein the removable adhesive layer is configured to adhere the chip to be loaded and to release the chip by reducing the adhesive force when heated or irradiated with ultraviolet light.

[0009] The second structural unit layer includes a plurality of through holes arranged along its length; and

[0010] The third structural unit layer includes a second substrate and a second adhesive layer stacked sequentially.

[0011] in:

[0012] The first structural unit layer, the via, and the third structural unit layer form multiple spaces for accommodating the chip to be loaded; and

[0013] The dimension of the detachable adhesive layer in the width direction of the first structural unit layer is smaller than the dimension of the first adhesive layer in the width direction of the first structural unit layer, such that the two ends of the first adhesive layer in the width direction of the first structural unit layer adhere to the second structural unit layer. Attached Figure Description

[0014] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate exemplary embodiments of the present invention and, together with the general description provided above and the detailed description provided below, serve to explain the features of the present invention.

[0015] Figure 1 This invention displays a plan view of a first structural unit layer, a second structural unit layer, and a third structural unit layer according to a specific embodiment of the present invention, as well as a top view of the load-bearing strip composed of the above three layers, viewed from the third structural unit layer side.

[0016] Figure 2 Display along Figure 1 The diagram shows a cross-sectional view of the carrier tape for loading the chip, represented by line L1; and

[0017] Figure 3 Display along Figure 1 A schematic cross-sectional view of the carrier strip for loading the chip shown in line L2;

[0018] Figure 4 Showing when Figure 1 The diagram shows a cross-sectional view of the carrier tape loaded with chips; and

[0019] Figure 5 A cross-sectional schematic diagram of a support belt according to another embodiment of the present invention is shown. Detailed Implementation

[0020] It should be understood that, without departing from the scope or spirit of this disclosure, those skilled in the art can conceive of various other embodiments and can modify them based on the teachings of this specification. Therefore, the following specific embodiments are not intended to be limiting.

[0021] Unless otherwise specified, all figures used in this specification and claims to indicate feature dimensions, quantities, and physical properties should be understood to be modified by the term "about" in all cases. Therefore, unless stated to the contrary, the numerical parameters listed in the foregoing specification and appended claims are approximations, and those skilled in the art can appropriately modify these approximations to obtain the desired characteristics using the teachings disclosed herein. The use of numerical ranges indicated by endpoints includes all numbers within that range and any range within that range; for example, 1 to 5 includes 1, 1.1, 1.3, 1.5, 2, 2.75, 3, 3.80, 4, and 5, etc.

[0022] As mentioned earlier, while microbumps offer good reliability in advanced IC packaging (such as 3D ICs and 2.5D ICs), they are prone to damage during chip transport and assembly (T&R) due to contact with the carrier tape. This directly or indirectly affects the final IC assembly yield. According to the technical solution of this invention, a removable adhesive layer is provided in the middle portion of the first structural unit layer of the carrier tape used for loading the chip. This removable adhesive layer has sufficient adhesive strength to adhere and adsorb the chip onto the first structural unit layer, preventing damage to its microstructure due to movement or shaking within the receiving portion, thereby reducing the risk of damage. Furthermore, the carrier tape for loading the chip according to this invention allows for convenient removal of the chip from the carrier tape, thus simplifying the chip mounting process.

[0023] Specifically, this utility model provides a carrier strip for loading chips, the carrier strip comprising, in sequence:

[0024] The first structural unit layer includes a first substrate, a first adhesive layer and a removable adhesive layer stacked sequentially, wherein the removable adhesive layer is configured to adhere the chip to be loaded and to release the chip by reducing the adhesive force when heated or irradiated with ultraviolet light.

[0025] The second structural unit layer includes a plurality of through holes arranged along its length; and

[0026] The third structural unit layer includes a second substrate and a second adhesive layer stacked sequentially.

[0027] in:

[0028] The removable adhesive layer, the vias, and the third structural unit layer form multiple spaces for accommodating the chip to be loaded; and

[0029] The dimension of the detachable adhesive layer in the width direction of the first structural unit layer is smaller than the dimension of the first adhesive layer in the width direction of the first structural unit layer, such that the two ends of the first adhesive layer in the width direction of the first structural unit layer adhere to the second structural unit layer.

[0030] Figure 1 The diagram shows a plan view of the third structural unit layer 2, the second structural unit layer 3, and the first structural unit layer 4 according to a specific embodiment of the present invention, as well as a top view of the load-bearing belt 1 composed of the above three components, viewed from the third structural unit layer 2 side. Figure 2 Showing along Figure 1 The diagram shows a cross-sectional view of the carrier strip 1 used to load the chip, with line L1 shown. Figure 3 Showing along Figure 1 The diagram shows a cross-sectional view of the carrier strip 1 used to load the chip, which is part of line L2.

[0031] Specifically, the carrier strip 1 sequentially includes: a first structural unit layer 4, comprising a first substrate 5, a first adhesive layer 6, and a removable adhesive layer 7 stacked sequentially, wherein the removable adhesive layer 7 is configured to adhere the chip to be loaded and to release the chip by reducing adhesive force when heated or irradiated with ultraviolet light; a second structural unit layer 3, comprising a plurality of through holes 8 arranged along its length direction; and a third structural unit layer 2, comprising a second substrate 2-1 and a second adhesive layer 2-2 stacked sequentially, wherein: the first structural unit layer 4, the through holes 8, and the third structural unit layer 2 form a plurality of spaces for accommodating the chip to be loaded; and the dimension of the removable adhesive layer 7 in the width direction a of the first structural unit layer 4 is smaller than the dimension of the first adhesive layer 6 in the width direction a of the first structural unit layer 4, such that the two ends A and B of the first adhesive layer 6 in the width direction a of the first structural unit layer 4 adhere to the second structural unit layer 3. Optionally, the plurality of through holes 8 are equidistantly arranged in the middle of the carrier strip 1 along the length direction b of the carrier strip 1. Optionally, the carrier belt 1 further includes a plurality of positioning holes 9, which are equidistantly arranged along the length direction b of the carrier belt 1 at the edge portion of the carrier belt 1.

[0032] Figure 4 Showing when Figure 1 The diagram shows a cross-sectional view of the carrier belt 1 with the chip 10 loaded on it. Figure 4As shown, the chip 10 with microbumps is attached to the removable adhesive layer 7, which keeps it fixed during transportation and handling, reducing the risk of damage to the microbumps. Of course, it is understood that the chip 10 can also be a chip without microbumps. Attaching the chip 10 to the removable adhesive layer 7 reduces the probability of the chip moving and colliding within the via 8, thereby protecting the chip's edges and other shapes from damage.

[0033] As above Figure 1-4 (in particular, Figure 3 and 4 As shown in the diagram, in the width direction of the bearing strip 1, the width of the detachable adhesive layer 7 is greater than the width of the through hole 8. However, the technical solution of this utility model is not limited to this. The width of the detachable adhesive layer 7 can also be equal to or less than the width of the through hole 8 as needed, as long as the projection of the detachable adhesive layer 7 on the third structural unit layer 2 at least partially coincides with the projection of the through hole 8 on the third structural unit layer 2.

[0034] According to certain preferred embodiments of the present invention, the detachable adhesive layer is located in the middle part of the first adhesive layer of the first structural unit layer, facing the second structural unit layer. This design allows the detachable adhesive layer to directly contact the chip in the receiving space formed by the through hole, providing the necessary adhesion force.

[0035] According to the technical solution of this utility model, the main function of the removable adhesive layer is to temporarily fix the chip, keeping it fixed during transportation and handling, thereby protecting the microbumps from damage. When needed, the stickiness of the removable adhesive layer can be significantly reduced or eliminated through specific heat treatment or ultraviolet irradiation, allowing the chip to be easily separated from the carrier tape, facilitating subsequent mounting processes.

[0036] Preferably, the dissociable adhesive layer is a dissociable pressure-sensitive adhesive layer.

[0037] Alternatively, the removable adhesive layer sequentially comprises a backing layer, a primer layer, and a removable pressure-sensitive adhesive layer. The backing layer is adhered to the first adhesive layer, while the removable pressure-sensitive adhesive layer faces the interior of the space formed by the removable adhesive layer, the through-hole, and the third structural unit layer of the carrier strip.

[0038] The thickness of the dissociable pressure-sensitive adhesive layer ranges from 10 to 100 μm, preferably 20 to 40 μm, which provides sufficient adhesion while ensuring reliability during the debonding process. Furthermore, before heating or UV irradiation, the dissociable pressure-sensitive adhesive layer exhibits an initial tack (adhesive force) of 1.0 to 12 N / cm, preferably 3.0 to 8.0 N / cm, to the chip at room temperature, ensuring stable adhesion of the chip to the first structural unit layer. Moreover, when heated to 80-190°C, preferably 100-125°C, the adhesive force of the dissociable pressure-sensitive adhesive layer to the chip decreases to less than or equal to 0.20 N / cm, preferably less than or equal to 0.10 N / cm, and more preferably to below 0.03-0.05 N / cm. Furthermore, when the dissociable pressure-sensitive adhesive layer is subjected to ultraviolet light with a power of 400 millijoules or higher, its adhesion to the chip decreases to less than or equal to 0.20 N / cm, preferably less than or equal to 0.10 N / cm, and more preferably to less than 0.03-0.05 N / cm. This adhesion strength was measured at 23 degrees Celsius, a 180-degree peel angle, and a peel speed of 300 mm / min.

[0039] The dissociable pressure-sensitive adhesive layer that can be used in this invention can be composed of dissociable pressure-sensitive adhesives known in the art. These dissociable pressure-sensitive adhesives are commercially available or can be synthesized by known methods. Specific examples of dissociable pressure-sensitive adhesives that can be used in this invention include "Revalpha" and "Revaclean" dissociable tapes manufactured by Nitto Denko Corporation. Alternatively, the dissociable pressure-sensitive adhesive that can be used in this invention can also be synthesized according to the method described in Japanese Patent Application Publication No. 56-61468 (JPS5661468 A).

[0040] According to certain preferred technical solutions of this utility model, the first structural unit layer and the second structural unit layer are laminated together to form a carrier tape, and the third structural unit layer is a cover tape. Figure 1-4The diagram shows a configuration where a first structural unit layer 4 (comprising a first substrate 5, a first adhesive layer 6, and a removable adhesive layer 7 stacked sequentially) and a second structural unit layer 3 are laminated together to form a carrier tape, and a third structural unit layer 2 serves as a cover tape. During production, the carrier tape and the cover tape can be manufactured, packaged, and sold separately. Subsequently, at the chip manufacturer, they are bonded together after the chip is loaded. More preferably, the third structural unit layer further includes a low-tack backing layer disposed on the surface of the second substrate facing away from the second adhesive layer. The low-tack backing layer facilitates the winding process of the third structural unit layer as a cover tape. More preferably, the second adhesive layer is a pressure-sensitive adhesive layer or a heat-activated adhesive layer, configured to bond the second structural unit layer and the second substrate together.

[0041] According to certain preferred technical solutions of this utility model, the second structural unit layer and the third structural unit layer are laminated together to form a carrier tape, and the first structural unit layer is a cover tape. Figure 5 A cross-sectional schematic diagram of a support belt according to another embodiment of the present invention is shown. The support belt of this other embodiment is... Figure 1-4 The load-bearing belt shown has a similar construction. Specifically, Figure 5 The corresponding bearing belt of the other embodiment is shown. Figure 3 A cross-sectional schematic diagram, in which... Figure 3 The difference lies in that: the second structural unit layer 3 and the third structural unit layer 2 are laminated together to form a carrier tape, and the first structural unit layer 4 (including a first substrate 5, a first adhesive layer 6, and a removable adhesive layer 7 stacked sequentially) is a cover tape; and the width of the removable adhesive layer 7 is smaller than the width of the through-hole 8. During the production process, the carrier tape and the cover tape can be manufactured, packaged, and sold separately. Subsequently, at the chip manufacturer, after the chip is loaded, the two are bonded together. Through the different cover tape-carrier tape arrangements described above, carrier tape products can be produced in different forms, providing flexibility in the manufacturing and use of the carrier tape. More preferably, the first structural unit layer further includes a low-tack backing layer, which is disposed on the surface of the first substrate facing away from the first adhesive layer.

[0042] According to certain preferred embodiments of the present invention, the first substrate is a transparent substrate, and the first adhesive layer is a transparent adhesive layer. With the above design, when removing the chip from the carrier tape, ultraviolet light can be applied from one side of the first structural unit layer of the carrier tape, causing the dissociable pressure-sensitive adhesive layer to gradually lose its adhesiveness, thereby facilitating the removal of the chip from the receiving space formed by the through-hole.

[0043] According to certain preferred embodiments of the present invention, the second structural unit layer includes a substrate layer, on which a plurality of spaced-apart through holes are punched.

[0044] According to certain preferred embodiments of the present invention, the second structural unit layer has a stable structure to provide support for the bearing belt. Preferably, the second structural unit layer is a plastic perforated layer, a cardboard perforated layer, or a foamed plastic perforated layer.

[0045] There are no particular limitations on the specific shape of the through-hole that can be used in this invention; it can be selected according to actual needs, especially according to the size and shape of the chip actually accommodated. Preferably, the through-hole is a circular through-hole, a square through-hole, a rectangular through-hole, or an elliptical through-hole.

[0046] According to the technical solution of this utility model, the first substrate and the second substrate can be made of materials known in the art. Preferably, the first substrate and the second substrate can be made of polyethylene terephthalate (PET), polyester copolymers, or polyolefins (such as polyethylene and polyethylene copolymers, polypropylene and polyolefin copolymers). These materials are commercially available.

[0047] According to the technical solution of this utility model, the first adhesive layer and the second adhesive layer can be made of materials known in the art. Preferably, the first adhesive layer and the second adhesive layer can be made of polystyrene-based resin, polyethylene-based resin, or acrylic-based resin. These materials are commercially available.

[0048] According to the technical solution of this utility model, the third structural unit layer can be made of materials known in the art. Preferably, the second structural unit layer is a plastic perforated layer, a cardboard perforated layer, or a foamed plastic perforated layer. The third structural unit layer includes a second substrate and a second adhesive layer stacked sequentially.

[0049] The carrier belt according to this invention can be effectively used for chip storage and transportation, avoiding the risk of damage to the microbumps on the chip during transportation and handling.

[0050] Specifically, in chip packaging operations, following the conventional carrier tape packaging process, the chip (such as an HBM chip) is placed in the receiving space formed by the through-holes in the carrier tape. At this time, the removable adhesive layer attached to the first structural unit layer will use its adhesive force to adhere and adsorb the chip onto the first structural unit layer, effectively preventing damage caused by shaking, collision, etc. during transportation.

[0051] The second structural unit layer provides excellent protection for the chip during transportation. Furthermore, the detachable pressure-sensitive adhesive layer of the detachable bonding layer has sufficient adhesion to ensure the chip remains stably attached to the first structural unit layer even during vibrations and bumps, preventing movement within the via space and protecting against damage to tiny solder balls or the device itself due to impact.

[0052] When performing a placement operation, the carrier tape is placed in the appropriate equipment, and a specific heating temperature (80-190°C, preferably 100-125°C, for 3-5 minutes) or UV irradiation is applied to the removable adhesive layer of the carrier tape. (The removable pressure-sensitive adhesive layer of the carrier tape can be accurately and efficiently irradiated by a conventional UV light-emitting diode (LED) system, such as an LED head containing a power / control unit, an LED driver module, and a focusing lens, which can be mounted on an SMT machine).

[0053] After the aforementioned heating or UV irradiation, the adhesiveness of the removable pressure-sensitive adhesive layer rapidly decreases to near zero. At this point, the chip no longer adheres to the removable adhesive layer on the first structural unit layer but returns to the bottom of the receiving space formed by the through-holes in the carrier tape. Subsequently, the nozzle of the device can easily pick up the chip from the receiving space for subsequent placement operations, accurately mounting the chip onto the target location such as the circuit board. Throughout the process, the chip is effectively protected during transportation and can smoothly detach from the carrier tape during placement, ensuring chip integrity and the high efficiency of the placement operation.

[0054] The following list of embodiments further illustrates various exemplary embodiments of the present invention, which should not be construed as unduly limiting the present invention:

[0055] Specific implementation scheme 1 is a carrier strip for loading chips, characterized in that the carrier strip comprises, in sequence:

[0056] The first structural unit layer includes a first substrate, a first adhesive layer and a removable adhesive layer stacked sequentially, wherein the removable adhesive layer is configured to adhere the chip to be loaded and to release the chip by reducing the adhesive force when heated or irradiated with ultraviolet light.

[0057] The second structural unit layer includes a plurality of through holes arranged along its length; and

[0058] The third structural unit layer includes a second substrate and a second adhesive layer stacked sequentially.

[0059] in:

[0060] The removable adhesive layer, the vias, and the third structural unit layer form multiple spaces for accommodating the chip to be loaded; and

[0061] The dimension of the detachable adhesive layer in the width direction of the first structural unit layer is smaller than the dimension of the first adhesive layer in the width direction of the first structural unit layer, such that the two ends of the first adhesive layer in the width direction of the first structural unit layer adhere to the second structural unit layer.

[0062] Specific implementation scheme 2 is a carrier strip for accommodating chips as described in specific implementation scheme 1, characterized in that the removable adhesive layer is a removable pressure-sensitive adhesive layer.

[0063] Specific implementation scheme 3 is a carrier strip for accommodating chips as described in specific implementation scheme 1, characterized in that the removable adhesive layer sequentially includes a backing layer, a primer layer and a removable pressure-sensitive adhesive layer.

[0064] Specific implementation scheme 4 is a carrier strip for accommodating a chip according to specific implementation scheme 2 or 3, characterized in that the adhesive force of the removable pressure-sensitive adhesive layer to the chip at room temperature is in the range of 1.0 to 12 Newtons / cm.

[0065] Specific implementation scheme 5 is a carrier tape for accommodating a chip according to specific implementation scheme 2 or 3, characterized in that the adhesive force of the removable pressure-sensitive adhesive layer to the chip at room temperature is in the range of 3.0 to 8.0 Newtons / cm.

[0066] Specific implementation scheme 6 is a carrier strip for accommodating a chip according to specific implementation scheme 2 or 3, characterized in that the adhesive force of the dissociable pressure-sensitive adhesive layer to the chip is reduced to less than or equal to 0.05 Newtons / cm when heated to 80-190°C.

[0067] Specific implementation scheme 7 is a carrier strip for accommodating a chip according to specific implementation scheme 2 or 3, characterized in that the adhesive force of the dissociable pressure-sensitive adhesive layer to the chip is reduced to less than or equal to 0.05 N / cm when subjected to ultraviolet light of 400 mJ or more.

[0068] Specific implementation scheme 8 is a carrier strip for accommodating a chip according to specific implementation scheme 2 or 3, characterized in that the thickness of the dissociable pressure-sensitive adhesive layer is in the range of 10 μm to 100 μm.

[0069] Specific implementation scheme 9 is a carrier tape for accommodating chips according to specific implementation scheme 1, characterized in that the first structural unit layer and the second structural unit layer are laminated together to form a carrier tape, and the third structural unit layer is a cover tape.

[0070] Specific implementation scheme 10 is a carrier strip for accommodating chips according to specific implementation scheme 9, characterized in that the third structural unit layer further includes a low-adhesion backing layer, which is disposed on the surface of the second substrate facing away from the second adhesive layer; the second adhesive layer is a pressure-sensitive adhesive layer or a heat-activated adhesive layer, which is configured to bond the second structural unit layer and the second substrate together.

[0071] Specific implementation scheme 11 is a carrier tape for accommodating chips according to specific implementation scheme 1, characterized in that the second structural unit layer and the third structural unit layer are laminated together to form a carrier tape, and the first structural unit layer is a cover tape.

[0072] Specific implementation scheme 12 is a carrier strip for accommodating chips according to specific implementation scheme 11, characterized in that the first structural unit layer further includes a low-adhesion back layer, which is disposed on the surface of the first substrate facing away from the first adhesive layer.

[0073] Specific implementation scheme 13 is a carrier strip for accommodating chips according to specific implementation scheme 1, characterized in that the first substrate is a transparent substrate and the first adhesive layer is a transparent adhesive layer.

[0074] Specific implementation scheme 14 is a carrier strip for accommodating chips according to specific implementation scheme 1, characterized in that the second structural unit layer includes a substrate layer, on which a plurality of through holes spaced apart from each other are punched.

[0075] Compared with the prior art in this field, the advantages of this utility model are as follows:

[0076] 1. Microbump protection: This invention provides a removable adhesive layer in the first structural unit layer to fix the chip, effectively avoiding the risk of damage to the microbumps on the chip during transportation and handling.

[0077] 2. Ease of Operation: By incorporating a removable adhesive layer for chip fixation within the first structural unit layer during a separate carrier tape or cover tape manufacturing process, the complex operation of applying adhesive to the bottom of the concave receiving portion, as required in existing technologies, is avoided, thus improving process simplicity. Furthermore, utilizing the removable adhesive layer's removable bonding properties, the chip can be released simply by heating or ultraviolet irradiation, simplifying the traditionally complex separation process and further enhancing operational ease of operation.

[0078] 3. Enhanced Protection: The adhesive layer exhibits an adhesive strength ranging from 1.0 to 12 N / cm at room temperature, providing sufficient strength to ensure chip stability during transport. Furthermore, the adhesive strength of the dissociable pressure-sensitive adhesive layer decreases to less than or equal to 0.05 N / cm when heated to 80-190°C, or to less than or equal to 0.05 N / cm when subjected to ultraviolet light exceeding 400 mJ. This allows for rapid loss of tack when needed, facilitating chip handling. This controllable adhesion mechanism enhances chip protection.

[0079] 4. Improved production efficiency: Since the chip can quickly lose its adhesiveness when needed, it can be easily separated from the carrier tape, which helps to improve the efficiency of the mounting process and reduce production time and costs.

[0080] 5. Flexible structural design: The detachable adhesive layer can be designed into different shapes and areas as needed. For example, in the width direction of the bearing strip, the width of the detachable adhesive layer can be greater than, equal to or less than the width of the through hole, which provides flexibility in structural design.

[0081] Although specific embodiments have been shown and described in this invention, those skilled in the art will understand that various alternative and / or equivalent embodiments can be used instead of the shown and described specific embodiments without departing from the scope of this invention. This application is intended to include any improvements or modifications to the specific embodiments discussed in this invention. Therefore, this invention is limited only to the claims and their equivalents.

[0082] Those skilled in the art will understand that various modifications and alterations can be made without departing from the scope of this utility model. Such modifications and alterations are intended to fall within the scope of this utility model as defined in the appended claims.

Claims

1. A carrier tape for loading chips, characterized in that, The carrier belt comprises, in sequence: The first structural unit layer includes a first substrate, a first adhesive layer and a removable adhesive layer stacked sequentially, wherein the removable adhesive layer is configured to adhere the chip to be loaded and to release the chip by reducing the adhesive force when heated or irradiated with ultraviolet light. The second structural unit layer includes a plurality of through holes arranged along its length; and The third structural unit layer includes a second substrate and a second adhesive layer stacked sequentially. in: The first structural unit layer, the via, and the third structural unit layer form multiple spaces for accommodating the chip to be loaded; and The dimension of the detachable adhesive layer in the width direction of the first structural unit layer is smaller than the dimension of the first adhesive layer in the width direction of the first structural unit layer, such that the two ends of the first adhesive layer in the width direction of the first structural unit layer adhere to the second structural unit layer.

2. The carrier tape for loading chips according to claim 1, characterized in that, The dissociable adhesive layer is a dissociable pressure-sensitive adhesive layer.

3. The carrier tape for loading chips according to claim 1, characterized in that, The removable adhesive layer comprises, in sequence, a backing layer, a primer layer, and a removable pressure-sensitive adhesive layer.

4. The carrier tape for loading chips according to claim 2 or 3, characterized in that, The adhesive force of the dissociable pressure-sensitive adhesive layer at room temperature is in the range of 1.0 to 12 N / cm.

5. The carrier tape for loading chips according to claim 2 or 3, characterized in that, The adhesive force of the dissociable pressure-sensitive adhesive layer at room temperature is in the range of 3.0 to 8.0 N / cm.

6. The carrier tape for loading chips according to claim 2 or 3, characterized in that, When the dissociable pressure-sensitive adhesive layer is heated to 80-190°C, the adhesive strength decreases to less than or equal to 0.05 N / cm.

7. The carrier tape for loading chips according to claim 2 or 3, characterized in that, When the dissociable pressure-sensitive adhesive layer is subjected to ultraviolet light of 400 millijoules or higher, the adhesive strength decreases to less than or equal to 0.05 Newtons / cm.

8. The carrier tape for loading chips according to claim 2 or 3, characterized in that, The thickness of the dissociable pressure-sensitive adhesive layer is in the range of 10 μm to 100 μm.

9. The carrier tape for loading chips according to claim 1, characterized in that, The first structural unit layer and the second structural unit layer are laminated together to form a carrier tape, and the third structural unit layer is a cover tape.

10. The carrier tape for loading chips according to claim 9, characterized in that, The third structural unit layer further includes a low-tack backing layer, which is disposed on the surface of the second substrate facing away from the second adhesive layer; the second adhesive layer is a pressure-sensitive adhesive layer or a heat-activated adhesive layer, which is configured to bond the second structural unit layer and the second substrate together.

11. The carrier tape for loading chips according to claim 1, characterized in that, The second structural unit layer and the third structural unit layer are laminated together to form a carrier tape, and the first structural unit layer is a cover tape.

12. The carrier tape for loading chips according to claim 11, characterized in that, The first structural unit layer further includes a low-adhesion backing layer, which is disposed on the surface of the first substrate facing away from the first adhesive layer.

13. The carrier tape for loading chips according to claim 1, characterized in that, The first substrate is a transparent substrate, and the first adhesive layer is a transparent adhesive layer.

14. The carrier tape for loading chips according to claim 1, characterized in that, The second structural unit layer includes a substrate layer, on which a plurality of spaced-apart through holes are punched.

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