Parallel current adding system

Abstract

The utility model discloses a parallel current adding system, belongs to the technical field of electronic equipment for measurement and test, and solves the problem of how to design a parallel current adding system which is simple in hardware circuit and high in control precision. The utility model relates to a parallel-connection current adding system, which comprises a plurality of single-machine current sampling circuits and a parallel-connection current adding circuit, the single-machine current sampling circuit comprises a first differential amplification circuit, a first proportional adjustment circuit, a first unit phase inverter circuit and a first digital potentiometer; the parallel current summing circuit comprises an instrument amplifier circuit, a second proportional adjusting circuit, a second unit phase inverting circuit, a second digital potentiometer and a plurality of proportional input end resistors; the digital potentiometers are applied to the parallel operation circuit, the amplification factor is adjusted by assigning the resistance values of the potentiometers according to the set parallel operation number, the mode that the amplification factor is adjusted by switching the resistance value of a single proportional resistor of a traditional resistance proportional circuit is replaced, a hardware circuit is simple, and amplification factor control is accurate.

Description

Technical Field

[0001] This utility model belongs to the technical field of electronic equipment for measurement and testing, and relates to a parallel current application system. Background Technology

[0002] In AC / DC power supply and load systems, high-precision resistors and operational amplifiers are generally used to form a current sampling circuit. The device reads the current code value through an ADC chip, and the chip calculates the actual current using a calibration coefficient. Most parallel power supply and load paralleling methods are divided into two types: analog paralleling and digital paralleling.

[0003] Analog parallel operation primarily uses differential amplifiers to sample the current of each device, converting the current signal into a voltage signal, which is then fed into the host current summing circuit. The host ADC then acquires the total current signal and calculates the total parallel current. This method requires adjusting the proportional resistor of the summing operational amplifier when multiple devices are operating in parallel, affecting the sampling accuracy. Furthermore, changing the number of devices in parallel necessitates switching the summing ratio, resulting in complex circuitry, cumbersome control, and difficult calibration. In a digital parallel system, each unit acquires its current via an ADC, and then the host performs a summation calculation using digital communication methods such as CAN or SPI before sending the results to each slave device. This method solves the interference problem during transmission, but ADC acquisition and digital communication require time, introducing latency and preventing real-time acquisition.

[0004] The current technical challenge lies in the fact that, in the case of multiple machines connected in parallel, the proportional gain in the parallel summing circuit needs to be switched by analog switches or other switching devices. Each additional device requires adjustment of the differential amplification factor, which leads to complex hardware circuitry, the need for more control interfaces, and difficulty in calibration. Utility Model Content

[0005] The technical solution of this utility model is used to solve the problem of how to design a parallel current summing system with simple hardware circuitry and high control precision.

[0006] This utility model solves the above-mentioned technical problems through the following technical solution:

[0007] This utility model provides a parallel current summing system, comprising: multiple single-unit current sampling circuits and a parallel current summing circuit; the single-unit current sampling circuit includes: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverting circuit, and a first digital potentiometer; the parallel current summing circuit includes: an instrumentation amplifier circuit, a second proportional adjustment circuit, a second unit inverting circuit, a second digital potentiometer, and multiple proportional input resistors; the input terminal of the first differential amplifier circuit samples the single-unit current flowing through the sampling resistors, the output terminal of the first differential amplifier circuit is connected to the B terminal of the first digital potentiometer, the W terminal of the first digital potentiometer is connected to the inverting input terminal of the first proportional adjustment circuit, and the A terminal of the first digital potentiometer is connected to the output terminal of the first proportional adjustment circuit; the output terminal of the first proportional adjustment circuit is connected to the input terminal of the first unit inverting circuit, wherein the output terminal of the first proportional adjustment circuit outputs a PARA+ signal, and the output terminal of the first unit inverting circuit outputs a PARA- signal; multiple single-unit current sampling circuits are used. The PARA+ signal terminals of the circuit are all connected to the PARA+ signal terminals of the parallel current summing circuit, and the PARA- signal terminals of the multiple single-unit current sampling circuits are all connected to the PARA- signal terminals of the parallel current summing circuit. The number of proportional input resistors is twice that of the single-unit current sampling circuit. The multiple proportional input resistors are divided into two groups. The first group of proportional input resistors are all connected in parallel, and one of the parallel common terminals serves as the PARA+ signal terminal of the parallel current summing circuit. The other parallel common terminal is connected to the first input terminal of the instrumentation amplifier circuit. The second group of proportional input resistors are also all connected in parallel, and one of the parallel common terminals serves as the PARA- signal terminal of the parallel current summing circuit. The other parallel common terminal is connected to the second input terminal of the instrumentation amplifier circuit. The output terminal of the instrumentation amplifier circuit is connected to the A terminal of the second digital potentiometer, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the second proportional adjustment circuit, and the B terminal of the second digital potentiometer is connected to the input terminal of the second unit inverting circuit.

[0008] Further, the first differential amplifier circuit includes: sampling resistors R3, R5, R6, R7, R8, and R9, and a first operational amplifier U1; one end of resistor R5 is connected to the inverting input terminal of the first operational amplifier U1, one end of resistor R6 is connected to the non-inverting input terminal of the first operational amplifier U1, and the other ends of resistors R5 and R6 are respectively connected to the two ends of sampling resistor R3; one end of resistor R7 is connected to the inverting input terminal of the first operational amplifier U1, and the other end of resistor R7 is connected to the output terminal of the first operational amplifier U1; one end of resistor R8 is connected to the non-inverting input terminal of the first operational amplifier U1, and the other end of resistor R8 is grounded; one end of resistor R9 is connected to the output terminal of the first operational amplifier U1, and the other end of resistor R9 is connected to the B terminal of the first digital potentiometer; the output signal of the first operational amplifier U1 serves as the single-machine ADC1 signal.

[0009] Furthermore, the first proportional adjustment circuit includes: a resistor R10 and a second operational amplifier U2; the W terminal of the first digital potentiometer is connected to the inverting input terminal of the second operational amplifier U2, the non-inverting input terminal of the second operational amplifier U2 is grounded, the A terminal of the first digital potentiometer is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the output terminal of the second operational amplifier U2; the output signal of the second operational amplifier U2 serves as the PARA+ signal.

[0010] Furthermore, the first unit inverting circuit includes: resistor R14, resistor R15, and a third operational amplifier U3; one end of resistor R14 is connected to the output terminal of the second operational amplifier U2, and the other end of resistor R14 is connected to the inverting input terminal of the third operational amplifier U3; one end of resistor R15 is connected to the inverting input terminal of the third operational amplifier U3, and the other end of resistor R15 is connected to the output terminal of the third operational amplifier U3; the non-inverting input terminal of the third operational amplifier U3 is grounded; the output signal of the third operational amplifier U3 serves as the PARA- signal.

[0011] Further, the instrumentation amplifier circuit includes: resistors R16, R17, R18, R19, R20, and R21; a fourth operational amplifier U4; a fifth operational amplifier U5; and a sixth operational amplifier U6. The common terminal of the parallel connection of the first set of proportional input resistors is connected to the inverting input of the fourth operational amplifier U4, and the non-inverting input of the fourth operational amplifier U4 is grounded. One end of resistor R16 is connected to the inverting input of the fourth operational amplifier U4, and the other end of resistor R16 is connected to the output of the fourth operational amplifier U4. The common terminal of the parallel connection of the second set of proportional input resistors is connected to the inverting input of the fifth operational amplifier U5, and the non-inverting input of the fifth operational amplifier U6 is grounded. One end of resistor R17 is connected to the inverting input of the fifth operational amplifier U5, and the other end of resistor R17 is connected to the output of the fifth operational amplifier U5. One end of resistor R18 is connected to the output of the fourth operational amplifier U4, and the other end of resistor R18 is connected to the inverting input of the sixth operational amplifier U6. One end of resistor R19 is connected to the output of the fifth operational amplifier U5, and the other end of resistor R19 is connected to the non-inverting input of the sixth operational amplifier U6. One end of resistor R20 is connected to the inverting input of the sixth operational amplifier U6, and the other end of resistor R20 is connected to the output of the sixth operational amplifier U6. One end of resistor R21 is connected to the non-inverting input of the sixth operational amplifier U6, and the other end of resistor R21 is grounded.

[0012] Furthermore, the second proportional adjustment circuit includes: a seventh operational amplifier U7; the A terminal of the second digital potentiometer is connected to the output terminal of the sixth operational amplifier U6, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the seventh operational amplifier U7, the B terminal of the second digital potentiometer is connected to the output terminal of the seventh operational amplifier U7, and the non-inverting input terminal of the seventh operational amplifier U7 is grounded.

[0013] Furthermore, the second unit inverting circuit includes: resistor R24, resistor R25, and an eighth operational amplifier U8; one end of resistor R24 ​​is connected to the output terminal of the seventh operational amplifier U7, and the other end of resistor R24 ​​is connected to the inverting input terminal of the eighth operational amplifier U8; one end of resistor R25 is connected to the inverting input terminal of the eighth operational amplifier U8, and the other end of resistor R25 is connected to the output terminal of the eighth operational amplifier U8; the non-inverting input terminal of the eighth operational amplifier U8 is grounded, and the output terminal of the eighth operational amplifier U8 serves as the ADC2 signal output terminal.

[0014] Furthermore, the model number of the digital potentiometer is AD5292.

[0015] The advantages of this utility model are:

[0016] This invention applies a digital potentiometer to a parallel circuit. By setting the number of parallel circuits, the resistance value of the potentiometer is assigned to adjust the amplification factor, replacing the traditional resistor proportional circuit that uses a single proportional resistor to adjust the amplification factor. This results in a simple hardware circuit; by controlling the digital potentiometer, precise control of the parallel amplification factor can be achieved, and it has the advantages of high current accuracy. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the single-machine current sampling circuit of the parallel current summing system according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the parallel current summing circuit of the parallel current summing system according to an embodiment of the present invention;

[0019] Figure 3 This is a pinout diagram of the digital potentiometer used in the parallel current summing system of this utility model embodiment;

[0020] Figure 4 This is a diagram showing the internal circuit structure of the digital potentiometer used in the parallel current summing system of this utility model embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below in conjunction with the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0022] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments:

[0023] Example 1

[0024] The parallel current summing system of this utility model embodiment includes: multiple single-machine current sampling circuits and parallel current summing circuits.

[0025] like Figure 1As shown, the single-machine current sampling circuit includes: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverting circuit, and a first digital potentiometer; the first differential amplifier circuit includes: sampling resistors R3, R5, R6, R7, R8, and R9, and a first operational amplifier U1; the first proportional adjustment circuit includes: resistor R10 and a second operational amplifier U2; the first unit inverting circuit includes: resistor R14 and R15, and a third operational amplifier U3.

[0026] One end of resistor R5 is connected to the inverting input of the first operational amplifier U1; one end of resistor R6 is connected to the non-inverting input of the first operational amplifier U1; the other ends of resistors R5 and R6 are respectively connected to the two ends of sampling resistor R3; one end of resistor R7 is connected to the inverting input of the first operational amplifier U1, and the other end of resistor R7 is connected to the output of the first operational amplifier U1; one end of resistor R8 is connected to the non-inverting input of the first operational amplifier U1, and the other end of resistor R8 is grounded; one end of resistor R9 is connected to the output of the first operational amplifier U1, and the other end of resistor R9 is connected to the B terminal of the first digital potentiometer; the W terminal of the first digital potentiometer is connected to the inverting input of the second operational amplifier U2; the second operational amplifier U2... The non-inverting input of the second operational amplifier U1 is grounded. Terminal A of the first digital potentiometer is connected to one end of resistor R10, and the other end of resistor R10 is connected to the output of the second operational amplifier U2. One end of resistor R14 is connected to the output of the second operational amplifier U2, and the other end of resistor R14 is connected to the inverting input of the third operational amplifier U3. One end of resistor R15 is connected to the inverting input of the third operational amplifier U3, and the other end of resistor R15 is connected to the output of the third operational amplifier U3. The non-inverting input of the third operational amplifier U3 is grounded. The output signal of the first operational amplifier U1 is used as the single-machine ADC1 signal, the output signal of the second operational amplifier U2 is used as the PARA+ signal, and the output signal of the third operational amplifier U3 is used as the PARA- signal.

[0027] like Figure 2As shown, taking the summation of two currents as an example, the composition of the parallel current summing circuit is described in detail. The parallel current summing circuit includes: an instrumentation amplifier circuit, a second proportional adjustment circuit, a second unit inverting circuit, and a second digital potentiometer. The instrumentation amplifier circuit includes: resistors R16, R17, R18, R19, R20, and R21; a fourth operational amplifier U4; a fifth operational amplifier U5; and a sixth operational amplifier U6. The second proportional adjustment circuit includes a seventh operational amplifier U7. The second unit inverting circuit includes: resistors R24 and R25; and an eighth operational amplifier U8. When the two currents are summed, the proportional input resistors of the instrumentation amplifier circuit consist of two pairs of parallel resistors, for a total of four resistors. Figure 2 As shown, the resistors are R26, R27, R28, and R29, respectively.

[0028] The parallel common terminal of resistors R26 and R28 is used to input the PARA+ signal, and the other parallel common terminal is connected to the inverting input of the fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is grounded. One end of resistor R16 is connected to the inverting input of the fourth operational amplifier U4, and the other end of resistor R16 is connected to the output of the fourth operational amplifier U4. Similarly, the parallel common terminal of resistors R27 and R29 is used to input the PARA- signal, and the other parallel common terminal is connected to the inverting input of the fifth operational amplifier U5. The non-inverting input of the fifth operational amplifier U5 is grounded. One end of resistor R17 is connected to the inverting input of the fifth operational amplifier U5, and the other end of resistor R17 is connected to the output of the fifth operational amplifier U5. One end of resistor R18 is connected to the output of the fourth operational amplifier U4, and the other end of resistor R18 is connected to the inverting input of the sixth operational amplifier U6. One end of resistor R19 is connected to the output of the fifth operational amplifier U5, and the other end of resistor R19 is connected to the output of the sixth operational amplifier U6. Operational amplifier U6 is connected to its non-inverting input. One end of resistor R20 is connected to the inverting input of operational amplifier U6, and the other end of resistor R20 is connected to the output of operational amplifier U6. One end of resistor R21 is connected to the non-inverting input of operational amplifier U6, and the other end of resistor R21 is grounded. The A terminal of the second digital potentiometer is connected to the output of operational amplifier U6. The W terminal of the second digital potentiometer is connected to the inverting input of operational amplifier U7, and the B terminal of the second digital potentiometer is connected to the output of operational amplifier U7. The non-inverting input of operational amplifier U7 is grounded. One end of resistor R24 ​​is connected to the output of operational amplifier U7, and the other end of resistor R24 ​​is connected to the inverting input of operational amplifier U8. One end of resistor R25 is connected to the inverting input of operational amplifier U8, and the other end of resistor R25 is connected to the output of operational amplifier U8. The non-inverting input of operational amplifier U8 is grounded. The output of operational amplifier U8 serves as the ADC2 signal output terminal.

[0029] like Figure 3 and Figure 4 The figures shown are the pinout diagram and internal circuit structure diagram of the digital potentiometer, which is model AD5292.

[0030] The working principle is as follows:

[0031] When set to stand-alone mode, the stand-alone current passes through the sampling resistor R3 and is converted into a stand-alone ADC1 signal through the first differential amplifier circuit (1). The ADC1 signal is directly connected to the current ADC sampling chip, the ammeter current is read, and the calibration coefficients k1 and b1 are calculated together with the ADC sampling code value and saved to the CPU. ADC code value = actual current Ir1*k1+b1.

[0032] The A, W, and B positions in the first proportional adjustment circuit are connected to the first digital potentiometer. The code value is transmitted via SPI, using a 1024-bit digital potentiometer, R. AB If the resistance is 20kΩ, then R AW1 With R BW1 The value can be set by sending a code value from 0 to 1023. The amplification factor of the first proportional adjustment circuit is:

[0033]

[0034] Among them, A V1 R is the amplification factor of the first proportional adjustment circuit. AW1 R is the resistance between terminals A and W of the first digital potentiometer. BW1 The resistance is between terminals B and W of the first digital potentiometer.

[0035] During calibration, adjust the first digital potentiometer code value of each individual current sampling circuit so that PARA+ and PARA- are equal to the target value;

[0036] At this point, connect PARA+ and PARA- of each individual current sampling circuit to the parallel current summing circuit, and adjust the second digital potentiometer of the parallel current summing circuit so that the voltage at point B of the parallel current summing circuit is equal to the value of PARA+ in the individual current sampling circuit; the amplification factor of the second proportional adjustment circuit of the parallel current summing circuit is:

[0037]

[0038] Among them, A V2 R is the amplification factor of the second proportional adjustment circuit. AW2 R is the resistance between terminals A and W of the second digital potentiometer. BW2 This is the resistance between terminals B and W of the second digital potentiometer.

[0039] Disconnect ADC1 from the standalone current sampling circuit to the ADC chip, and connect ADC2 from the parallel current summing circuit to the ADC chip. Calculate the k2 and b2 coefficients at this point. The ADC code value = actual current Ir2 * k2 + b2. The calibration is now complete. Assuming the standalone digital potentiometer is set to 512, then R... AW =R BW =10K, at this time the amplification factor of U2 inverting amplifier is -1, resulting in PARA+, which is then inverted to obtain PARA-. Here, two currents are re-loaded to obtain two sets of data, and the parallel calibration value is calculated according to the single-machine calibration coefficient calculation method.

[0040] The calibration employs a two-point calibration method. First, a positive DC current of 30A is applied, and the ammeter data is read and the corresponding ADC code value is recorded. Then, a negative DC current of 30A is applied, and the ammeter data is read again, recording the corresponding ADC code value. Two sets of data are used to calculate coefficients k1 and b1, obtaining the correspondence between the ADC sampled code value and the actual current: ADC code value = actual current Ir * k1 + b1. During calibration, the digital potentiometer values ​​are adjusted so that PARA+ and PARA- equal the target values. The target value is the theoretical calibration voltage. With a 30A current load, assuming the internal proportional gain after the sampling resistor is 0.1, a 3V output is required.

[0041] When set to parallel calibration mode, after each unit completes the calibration of two sets of coefficients, n units are connected in parallel. At this time, parallel configuration information is sent out, and the setting value of the second digital potentiometer is changed by the number of units in parallel to achieve the effect of summing the parallel current.

[0042] At this point, the fourth operational amplifier U4, the fifth operational amplifier U5, and the sixth operational amplifier U6 form a current summing circuit. A second digital potentiometer is set. When the number of parallel units is 1, the multiplier of the digital potentiometer is set to 10 times. Similarly, when multiple units are used in parallel, the number of parallel units is 2, 3, 4... and the multiplier of the second proportional adjustment circuit is 5 times, 10 / 3 times, 2.5 times, 2 times... to finally obtain the parallel current sampling signal.

[0043] By combining analog and digital parallel operation, configuration parameters are issued from the digital channel, and analog current signals are summed and calibrated and adjusted using digital potentiometers. This achieves advantages such as simple hardware circuitry and high current accuracy after calibration. By using digital potentiometers to replace traditional resistor-proportional circuits, in a single-machine configuration, after calculating the calibration coefficient according to the above calibration method, a high-precision current value can be obtained by changing the parallel digital potentiometers when multiple power supplies or loads are connected in parallel.

[0044] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A parallel current summing system, characterized in that, include: Multiple stand-alone current sampling circuits and parallel current summing circuits; The single-unit current sampling circuit includes: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverting circuit, and a first digital potentiometer; the parallel current summing circuit includes: an instrumentation amplifier circuit, a second proportional adjustment circuit, a second unit inverting circuit, a second digital potentiometer, and multiple proportional input resistors; the input terminal of the first differential amplifier circuit samples the single-unit current flowing through the sampling resistor; the output terminal of the first differential amplifier circuit is connected to the B terminal of the first digital potentiometer; the W terminal of the first digital potentiometer is connected to the inverting input terminal of the first proportional adjustment circuit; the A terminal of the first digital potentiometer is connected to the output terminal of the first proportional adjustment circuit; the output terminal of the first proportional adjustment circuit is connected to the input terminal of the first unit inverting circuit, wherein the output terminal of the first proportional adjustment circuit outputs a PARA+ signal, and the output terminal of the first unit inverting circuit outputs a PARA- signal; the PARA+ signal terminals of the multiple single-unit current sampling circuits are all connected to the parallel current summing circuit. The PARA+ signal terminal of the circuit is connected, and the PARA- signal terminals of multiple single-unit current sampling circuits are all connected to the PARA- signal terminal of the parallel current summing circuit. The number of proportional input resistors is twice that of the single-unit current sampling circuit. The multiple proportional input resistors are divided into two groups. All the proportional input resistors in the first group are connected in parallel. One of the parallel common terminals is used as the PARA+ signal terminal of the parallel current summing circuit, and the other parallel common terminal is connected to the first input terminal of the instrumentation amplifier circuit. All the proportional input resistors in the second group are also connected in parallel. One of the parallel common terminals is used as the PARA- signal terminal of the parallel current summing circuit, and the other parallel common terminal is connected to the second input terminal of the instrumentation amplifier circuit. The output terminal of the instrumentation amplifier circuit is connected to the A terminal of the second digital potentiometer. The W terminal of the second digital potentiometer is connected to the inverting input terminal of the second proportional adjustment circuit, and the B terminal of the second digital potentiometer is connected to the input terminal of the second unit inverting circuit.

2. The parallel current summing system according to claim 1, characterized in that, The first differential amplifier circuit includes: sampling resistors R3, R5, R6, R7, R8, and R9, and a first operational amplifier U1; one end of resistor R5 is connected to the inverting input of the first operational amplifier U1, one end of resistor R6 is connected to the non-inverting input of the first operational amplifier U1, and the other ends of resistors R5 and R6 are respectively connected to the two ends of sampling resistor R3; one end of resistor R7 is connected to the inverting input of the first operational amplifier U1, and the other end of resistor R7 is connected to the output of the first operational amplifier U1; one end of resistor R8 is connected to the non-inverting input of the first operational amplifier U1, and the other end of resistor R8 is grounded; one end of resistor R9 is connected to the output of the first operational amplifier U1, and the other end of resistor R9 is connected to the B terminal of the first digital potentiometer; the output signal of the first operational amplifier U1 serves as the single-machine ADC1 signal.

3. The parallel current summing system according to claim 2, characterized in that, The first proportional adjustment circuit includes: a resistor R10 and a second operational amplifier U2; the W terminal of the first digital potentiometer is connected to the inverting input terminal of the second operational amplifier U2, the non-inverting input terminal of the second operational amplifier U2 is grounded, the A terminal of the first digital potentiometer is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the output terminal of the second operational amplifier U2; the output signal of the second operational amplifier U2 serves as the PARA+ signal.

4. The parallel current summing system according to claim 3, characterized in that, The first unit inverting circuit includes: resistor R14, resistor R15, and third operational amplifier U3; one end of resistor R14 is connected to the output terminal of the second operational amplifier U2, and the other end of resistor R14 is connected to the inverting input terminal of the third operational amplifier U3; one end of resistor R15 is connected to the inverting input terminal of the third operational amplifier U3, and the other end of resistor R15 is connected to the output terminal of the third operational amplifier U3; the non-inverting input terminal of the third operational amplifier U3 is grounded; the output signal of the third operational amplifier U3 serves as the PARA- signal.

5. The parallel current summing system according to claim 4, characterized in that, The instrumentation amplifier circuit includes: resistors R16, R17, R18, R19, R20, and R21; a fourth operational amplifier U4; a fifth operational amplifier U5; and a sixth operational amplifier U6. The common terminal of the parallel connection of the first set of proportional input resistors is connected to the inverting input of the fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is grounded. One end of resistor R16 is connected to the inverting input of the fourth operational amplifier U4, and the other end of resistor R16 is connected to the output of the fourth operational amplifier U4. The common terminal of the parallel connection of the second set of proportional input resistors is connected to the inverting input of the fifth operational amplifier U5. The non-inverting input of the fifth operational amplifier U5 is connected to... One end of resistor R17 is connected to the inverting input of the fifth operational amplifier U5, and the other end of resistor R17 is connected to the output of the fifth operational amplifier U5; one end of resistor R18 is connected to the output of the fourth operational amplifier U4, and the other end of resistor R18 is connected to the inverting input of the sixth operational amplifier U6; one end of resistor R19 is connected to the output of the fifth operational amplifier U5, and the other end of resistor R19 is connected to the non-inverting input of the sixth operational amplifier U6; one end of resistor R20 is connected to the inverting input of the sixth operational amplifier U6, and the other end of resistor R20 is connected to the output of the sixth operational amplifier U6; one end of resistor R21 is connected to the non-inverting input of the sixth operational amplifier U6, and the other end of resistor R21 is grounded.

6. The parallel current summing system according to claim 5, characterized in that, The second proportional adjustment circuit includes: a seventh operational amplifier U7; the A terminal of the second digital potentiometer is connected to the output terminal of the sixth operational amplifier U6, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the seventh operational amplifier U7, the B terminal of the second digital potentiometer is connected to the output terminal of the seventh operational amplifier U7, and the non-inverting input terminal of the seventh operational amplifier U7 is grounded.

7. The parallel current summing system according to claim 6, characterized in that, The second unit inverting circuit includes: resistor R24, resistor R25, and eighth operational amplifier U8; one end of resistor R24 ​​is connected to the output terminal of seventh operational amplifier U7, and the other end of resistor R24 ​​is connected to the inverting input terminal of eighth operational amplifier U8; one end of resistor R25 is connected to the inverting input terminal of eighth operational amplifier U8, and the other end of resistor R25 is connected to the output terminal of eighth operational amplifier U8; the non-inverting input terminal of eighth operational amplifier U8 is grounded; and the output terminal of eighth operational amplifier U8 serves as the ADC2 signal output terminal.

8. The parallel current summing system according to claim 1, characterized in that, The digital potentiometer in question is model AD5292.

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