Delay reset circuit and power terminal equipment

Abstract

The utility model provides a delay reset circuit and power terminal equipment. The delay reset circuit comprises a reset switch, one end of which is connected with a power supply; the reset early warning circuit is connected with the other end of the reset switch and is used for outputting an early warning signal when the reset switch is in a closed state; the other end of the reset switch is also connected with the time delay circuit; the reset circuit is connected with the time delay circuit; a first port of the control module is connected with the reset early warning circuit, and the control module stores internal data of the control module after outputting an early warning signal based on the reset early warning circuit; and a second port of the control module is connected with the reset circuit. According to the utility model, when the reset switch is in a closed state, the reset early warning circuit can send out an early warning signal, so that the control module can store data needing to be stored before resetting, and the technical effect that the data can be effectively stored during hard resetting is realized.

Description

Technical Field

[0001] This utility model relates to the field of hardware circuit technology, and more specifically, to a time-delayed reset circuit and a power terminal device. Background Technology

[0002] In embedded systems, a hard reset may be required during operation for various reasons (such as pressing the reset button). However, if data read / write operations are in progress during the system reset process, data loss or corruption may occur. Therefore, how to effectively preserve data during a system hard reset has become a pressing problem. Utility Model Content

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related technologies.

[0004] Therefore, the first aspect of this utility model proposes a time-delayed reset circuit.

[0005] The second aspect of this utility model proposes a power terminal device.

[0006] In view of the above, according to the first aspect of this utility model, a delayed reset circuit is proposed, wherein the delayed reset circuit includes: a reset switch, one end of which is connected to a power supply; a reset warning circuit, which is connected to the other end of the reset switch and is used to output a warning signal when the reset switch is in a closed state; a delay circuit, the other end of the reset switch is also connected to the delay circuit; a reset circuit, which is connected to the delay circuit; a control module, the first port of which is connected to the reset warning circuit and, after the reset warning circuit outputs a warning signal, saves the internal data of the control module; and the second port of which is connected to the reset circuit.

[0007] The delayed reset circuit provided by this utility model mainly includes: a reset switch, a reset warning circuit, a delay circuit, a reset circuit, and a control module. One end of the reset switch is connected to the power supply. When the reset switch is closed, the power supply provides current to the entire delayed reset circuit. One end of the reset warning circuit is connected to the other end of the reset switch. When the reset switch is closed, the power supply inputs current to the reset warning circuit through the reset switch, turning on the reset warning circuit and outputting a warning signal. Simultaneously, the reset warning circuit is connected to the first port of the control module. When the reset switch is closed, the reset warning circuit outputs a warning signal to the control module through the first port. Upon receiving the warning signal, the control module saves the data that needs to be stored internally. The other end of the reset switch is also connected to a delay circuit, which is connected to the reset circuit. The reset circuit is also connected to the second port of the control module. When the reset switch is closed, the power supply inputs current to the delay circuit through the reset switch. After a preset delay time, the delay circuit sends the current to the reset circuit. Upon receiving the current, the reset circuit starts working and outputs a reset signal, which is then sent to the control module through the second port of the control module. Upon receiving the reset signal, the control module performs a reset operation. In this invention, the power supply is connected to one end of the reset switch, and the other end of the reset switch is connected to both the reset warning circuit and the delay circuit. When the reset switch is closed, current flows through the reset switch into both the reset warning circuit and the delay circuit, enabling them to conduct. The reset warning circuit is then connected to the first port of the control module. When the reset warning circuit is active, it outputs a warning signal to the control module through the first port. Upon receiving the warning signal, the control module saves the data that needs to be saved. The delay circuit is connected to the reset circuit. When the delay circuit is turned on, it transmits current to the reset circuit after a preset time to turn on the reset circuit. The reset circuit is connected to the second port of the control module. When the reset circuit is turned on, it outputs a reset signal to the control module through the second port to reset the control module. In this invention, by having the control module receive a warning signal before receiving the reset signal to save the data that needs to be saved, the technical effect of effectively saving data during a hard reset is achieved.

[0008] The delay reset circuit according to the present invention may also have the following technical features:

[0009] In some technical solutions, optionally, the reset warning circuit includes: a first resistor, the first end of which is connected to a reset switch, and the second end of which is connected to a first port of the control module; a second resistor, the first end of which is connected to the second end of the first resistor, the second end of which is grounded, and the first end of which is also connected to the first port of the control module; wherein, when the voltage across the second resistor is greater than a first preset voltage, a warning signal is output.

[0010] In this technical solution, the reset warning circuit includes a first resistor and a second resistor. The first end of the first resistor is connected to a reset switch, and the second end is connected to a first port of the control module. The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded. Simultaneously, the first end of the second resistor is also connected to the first port of the control module. That is, the first and second resistors are connected in series between the reset switch and ground, forming a current loop when the reset switch is closed. The first port of the control module is connected to the center point between the first and second resistors. When the reset switch is closed, the voltage value at the center point between the first and second resistors is obtained by voltage division between the two resistors. When the voltage across the second resistor is greater than a first preset voltage, a warning signal is output. The first preset voltage is the high-level threshold voltage of the first port of the control module. When the voltage across the second resistor is greater than the high-level threshold voltage of the first port of the control module, the reset warning circuit inputs a high level to the control module, causing the control module to save the data that needs to be saved. The resistance values ​​of the first and second resistors are determined based on the power supply voltage of the control module and the voltage of the power supply. This ensures that the voltage across the second resistor after voltage division, i.e., the voltage at the midpoint between the first and second resistors, is higher than the high-level threshold voltage of the first port of the control module, but lower than the power supply voltage of the control module. This invention, by setting a first resistor and a second resistor in the reset warning circuit, enables the output of a warning signal to the control module when the voltage across the second resistor exceeds a first preset voltage.

[0011] In some technical solutions, the reset warning circuit may optionally include: a first capacitor, the first end of which is connected to the first end of a second resistor, and the second end of the first capacitor is grounded to filter interference signals.

[0012] In this technical solution, the reset warning circuit also includes a first capacitor. The first terminal of the first capacitor is connected to the first terminal of the second resistor, and the second terminal of the first capacitor is grounded; that is, the first capacitor and the second resistor are connected in parallel. The first capacitor is typically selected as a pF-level capacitor. By connecting the second resistor in parallel with the first capacitor, the first capacitor can filter out high-frequency interference signals, thereby ensuring the signal quality of the warning signal.

[0013] In some technical solutions, the reset warning circuit may optionally include a third resistor, the first end of which is connected to the first end of the second resistor, and the second end of which is connected to the first port of the control module, for attenuating interference signals.

[0014] In this technical solution, the reset warning circuit further includes a third resistor. The first end of the third resistor is connected to both the first end of the second resistor and the second end of the first resistor, and the second end of the third resistor is connected to the first port of the control module. In other words, the center point of the third resistor connected in series between the first and second resistors is connected to the first port of the control module. By placing the third resistor between the center point and the first port, interference signals in the warning signal output by the reset warning circuit can be attenuated, thereby improving the signal quality of the warning signal and significantly reducing the possibility of malfunctions at the first port of the control module. The resistance value of the first resistor can be within 100 ohms.

[0015] In some technical solutions, the delay circuit may optionally include: a fourth resistor, the first end of which is connected to a reset switch; a fifth resistor, the first end of which is connected to the second end of the fourth resistor, and the second end of the fifth resistor is grounded; a second capacitor, the first end of which is connected to the first end of the fifth resistor, and the second end of which is connected to the second end of the fifth resistor; and a third capacitor, the first end of which is connected to both the first end of the second capacitor and the reset circuit, and the second end of which is connected to the second end of the second capacitor.

[0016] In this technical solution, the delay circuit includes a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor. The first terminal of the fourth resistor is connected to the reset switch, the second terminal of the fourth resistor is connected to the first terminal of the fifth resistor, and the second terminal of the fifth resistor is grounded. That is, the fourth and fifth resistors are connected in series and then positioned between the reset switch and ground. Simultaneously, the first terminal of the second capacitor is connected to the first terminal of the fifth resistor, and the second terminal of the second capacitor is connected to the second terminal of the fifth resistor, meaning the second capacitor and the fifth resistor are connected in parallel. The first terminal of the third capacitor is connected to the first terminal of the second capacitor, and the second terminal of the third capacitor is connected to the second terminal of the second capacitor, meaning the third capacitor and the second capacitor are connected in parallel. The first terminal of the third capacitor is also connected to the reset circuit, so that when the voltage across the third capacitor reaches the threshold voltage for the reset circuit to conduct, the reset circuit can be activated. In the delay circuit, when the reset switch is closed, the power supply charges the second and third capacitors through the fourth resistor. The fourth and fifth resistors divide the voltage, and the voltage across the clamping capacitors can be charged up to half the power supply voltage. When the voltage across the second and third capacitors reaches the threshold voltage for the reset circuit to conduct, the reset circuit is activated. The values ​​of the fourth resistor, second capacitor, and third capacitor determine the delay reset time, and the resistance value of the fourth resistor is the same as that of the fifth resistor. In this invention, by setting a delay circuit including a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor, a delay of the reset signal is achieved.

[0017] In some technical solutions, optionally, the first end of the first resistor is connected to the first end of the fourth resistor; the second end of the second resistor is connected to the second end of the fifth resistor; wherein, when the reset switch is in the open state, the voltage across the fifth resistor is discharged through the first resistor and the second resistor.

[0018] In this technical solution, the first end of the first resistor is also connected to the first end of the fourth resistor, and the second end of the second resistor is also connected to the second end of the fifth resistor. That is, in this invention, the first, second, fourth, and fifth resistors, the second capacitor, and the third capacitor can also form a discharge circuit. It can be understood that after the reset switch is closed, the second and third capacitors will be filled with voltage. Therefore, when the reset switch is open, the voltage in the second and third capacitors needs to be discharged. Thus, connecting the first and fourth resistors, and connecting the second and fifth resistors, makes the first, second, fourth, and fifth resistors form a loop. Simultaneously, since the second and third capacitors are both connected in parallel with the fifth resistor, the first, second, fourth, and fifth resistors, the second capacitor, and the third capacitor form a loop. Therefore, when the reset switch is open, the voltage in the second and third capacitors will be discharged through the first and second resistors. This ensures the safety of the entire delayed reset circuit when the reset switch is open.

[0019] In some technical solutions, the reset circuit may optionally include: a sixth resistor, the first end of which is connected to the power supply; a power transistor, the gate of which is connected to the delay circuit, the source of which is grounded, and the drain of which is connected to the second end of the sixth resistor and the second port of the control module.

[0020] In this technical solution, the reset circuit includes a sixth resistor and a power transistor. The gate of the power transistor is connected to a delay circuit, its source is grounded, and its drain is connected to the second port of the control module. When the voltage of the third capacitor in the delay circuit reaches the turn-on voltage of the power transistor's gate, the power transistor conducts, inputting a high-level signal to the second port of the control module, thus resetting the control module. The first end of the sixth resistor is connected to the power supply, and the second end is connected to the drain of the power transistor. When the power transistor is turned on, the sixth resistor limits its current. In this invention, by setting a power transistor and a sixth resistor in the reset circuit, the power transistor conducts when the voltage in the delay circuit reaches its turn-on voltage, inputting a high-level signal (reset signal) to the second port of the control module, thereby resetting the control module. Simultaneously, by placing the sixth resistor between the power supply and the drain of the power transistor, the current of the power transistor is limited when it is turned on, ensuring the safe operation of the power transistor.

[0021] In some technical solutions, the reset circuit may optionally include a fourth capacitor, the first end of which is connected to the drain of the power transistor, and the second end of which is connected to the source of the power transistor, for filtering out high-frequency interference signals and providing a power-on reset signal.

[0022] In this technical solution, the reset circuit also includes a fourth capacitor. The first terminal of the fourth capacitor is connected to the drain of the power transistor, and the second terminal is connected to the source of the power transistor, meaning the fourth capacitor is connected in parallel with the power transistor. The fourth capacitor is a filter capacitor, typically selected at the pF level, used to filter out high-frequency interference signals and provide a power-on reset signal. Firstly, when the control module is first powered on, the voltage across the fourth capacitor cannot change abruptly; the voltage rises slowly from 0V, and the output reset signal is generated when the voltage rises below the reset signal threshold voltage. Secondly, after the control module is powered on, when the voltage across the third capacitor in the delay circuit is greater than the turn-on voltage, the power transistor conducts and outputs a reset signal.

[0023] In some technical solutions, the power transistor may optionally include a metal-oxide-semiconductor field-effect transistor and / or an insulated-gate bipolar transistor.

[0024] In this technical solution, the power transistor can be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Alternatively, an N-type metal-oxide-semiconductor field-effect transistor can be selected.

[0025] According to a second aspect of the present invention, a power terminal device is provided, including a time-delayed reset circuit as described in any of the above technical solutions.

[0026] The power terminal equipment provided by this utility model includes the delayed reset circuit as described in any of the above technical solutions. Therefore, the power terminal equipment includes all the beneficial effects of the delayed reset circuit as described in any of the above technical solutions, which will not be repeated here. The power terminal equipment can be some electronic products with button reset. For example, industrial control devices, household appliances, and automotive power terminal equipment that require hard reset.

[0027] Additional aspects and advantages of this invention will become apparent in the description that follows, or may be learned by practice of this invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1One of the structural schematic diagrams of a delay reset circuit according to an embodiment of the present invention is shown;

[0030] Figure 2 A second schematic diagram of the delayed reset circuit according to an embodiment of this utility model is shown.

[0031] Figure 3 The third schematic diagram shows the structure of a delayed reset circuit according to an embodiment of the present invention;

[0032] Figure 4 The fourth schematic diagram shows the structure of a delayed reset circuit according to an embodiment of the present invention;

[0033] Figure 5 The fifth schematic diagram shows the structure of a delayed reset circuit according to an embodiment of the present invention;

[0034] Figure 6 The sixth schematic diagram shows the structure of a delayed reset circuit according to an embodiment of the present invention;

[0035] Figure 7 A schematic diagram of the structure of a power terminal device according to an embodiment of the present invention is shown.

[0036] in, Figures 1 to 7 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0037] 100 Delay Reset Circuit, 102 Reset Switch, VCC Power Supply, 104 Reset Warning Circuit, 106 Delay Circuit, 108 Reset Circuit, 110 Control Module, 1102 First Port, 1104 Second Port, R1 First Resistor, R2 Second Resistor, R3 Third Resistor, R4 Fourth Resistor, R5 Fifth Resistor, R6 Sixth Resistor, C1 First Capacitor, C2 Second Capacitor, C3 Third Capacitor, C4 Fourth Capacitor, Q1 Power Transistor, G Gate, S Source, D Drain, 10 Power Terminal Equipment, GND Ground. Detailed Implementation

[0038] To better understand the above-mentioned objectives, features, and advantages of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of this utility model and the features thereof can be combined with each other.

[0039] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0040] like Figure 1 As shown, this utility model proposes a delayed reset circuit 100, which includes: a reset switch 102, one end of which is connected to the power supply VCC; a reset warning circuit 104, which is connected to the other end of the reset switch 102 and is used to output a warning signal when the reset switch 102 is in the closed state; a delay circuit 106, the other end of the reset switch 102 is also connected to the delay circuit 106; a reset circuit 108, which is connected to the delay circuit 106; and a control module 110, whose first port 1102 is connected to the reset warning circuit 104 and saves the internal data of the control module 110 after the reset warning circuit 104 outputs a warning signal; and the second port 1104 of the control module 110 is connected to the reset circuit 108.

[0041] The delayed reset circuit 100 provided by this utility model mainly includes: a reset switch 102, a reset warning circuit 104, a delay circuit 106, a reset circuit 108, and a control module 110. One end of the reset switch 102 is connected to the power supply VCC. When the reset switch 102 is closed, the power supply VCC provides current to the entire delayed reset circuit 100. The reset switch 102 can be a button. One end of the reset warning circuit 104 is connected to the other end of the reset switch 102. When the reset switch 102 is closed, the power supply VCC inputs current to the reset warning circuit 104 through the reset switch 102, turning on the reset warning circuit 104 and outputting a warning signal. Meanwhile, the reset warning circuit 104 is connected to the first port 1102 of the control module 110. When the reset switch 102 is closed, the reset warning circuit 104 will output a warning signal to the control module 110 through the first port 1102. After receiving the warning signal, the control module 110 will save the data that needs to be saved inside the control module 110. The first port 1102 can be an I / O (Input / Output) port. The other end of the reset switch 102 is also connected to the delay circuit 106, which is connected to the reset circuit 108. The reset circuit 108 is also connected to the second port 1104 of the control module 110. When the reset switch 102 is closed, the power supply VCC inputs current to the delay circuit 106 through the reset switch 102. After a preset delay time, the delay circuit 106 sends the current to the reset circuit 108. After receiving the current, the reset circuit 108 starts to work and outputs a reset signal. The reset signal is then sent to the control module 110 through the second port 1104. After receiving the reset signal, the control module 110 performs a reset operation. The second port 1104 can be an RSTN (Reset Set Toggle Not) port. In this invention, the power supply VCC is connected to one end of the reset switch 102, and the other end of the reset switch 102 is connected to the reset warning circuit 104 and the delay circuit 106 respectively. When the reset switch 102 is closed, the current flows through the reset switch 102 into the reset warning circuit 104 and the delay circuit 106 respectively, so that the reset warning circuit 104 and the delay circuit 106 are turned on. Then, the reset warning circuit 104 is connected to the first port 1102 of the control module 110. When the reset warning circuit 104 is turned on, it will output a warning signal to the control module 110 through the first port 1102. When the control module 110 receives the warning signal, it will save the data that needs to be saved.The delay circuit 106 is connected to the reset circuit 108. When the delay circuit 106 is turned on, it will transmit current to the reset circuit 108 after a preset time, causing the reset circuit 108 to turn on. The reset circuit 108 is connected to the second port 1104 of the control module 110. When the reset circuit 108 is turned on, it will output a reset signal to the control module 110 through the second port 1104, causing the control module 110 to reset. In this invention, by having the control module 110 receive a warning signal before receiving the reset signal, the data that needs to be saved can be saved, thereby achieving the technical effect of effectively saving data during a hard reset.

[0042] like Figure 2 The diagram shows the circuit diagram of the reset warning circuit 104. When the reset switch 102 is pressed, the output of the reset warning circuit 104 changes from low to high. When the I / O (Input / Output) port of the control module 110 detects the high level, it informs the system that a reset is imminent. Simultaneously, the delay circuit 106 starts charging the second capacitor C2 and the third capacitor C3 through the fourth resistor R4. When the voltage across the third capacitor C3 and the fourth capacitor C4 reaches the turn-on voltage of the power transistor Q1, the power transistor Q1 conducts and outputs a reset signal. The control module 110 detects the reset signal through the RSRN port, and the system restarts. When the reset switch 102 is released, the voltage across the third capacitor C3 and the fourth capacitor C4 is discharged through the first resistor R1 and the second resistor R2. When the voltage across the third capacitor C3 and the fourth capacitor C4 falls below the turn-on voltage of the power transistor Q1, the power transistor Q1 turns off, the reset signal outputs a high level, and the system restart is about to complete.

[0043] like Figure 2 and Figure 3 As shown, the reset warning circuit 104 includes: a first resistor R1, the first end of which is connected to the reset switch 102, and the second end of which is connected to the first port 1102 of the control module 110; a second resistor R2, the first end of which is connected to the second end of the first resistor R1, the second end of which is grounded (GND), and the first end of which is also connected to the first port 1102 of the control module 110; wherein, when the voltage across the second resistor R2 is greater than a first preset voltage, a warning signal is output.

[0044] In this embodiment, the reset warning circuit 104 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the reset switch 102, and the second end of the first resistor R1 is connected to the first port 1102 of the control module 110. The first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is grounded (GND). Simultaneously, the first end of the second resistor R2 is also connected to the first port 1102 of the control module 110. That is, the first resistor R1 and the second resistor R2 are connected in series between the reset switch 102 and the ground wire, thus forming a current loop when the reset switch 102 is closed. The first port 1102 of the control module 110 is connected to the center point A between the first resistor R1 and the second resistor R2. When the reset switch 102 is closed, the voltage value VA at the center point between the first resistor R1 and the second resistor R2 is obtained by voltage division using the first resistor R1 and the second resistor R2. When the voltage across the second resistor R2 is greater than the first preset voltage, a warning signal is output. The first preset voltage is the high-level threshold voltage of the first port 1102 of the control module 110. When the voltage across the second resistor R2 is greater than the high-level threshold voltage of the first port 1102 of the control module 110, the reset warning circuit 104 inputs a high level to the control module 110, thereby enabling the control module 110 to save the data that needs to be saved. The resistance values ​​of the first resistor R1 and the second resistor R2 are determined based on the power supply voltage of the control module 110 and the voltage of the power supply VCC. For example, the power supply VCC voltage can be 3V, the resistance value of the first resistor R1 can be 1K ohms, and the resistance value of the second resistor R2 can be 10K ohms. This ensures that the voltage across the second resistor R2 after voltage division, i.e., the voltage at the midpoint between the first resistor R1 and the second resistor R2, is higher than the high-level threshold voltage of the first port 1102 of the control module 110 and lower than the power supply voltage of the control module 110. This invention sets a first resistor R1 and a second resistor R2 in the reset warning circuit 104, so that when the voltage across the second resistor R2 is greater than a first preset voltage, a warning signal can be output to the control module 110.

[0045] In some embodiments, optionally, such as Figure 2 and Figure 3 As shown, the reset warning circuit 104 also includes: a first capacitor C1, the first end of the first capacitor C1 is connected to the first end of the second resistor R2, and the second end of the first capacitor C1 is grounded (GND) to filter interference signals.

[0046] In this embodiment, the reset warning circuit 104 further includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the first terminal of the second resistor R2, and the second terminal of the first capacitor C1 is grounded (GND), meaning the first capacitor C1 and the second resistor R2 are connected in parallel. The first capacitor C1 is typically selected as a pF-level capacitor, and its capacitance can be 47pF. By connecting the second resistor R2 in parallel with the first capacitor C1, the first capacitor C1 can filter out high-frequency interference signals, thereby ensuring the signal quality of the warning signal.

[0047] In some embodiments, optionally, such as Figure 2 and Figure 3 As shown, the reset warning circuit 104 also includes a third resistor R3, the first end of the third resistor R3 is connected to the first end of the second resistor R2, and the second end of the third resistor R3 is connected to the first port 1102 of the control module 110, for attenuating interference signals.

[0048] In this embodiment, the reset warning circuit 104 further includes a third resistor R3. The first end of the third resistor R3 is connected to the first end of the second resistor R2 and the second end of the first resistor R1, respectively, and the second end of the third resistor R3 is connected to the first port 1102 of the control module 110. That is, the third resistor R3 is connected in series between the center point of the first resistor R1 and the second resistor R2 and then to the first port 1102 of the control module 110. By placing the third resistor R3 between the center point and the first port 1102, interference signals in the warning signal output by the reset warning circuit 104 can be attenuated, thereby improving the signal quality of the warning signal and significantly reducing the possibility of malfunctions at the first port 1102 of the control module 110. The resistance value of the first resistor R1 can be within 100 ohms.

[0049] In some embodiments, optionally, such as Figure 2 and Figure 4 As shown, the delay circuit 106 includes: a fourth resistor R4, the first end of which is connected to the reset switch 102; a fifth resistor R5, the first end of which is connected to the second end of the fourth resistor R4, and the second end of the fifth resistor R5 is grounded (GND); a second capacitor C2, the first end of which is connected to the first end of the fifth resistor R5, and the second end of which is connected to the second end of the fifth resistor R5; and a third capacitor C3, the first end of which is connected to the first end of the second capacitor C2 and the reset circuit 108, and the second end of the third capacitor C3 is connected to the second end of the second capacitor C2.

[0050] In this embodiment, the delay circuit 106 includes a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a third capacitor C3. The first end of the fourth resistor R4 is connected to the reset switch 102, and the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is grounded (GND). That is, the fourth resistor R4 and the fifth resistor R5 are connected in series and then positioned between the reset switch 102 and the ground wire. Simultaneously, the first end of the second capacitor C2 is connected to the first end of the fifth resistor R5, and the second end of the second capacitor C2 is connected to the second end of the fifth resistor R5, meaning the second capacitor C2 and the fifth resistor R5 are connected in parallel. The first end of the third capacitor C3 is connected to the first end of the second capacitor C2, and the second end of the third capacitor C3 is connected to the second end of the second capacitor C2, meaning the third capacitor C3 and the second capacitor C2 are connected in parallel. Simultaneously, the first end of the third capacitor C3 is connected to the reset circuit 108, thereby enabling the reset circuit 108 to conduct when the voltage across the third capacitor C3 reaches the threshold voltage required for the reset circuit 108 to operate. Point B is the connection point of the fourth resistor R4, the fifth resistor R5, the second capacitor C2, and the third capacitor C3. In the delay circuit 106, when the reset switch 102 is closed, the power supply VCC charges the second capacitor C2 and the third capacitor C3 through the fourth resistor R4. The fourth resistor R4 and the fifth resistor R5 divide the voltage, and the voltage across the clamping capacitors can be charged up to half the voltage of the power supply VCC, i.e., VB1 = 1.5V. When the voltage of the second capacitor C2 and the third capacitor C3 reaches the threshold voltage for the reset circuit 108 to conduct, the reset circuit 108 is turned on. The values ​​of the fourth resistor R4, the second capacitor C2, and the third capacitor C3 determine the delay reset time, and the resistance value of the fourth resistor R4 is the same as the resistance value of the fifth resistor R5. The formula for the delay reset time t can be:

[0051]

[0052] Where t is time, R4 is the resistance of the fourth resistor, C2 is the capacitance of the second capacitor, C3 is the capacitance of the third capacitor, VCC is the voltage of the power supply, and VB is the voltage at point B.

[0053] In this invention, R4 = 510KΩ, C2 = C3 = 10uF, VCC = 3.3V, and VB can be set as the voltage at point B. The VB voltage is used to turn on the power transistor Q1 in the reset circuit 108. The minimum turn-on voltage VGS(th) of the power transistor Q1 is 1V, so VB is taken as 1.2V. Substituting these values ​​into the formula, we get t ≈ 4.6s. That is, the time for the VB voltage to charge from 0V to the turn-on voltage of 1V for the power transistor Q1 is approximately 4.6s. That is, when the reset switch 102 is closed, the delay circuit 106 outputs a reset signal after 4.6s. In this invention, the delay of the reset signal is achieved by setting the delay circuit 106 to include a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a third capacitor C3.

[0054] In some embodiments, optionally, such as Figure 5 As shown, the first end of the first resistor R1 is connected to the first end of the fourth resistor R4; the second end of the second resistor R2 is connected to the second end of the fifth resistor R5; wherein, when the reset switch 102 is in the open state, the voltage across the fifth resistor R5 is discharged through the first resistor R1 and the second resistor R2.

[0055] In this embodiment, the first end of the first resistor R1 is also connected to the first end of the fourth resistor R4, and the second end of the second resistor R2 is also connected to the second end of the fifth resistor R5. That is, in this invention, the first resistor R1, the second resistor R2, the fourth resistor R4, the fifth resistor R5, the second capacitor C2, and the third capacitor C3 can also form a discharge circuit. It is understood that after the reset switch 102 is closed, the second capacitor C2 and the third capacitor C3 will be fully charged with voltage. Therefore, when the reset switch 102 is opened, the voltage in the second capacitor C2 and the third capacitor C3 needs to be discharged. Therefore, the first resistor R1 is connected to the first end of the fourth resistor R4, and the second end of the second resistor R2 is connected to the second end of the fifth resistor R5. Resistor R1 is connected to resistor R4, and resistor R2 is connected to resistor R5, forming a circuit. Since capacitors C2 and C3 are connected in parallel with resistor R5, the circuit also forms a loop. Therefore, when reset switch 102 is open, the voltage in capacitors C2 and C3 needs to be discharged through resistors R1 and R2. This ensures the safety of the entire delayed reset circuit 100 when reset switch 102 is open. For example, the discharge time can be calculated using the RC discharge formula:

[0056]

[0057] Where t represents time, R5 represents the resistance value of the fifth resistor, R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, R4 represents the resistance value of the fourth resistor, C2 represents the capacitance value of the second capacitor, C3 represents the capacitance value of the third capacitor, VB1 represents the maximum voltage value at point B, and VB represents the low-level voltage threshold of the second port.

[0058] In this invention, R2 = 510KΩ, R3 = 510KΩ, R4 = 510KΩ, and R5 = 510KΩ. Substituting these values ​​into the formula, we obtain t ≈ 1.1s. That is, the time it takes for the VB voltage to discharge from the 1.5V turn-on voltage of power transistor Q1 to the low-level threshold of 1.2V on the reset IO pin is approximately 1.1s. In other words, when the reset switch 102 is turned off, the reset signal output by the delay circuit 106 is cut off after 1.1s.

[0059] In some embodiments, optionally, such as Figure 2 and Figure 6 As shown, the reset circuit 108 includes: a sixth resistor R6, the first end of which is connected to the power supply VCC; a power transistor Q1, the gate G of which is connected to the delay circuit 106, the source S of which is grounded (GND), and the drain D of which is connected to the second end of the sixth resistor R6 and the second port 1104 of the control module 110.

[0060] In this embodiment, the reset circuit 108 includes a sixth resistor R6 and a power transistor Q1. The gate G of the power transistor Q1 is connected to the delay circuit 106, the source S of the power transistor Q1 is grounded (GND), and the drain D of the power transistor Q1 is connected to the second port 1104 of the control module 110. When the voltage of the third capacitor C3 in the delay circuit 106 reaches the turn-on voltage of the gate G of the power transistor Q1, the power transistor Q1 will conduct, thereby inputting a high level to the second port 1104 of the control module 110, thus inputting a reset signal to the control module 110, causing the control module 110 to reset. The first end of the sixth resistor R6 is connected to the power supply VCC, and the second end of the sixth resistor R6 is connected to the drain D of the power transistor Q1. When the power transistor Q1 is turned on, the sixth resistor R6 can limit the current of the power transistor Q1. The resistance value of the sixth resistor R6 can be 51K ohms. In this invention, by setting a power transistor Q1 and a sixth resistor R6 in the reset circuit 108, the power transistor Q1 will conduct when the voltage in the delay circuit 106 reaches its turn-on voltage. Consequently, the power transistor Q1 will input a high-level reset signal to the second port 1104 of the control module 110, thus resetting the control module 110. Simultaneously, by placing the sixth resistor R6 between the power supply VCC and the drain D of the power transistor Q1, the current of the power transistor Q1 is limited when it is conducting, ensuring the safe operation of the power transistor Q1.

[0061] In some embodiments, optionally, such as Figure 6 As shown, the reset circuit 108 further includes a fourth capacitor C4, the first end of which is connected to the drain D of the power transistor Q1, and the second end of which is connected to the source S of the power transistor Q1, for filtering out high-frequency interference signals and providing a power-on reset signal.

[0062] In this embodiment, the reset circuit 108 further includes a fourth capacitor C4. The first terminal of the fourth capacitor C4 is connected to the drain (D) of the power transistor Q1, and the second terminal of the fourth capacitor C4 is connected to the source (S) of the power transistor Q1, meaning the fourth capacitor C4 is connected in parallel with the power transistor Q1. The fourth capacitor C4 is a filter capacitor, typically selected at the pF level, used to filter out high-frequency interference signals and provide a power-on reset signal. Firstly, when the control module 110 is first powered on, the voltage across the fourth capacitor C4 cannot change abruptly; the voltage across the fourth capacitor C4 gradually rises from 0V, and the output reset signal is generated when the rising voltage is below the threshold voltage of the reset signal. Secondly, after the control module 110 is powered on, when the voltage across the third capacitor C3 in the delay circuit 106 is greater than the turn-on voltage, the power transistor Q1 conducts and outputs a reset signal.

[0063] In some embodiments, the power transistor Q1 may optionally include a metal-oxide-semiconductor field-effect transistor and / or an insulated-gate bipolar transistor.

[0064] In this embodiment, the power transistor Q1 can be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Alternatively, the power transistor Q1 can be an N-type metal-oxide-semiconductor field-effect transistor.

[0065] like Figure 7 As shown, this utility model proposes a power terminal device 10, including a delayed reset circuit 100 as described in any of the above embodiments.

[0066] The power terminal device 10 provided by this utility model includes the delayed reset circuit 100 as described in any of the above embodiments. Therefore, the power terminal device 10 includes all the beneficial effects of the delayed reset circuit 100 as described in any of the above embodiments, which will not be repeated here. The power terminal device 10 can be an electronic product with a button reset function. For example, it can be an industrial control device, a household appliance, or an automotive power terminal device 10, etc., that requires a hard reset.

[0067] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, unless otherwise expressly specified and limited. The terms "connection," "installation," and "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0068] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0069] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A time-delayed reset circuit, characterized in that, include: A reset switch, one end of which is connected to a power supply; A reset warning circuit is provided, which is connected to the other end of the reset switch, and is used to output a warning signal when the reset switch is in the closed state. The other end of the reset switch is also connected to the delay circuit; A reset circuit, which is connected to the delay circuit; The control module has a first port connected to the reset warning circuit. After the reset warning circuit outputs the warning signal, the control module saves its internal data. The second port of the control module is connected to the reset circuit.

2. The delayed reset circuit according to claim 1, characterized in that, The reset warning circuit includes: A first resistor, the first end of which is connected to the reset switch, and the second end of which is connected to the first port of the control module; The second resistor has a first end connected to the second end of the first resistor, the second end of the second resistor is grounded, and the first end of the second resistor is also connected to the first port of the control module. Specifically, when the voltage across the second resistor is greater than a first preset voltage, the warning signal is output.

3. The delayed reset circuit according to claim 2, characterized in that, The reset warning circuit also includes: The first capacitor has its first terminal connected to the first terminal of the second resistor, and its second terminal grounded, for filtering interference signals.

4. The delayed reset circuit according to claim 3, characterized in that, The reset warning circuit also includes: The third resistor, with its first end connected to the first end of the second resistor and its second end connected to the first port of the control module, is used to attenuate interference signals.

5. The delayed reset circuit according to claim 2, characterized in that, The delay circuit includes: A fourth resistor, the first end of which is connected to the reset switch; The fifth resistor has its first end connected to the second end of the fourth resistor, and its second end is grounded. The second capacitor has its first terminal connected to the first terminal of the fifth resistor, and its second terminal connected to the second terminal of the fifth resistor. The third capacitor has its first terminal connected to the first terminal of the second capacitor and the reset circuit, and its second terminal connected to the second terminal of the second capacitor.

6. The delayed reset circuit according to claim 5, characterized in that, The first end of the first resistor is connected to the first end of the fourth resistor; The second terminal of the second resistor is connected to the second terminal of the fifth resistor; When the reset switch is in the open state, the voltage across the fifth resistor is discharged through the first resistor and the second resistor.

7. The time-delayed reset circuit according to any one of claims 1 to 6, characterized in that, The reset circuit includes: The sixth resistor, the first end of which is connected to the power supply; The power transistor has its gate connected to the delay circuit, its source grounded, and its drain connected to the second terminal of the sixth resistor and the second port of the control module.

8. The delayed reset circuit according to claim 7, characterized in that, The reset circuit also includes: The fourth capacitor has its first terminal connected to the drain of the power transistor and its second terminal connected to the source of the power transistor. It is used to filter out high-frequency interference signals and provide a power-on reset signal.

9. The delayed reset circuit according to claim 7, characterized in that, The power transistor includes a metal-oxide-semiconductor field-effect transistor and / or an insulated-gate bipolar transistor.

10. A power terminal device, characterized in that, include: The delayed reset circuit as described in any one of claims 1 to 9.

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