Simulation debugging system with fault judgment function

Abstract

The utility model discloses a simulation debugging system with a fault judgment function. Comprising an emulator mainboard, and an emulator state monitoring module, a chip state monitoring module, an interface state monitoring module, an error state analysis module and a display module which are integrated on the emulator mainboard, wherein the emulator state monitoring module, the chip state monitoring module, the interface state monitoring module and the error state analysis module are respectively connected with the display module; the chip state monitoring module, the interface state monitoring module and the error state analysis module are respectively connected with a tested chip; and the simulator state monitoring module is connected with the simulator mainboard. According to the utility model, the simulation debugging system is connected with the tested chip, so that the current state of the tested chip can be known in time, and the efficiency of debugging work is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip simulation debugging fault detection technical field, especially involve a kind of simulation debugging system with fault judgment. BACKGROUND

[0002] In the process of debugging chip, debugging personnel needs to use integrated development environment, and carries out simulation debugging to the chip being debugged by simulator. Simulator cannot correctly carry out chip debugging work due to the reasons such as the problem of hardware environment preparation, the bug of debugging program, the problem of chip itself peripheral or data link. At this time, if simulator cannot provide the state information about chip and simulator, it will cause the debugging personnel to spend a lot of time and energy to analyze the error reason. Therefore, a good simulator can make the chip debugging progress of debugging personnel achieve the effect of doubling the result with half the effort.

[0003] With the development of chip design and manufacturing industry, the types of simulator are also increasing. Chip simulation debugging becomes more and more important, and simulator is an important object for debugging development program and testing chip function in chip research and development stage and development stage. Simulator can carry out single-step tracking debugging to the test program of chip in cooperation with integrated development environment, and can use debugging means such as software breakpoint, hardware breakpoint and full-speed running, and can observe the value of various variables, SDRAM, DDR type storage space and real-time data of core register and peripheral register of chip in development environment, and real-time feedback the execution situation of chip program.

[0004] The simulator developed by Beijing Technology Co., Ltd. in the prior art has the following problems:

[0005] 1. There are too many indicator lights on the simulator, and the COM1 indicator light, the COM2 indicator light, the COM3 indicator light and the EMU1 indicator light have no prompt function for chip debugging, and the names of the indicator lights have no direct relationship with the functions of the indicator lights. When the simulator has a debugging fault, the debugging personnel needs to spend a lot of time to analyze the fault reason.

[0006] 2. The function of the indicator light of the simulator is not obvious, and the indicator light of the simulator can only simply feedback the state of the simulator, so that the whole debugging process consumes a long time and has low efficiency. INVENTION CONTENT

[0007] The utility model provides a kind of simulation debugging system with fault judgment to solve the technical problem mentioned in background art.

[0008] To achieve the above purpose, the technical scheme of the utility model is as follows:

[0009] The utility model provides a kind of simulation debugging system with fault judgment, including simulator mainboard and simulator state monitoring module, chip state monitoring module, interface state monitoring module, error state analysis module integrated on simulator mainboard 、 Display module:

[0010] Simulator state monitoring module, chip state monitoring module, interface state monitoring module, error state analysis module are connected with display module respectively, chip state monitoring module, interface state monitoring module, error state analysis module are connected with measured chip respectively;Simulator state monitoring module is connected with simulator mainboard.

[0011] Further, the interface state monitoring module is a JTAG interface state monitoring module, and the JTAG interface state monitoring module is connected with the JTAG interface of the measured chip.

[0012] Further, the simulation debugging system further includes an information interaction module, and the information interaction module is connected with the simulator state monitoring module, the chip state monitoring module, the interface state monitoring module and the error state analysis module respectively.

[0013] Further, the display module includes four different three-color indicator lights, which are a POWER indicator light, a STATE indicator light, a RUN indicator light and an ERROR indicator light.

[0014] Among them, the POWER indicator light is connected with the simulator state monitoring module, the RUN indicator light is connected with the chip state monitoring module, the STATE indicator light is connected with the JTAG interface state monitoring module, and the ERROR indicator light is connected with the error state analysis module.

[0015] The utility model has the advantages of:

[0016] 1. The simulation debugging system with fault judgment can quickly determine the current state of the chip, quickly feedback information to the debugging personnel through the four indicator lights, and speed up the work efficiency of the debugging personnel.

[0017] 2. The simulation debugging system has four indicator lights, which are a POWER indicator light, a STATE indicator light, a RUN indicator light and an ERROR indicator light.

[0018] In contrast, a certain existing emulator model has six status indicator lights, two more than this invention. However, this emulator cannot intuitively reflect the status of the emulator and chip. The six indicator lights not only have similar names, but their names are not directly related to their functions, requiring debugging personnel to consult the user manual. The four indicator lights in this invention, on the other hand, provide a more intuitive reflection of the emulator and chip status, eliminating the need for debugging personnel to consult the user manual, making it more convenient and efficient to use. Attached Figure Description

[0019] Figure 1 This is a connection block diagram of the simulation debugging system in this utility model;

[0020] Figure 2 The diagram shows the differences in the layout of multiple indicator lights in the simulation debugging system of this utility model and the multiple indicator lights in an existing DSP emulator. (a) is a layout diagram of multiple indicator lights in an existing DSP emulator; (b) is a layout diagram of multiple indicator lights in the simulation debugging system of this utility model. Detailed Implementation

[0021] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this utility model. However, this utility model can be implemented in many other different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.

[0022] In the existing technology, a certain model of simulator developed by a Beijing technology company has six status indicator lights, the functions of which are shown in Table 1. The indicator lights are named COM1, COM2, COM3, EMU1, EMU2, and EMU3. Each status indicator light has a different function, providing relevant information during power supply, operation, and configuration.

[0023] Table 1: Functional overview of 6 status indicator lights in a certain model of simulator developed by a Beijing technology company;

[0024] Identification Color Function Description COM1 Green Ready indicator light COM2 Green FPGA loading completion indicator light COM3 Green System Boot indicator light EMU1 Green Trace indicator light EMU2 Green Host communication indicator light EMU3 Green CCS connection indicator light

[0025] Currently, the aforementioned simulator model has the following problems:

[0026] a. The emulator has too many indicator lights. COM1 is the emulator preparation indicator, COM2 is the emulator FPGA (Field Programmable Gate Array) loading completion indicator, and COM3 is the emulator system boot indicator. These three indicators could be combined into one emulator ready indicator, and the name could be changed from COM to Ready for better clarity and easier memorization of their functions. EMU1 is the emulator's Trace indicator, which is rarely used and lacks practical value; it can be removed. These four indicator lights offer no guidance for chip debugging, and their names are not directly related to their functions. When the emulator malfunctions, debuggers need to spend a significant amount of time analyzing the cause. Some emulators have too few indicator lights, with only one STATUS indicator, providing even less information to debuggers.

[0027] b. The indicator lights on the emulator are not very useful. They only provide basic feedback on the emulator's status. For example, the EMU2 indicator light is a host communication indicator, which only indicates that the host and emulator are communicating, but does not detect data errors. The EMU3 indicator light is a CCS connection indicator, which only indicates whether the emulator is connected to the board, but cannot directly indicate the chip's status, and it is not directly related to chip emulation debugging. Therefore, this causes many inconveniences for debugging personnel when performing chip debugging, making it difficult to quickly troubleshoot emulator problems or directly determine the chip's status.

[0028] The reasons for the above problems are: 1. There are many designers and manufacturers of emulators, and there is no unified standard in the industry, resulting in differences in indicator lights for each type of emulator. 2. Emulator designers and manufacturers only focus on the debugging function of the emulator, and have not yet realized the importance of the fault diagnosis function of the emulator.

[0029] Reference Figure 1 This application provides a simulation debugging system with fault diagnosis capabilities, including a simulator motherboard and a simulator status monitoring module, a chip status monitoring module, an interface status monitoring module, and an error status analysis module integrated on the simulator motherboard. 、 Display module:

[0030] The emulator status monitoring module, chip status monitoring module, interface status monitoring module, and error status analysis module are connected to the display module, respectively; the chip status monitoring module, interface status monitoring module, and error status analysis module are connected to the chip under test, respectively; and the emulator status monitoring module is connected to the emulator motherboard.

[0031] The emulator status monitoring module is used to monitor the power-on status of the emulator motherboard, the startup status of the FPGA program on the emulator motherboard, and the startup status of the control program on the emulator motherboard.

[0032] The chip status monitoring module is used to monitor the status of the program of the chip under test; the status of the program of the chip under test includes normal operation status, software breakpoint pause status, and abnormal status.

[0033] The error status analysis module is used to monitor the operation of the ET (Emulation / Test) component of the chip under test, the start-up status of the chip under test registers, and the access status of the program address of the chip under test.

[0034] In some embodiments, the interface status monitoring module is a JTAG interface status monitoring module, which is connected to the JTAG interface of the chip under test.

[0035] The JTAG (Joint Test Action Group) interface status monitoring module is used to monitor the power-on status of the chip board, the data transmission status of the JTAG interface, and JTAG data anomalies.

[0036] In some embodiments, the simulation debugging system further includes an information interaction module, which is connected to the simulator status monitoring module, the chip status monitoring module, the interface status monitoring module, and the error status analysis module, respectively.

[0037] The information interaction module is used to generate a startup log. It prints the debugging error information output by the four modules—emulator status monitoring module, chip status monitoring module, JTAG interface status monitoring module, and error status analysis module—into the startup log. This prevents debugging personnel from misunderstanding the specific meaning of the indicator lights, reduces debugging pressure, and lowers the probability of misinterpreting the prompts.

[0038] In some embodiments, the display module includes four different tri-color indicator lights: a POWER indicator light, a STATE indicator light, a RUN indicator light, and an ERROR indicator light.

[0039] The POWER indicator is electrically connected to the emulator status monitoring module; the RUN indicator is electrically connected to the chip status monitoring module; the STATE indicator is electrically connected to the JTAG interface status monitoring module; and the ERROR indicator is electrically connected to the error status analysis module.

[0040] The simulation debugging system of this invention has four indicator lights: POWER, STATE, RUN, and ERROR. Each indicator uses a tri-color LED, providing different debugging information to the debugger through different colors. The names and functions of the indicator lights are closely related, allowing testers to quickly obtain debugging information about the chip under test and the emulator.

[0041] In contrast, a certain existing emulator model has six status indicator lights, two more than this invention. However, this emulator cannot intuitively reflect the status of the emulator and chip. The six indicator lights not only have similar names, but their names are not directly related to their functions, requiring debugging personnel to consult the user manual. The four indicator lights in this invention, on the other hand, provide a more intuitive reflection of the emulator and chip status, eliminating the need for debugging personnel to consult the user manual, making it more convenient and efficient to use.

[0042] The simulation and debugging system disclosed in this utility model, combined with the ET component design architecture of the chip under test, can quickly determine the current status of the chip under test through the data information on TDO (Test Data Output, JTAG pin) in JTAG, and quickly provide feedback information to the debugging personnel through four indicator lights, which can speed up the work efficiency of the debugging personnel.

[0043] Furthermore, by analyzing the data transmitted between the emulator and the chip under test, the current status of the chip under test can be known in a timely manner, which can ensure the normal operation of the debugging program. Detecting the power-on status of the emulator and the chip board under test helps in problem analysis and further improves the efficiency of debugging work.

[0044] The specific debugging process of the simulation debugging system in this utility model is as follows:

[0045] S1. First, connect the emulator motherboard to the chip under test. Then, use the emulator status monitoring module to monitor the power-on status of the emulator motherboard, the startup status of the FPGA program, and the startup status of the emulator control program. Feed back the monitoring results to the information interaction module and the display module. If the monitoring results are abnormal, do not proceed to S2. Debug the emulator until the monitoring results are all normal.

[0046] Specifically, S1 includes the following process:

[0047] S11. First, connect the emulator motherboard to the chip under test;

[0048] S12: The emulator control program reads the voltage value of the power supply pin connected to the microcontroller on the emulator motherboard. If the voltage value is within the set voltage value range, the emulator motherboard is considered to be powered on normally, and the PWOER indicator on the display module lights up red; otherwise, the emulator motherboard is considered to be powered on abnormally, the PWOER indicator on the display module does not light up, and the information of abnormal power supply of the emulator motherboard is fed back to the information interaction module. The emulator motherboard will not perform any further status monitoring work until the debugging personnel debug the emulator motherboard and determine that the emulator motherboard is powered on normally before proceeding to S13.

[0049] S13. Then, the simulator status monitoring module monitors the startup status of the simulator control program. If the simulator control program can start normally, the PWOER indicator light changes from red to yellow; otherwise, the PWOER indicator light remains red, and the information that the simulator control program cannot start normally is fed back to the information interaction module. The simulator motherboard will not perform any further status monitoring until the debugging personnel debug the simulator motherboard and determine that the simulator control program can start normally before proceeding to S14.

[0050] Specifically, the method for determining whether the simulator control program can start normally is as follows:

[0051] The following two operations will only be performed if the simulator control program starts normally: 1. Generate a startup log through the information interaction module; 2. Output error information about the monitoring results in the startup log; therefore, the simulator control program can be judged to have started normally by the above two operations.

[0052] S14. The emulator status monitoring module monitors the FPGA program startup status. After the FPGA program starts on the emulator, the FPGA sends status flag information to the emulator control program. The emulator control program uses the status flag information to determine whether the FPGA program has started normally. If the FPGA program starts normally, the color of the PWOER indicator light changes from yellow to green. If the PWOER light remains green, it indicates that the emulator motherboard is working normally. If the FPGA program fails to start, the color of the PWOER indicator light remains unchanged, and the information about the FPGA program startup failure is fed back to the information interaction module. The process will not proceed to S2 until the FPGA program can start normally after debugging. During chip debugging, if the PWOER indicator light illuminates a different color or does not illuminate, the emulator motherboard needs to be powered on again.

[0053] S2. Use the JTAG interface status monitoring module to monitor the power-on status of the chip board under test, the data transmission status of the JTAG interface, and the abnormal status of JTAG data. Feed back the monitoring results obtained in S2 to the information interaction module and the display module. If the monitoring results obtained in S2 are abnormal, do not proceed to S3. Debug the emulator motherboard and the chip under test until the monitoring results are all normal.

[0054] Specifically, S2 includes the following process:

[0055] S21. The JTAG interface status monitoring module monitors the power-on status of the chip board under test. The emulator control program checks whether the PD voltage in the JTAG pin is 3.3V. If the PD voltage is 3.3V, it is determined that the chip board under test can power on normally, and the STATE indicator on the display module will light up green. If the PD voltage is not 3.3V, it is determined that the chip board under test cannot power on normally, and the STATE indicator on the display module will light up yellow. The information that the chip board under test cannot power on normally is fed back to the information interaction module. The program will not enter S22 until the chip board under test is debugged and can power on normally.

[0056] S22. Use the JTAG interface status monitoring module to monitor the JTAG interface data transmission function. During monitoring, the emulator motherboard transmits data with the chip under test through the JTAG interface. During data transmission, the emulator control program will make the STATE indicator light flash at a set frequency, indicating that data is being transmitted normally. When the STATE indicator light is always green, it indicates that the JTAG interface data transmission is abnormal. The abnormal JTAG interface information is fed back to the information interaction module, and the program will not enter S23 until the JTAG interface is debugged and the JTAG interface data transmission is normal.

[0057] S23. Use the JTAG interface status monitoring module to monitor the data on TDO. If the data on TDO is normal, the STATE indicator light will not light up. If the data on TDO has an abnormal format or is all zeros or all 1s, it is determined that the JTAG data is abnormal. At this time, the STATE indicator light will light up red to prompt the tester to debug the abnormality. The information of the JTAG data abnormality will be fed back to the information interaction module, and it will not enter S3 until the data on TDO is normal after the JTAG interface has been debugged.

[0058] S3. Use the chip status monitoring module to monitor and determine the status of the chip program of the chip under test, and feed back the monitoring results obtained in S3 to the information interaction module and the display module.

[0059] Specifically, S3 includes the following process:

[0060] S31. The emulator motherboard reads the status register of the chip under test and determines whether the chip program is in normal operation by using the valid bits. If the chip program is in normal operation, the emulator control program will make the RUN indicator on the display module light up green.

[0061] S32. The emulator motherboard reads the status register of the chip under test and determines whether the chip under test is in a software breakpoint pause state by using the valid bits of the data. If the chip program is in a software breakpoint pause state, the emulator control program will make the RUN indicator light yellow.

[0062] S33. The emulator motherboard reads the status register of the chip under test and performs logical checks by verifying whether the valid bits of the data are normal values, or all zeros or all one bits, to determine if the chip program is in an abnormal state. If the chip program is in an abnormal state, the emulator control program will control the RUN indicator light on the display module to turn it red, and feed back the information that the chip program is in an abnormal state to the information interaction module. A red RUN indicator light can alert the debugging personnel that there is an abnormal situation in the program.

[0063] S4. Use the error status analysis module to monitor the operation of the ET component, the startup status of the chip register, and the program address access status, and feed back the monitoring results obtained by S4 to the information interaction module and the display module.

[0064] Specifically, S4 includes the following process:

[0065] S41. The emulator motherboard sends link scan data to the ET component of the chip under test and determines whether the ET component of the chip under test is operating normally by the return value of the data on TDO. If the ET component is operating normally, the ERROR indicator on the display module will light up green; otherwise, it is determined that the ET component is not operating normally, the ERROR indicator will light up red, and the information that the ET component is not operating normally will be fed back to the information interaction module.

[0066] S42. Some registers of the chip are read-only and cannot be written, and the registers have fixed values. For example, the chip's ID (Identity Document) register, CSR (Control Status Register) register, etc. The test chip determines whether the corresponding register of the chip under test can start normally based on the corresponding register value. If the corresponding register of the chip under test can start normally, the ERROR indicator light will be yellow; otherwise, the ERROR indicator light will be red, and the information that the corresponding register of the chip under test cannot start normally will be fed back to the information interaction module.

[0067] S43. Some memory spaces of the chip require initialization. After power-on, some memory spaces need to have their register values ​​configured before they can be used. This process is collectively called initialization. When the emulator accesses these memory spaces, if initialization is not completed, the data displayed on TDO will be all zeros or all 1s. For example, DDR (Double Data Rate Synchronous Dynamic Random Access Memory) and EMIF (External Memory Interface) cannot be accessed by the program before initialization is complete. The emulator motherboard determines the program's address access status based on the data return value on TDO. When the data on TDO is all zeros or all 1s, it indicates that the program has accessed an illegal memory space (i.e., an uninitialized memory space). At this time, the ERROR indicator light turns red, and the information that the program accessed an illegal memory space is fed back to the information interaction module to prompt the tester that a debugging anomaly has occurred, requiring a power-on reprogramming of both the emulator motherboard and the chip under test.

[0068] S5. After receiving the above feedback information, the information interaction module prints the error information about the monitoring results in the startup log so that the debugging personnel can debug the emulator motherboard and the chip under test according to the startup log file.

[0069] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Furthermore, the technical solutions of the various embodiments of this utility model can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope claimed by this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A simulation debugging system with fault diagnosis capability, characterized in that, This includes the emulator motherboard and the emulator status monitoring module, chip status monitoring module, interface status monitoring module, error status analysis module, and display module integrated on the emulator motherboard: The emulator status monitoring module, chip status monitoring module, interface status monitoring module, and error status analysis module are connected to the display module, respectively; the chip status monitoring module, interface status monitoring module, and error status analysis module are connected to the chip under test, respectively; and the emulator status monitoring module is connected to the emulator motherboard.

2. The simulation debugging system according to claim 1, characterized in that, The interface status monitoring module is a JTAG interface status monitoring module, which is connected to the JTAG interface of the chip under test.

3. The simulation debugging system according to claim 1, characterized in that, It also includes an information interaction module, which is connected to the simulator status monitoring module, the chip status monitoring module, the interface status monitoring module, and the error status analysis module, respectively.

4. The simulation debugging system according to claim 1, characterized in that, The display module includes four different tri-color indicator lights: POWER indicator light, STATE indicator light, RUN indicator light, and ERROR indicator light. The POWER indicator light is connected to the emulator status monitoring module; the RUN indicator light is connected to the chip status monitoring module; the STATE indicator light is connected to the JTAG interface status monitoring module; and the ERROR indicator light is connected to the error status analysis module.

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