Power amplifier and radio frequency front-end module

Abstract

The utility model discloses a power amplifier and a radio frequency front-end module, and the power amplifier comprises an amplification circuit which comprises a first amplification unit and a second amplification unit; the first bias circuit comprises a first bias unit, a first capacitor and a second capacitor, the first capacitor is connected between the third end of the first bias unit and the first signal input end, and the second capacitor is connected between the first end of the first bias unit and the output end of the first amplification unit; the second bias circuit comprises a second bias unit, a third capacitor and a fourth capacitor, the third capacitor is connected between the third end of the second bias unit and the output end of the first amplification unit, and the fourth capacitor is connected between the first end of the second bias unit and the output end of the second amplification unit. According to the power amplifier, not only can the linearity of the power amplifier be optimized, but also the durability can be ensured not to be deteriorated, so that the power additional efficiency of the power amplifier is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a power amplifier and a radio frequency front-end module. Background Technology

[0002] In radio frequency (RF) technology, to ensure that the power amplifier in the RF front-end module amplifies RF signals without distortion, a bias circuit is typically installed at the input of the amplifier circuit. In related technologies, increasing the bias current input from the bias circuit to the amplifier circuit can improve the gain of the power amplifier, thereby improving its linearity. However, increasing the bias current can easily lead to a decrease in the power-added efficiency and a deterioration in the power amplifier's durability. Utility Model Content

[0003] This application provides a power amplifier and an RF front-end module, which solves the problems in related technologies where improving the linearity of the power amplifier leads to lower power-added efficiency and reduced durability at high power.

[0004] In a first aspect, this application provides a power amplifier having a first signal input terminal and a first signal output terminal. The power amplifier includes: an amplification circuit comprising a first amplification unit and a second amplification unit, the first amplification unit being connected between the first signal input terminal and the second amplification unit, and the second amplification unit being connected between the first amplification unit and the first signal output terminal; and a first bias circuit comprising a first bias unit, a first capacitor, and a second capacitor, a first terminal of the first bias unit being connected to a first bias power supply terminal, a second terminal of the first bias unit being connected to a first bias power supply terminal, and a third terminal of the first bias unit being connected to the input terminal of the first amplification unit. A capacitor is connected between the third terminal of the first bias unit and the first signal input terminal, and a second capacitor is connected between the first terminal of the first bias unit and the output terminal of the first amplification unit; a second bias circuit includes a second bias unit, a third capacitor, and a fourth capacitor. The first terminal of the second bias unit is connected to the second bias power supply terminal, the second terminal of the second bias unit is connected to the second bias power supply terminal, the third terminal of the second bias unit is connected to the input terminal of the second amplification unit, the third capacitor is connected between the third terminal of the second bias unit and the output terminal of the first amplification unit, and the fourth capacitor is connected between the first terminal of the second bias unit and the output terminal of the second amplification unit.

[0005] The aforementioned power amplifier, by incorporating a first capacitor and a second capacitor in the first bias circuit, reduces the bias current input from the first bias circuit to the first amplification unit due to their small capacitance values, thereby reducing the output current of the first amplification unit at high power. Similarly, by incorporating a third capacitor and a fourth capacitor in the second bias circuit, the bias current input from the second bias circuit to the second amplification unit, also with smaller capacitance values, reduces the output current of the second amplification unit at high power. Therefore, the amplitude and phase distortion of the power amplifier can be improved, optimizing its linearity and ensuring its durability is not compromised, thus enhancing its power-added efficiency.

[0006] Secondly, this application also provides a power amplifier having a first signal input terminal and a first signal output terminal, the power amplifier comprising:

[0007] An amplifier circuit, the amplifier circuit including a first amplification unit, the first amplification unit being connected between the first signal input terminal and the first signal output terminal;

[0008] The first bias circuit includes a first bias unit, a first capacitor, and a second capacitor. A first terminal of the first bias unit is connected to a first bias power supply terminal, a second terminal of the first bias unit is connected to a first bias power supply terminal, a third terminal of the first bias unit is connected to the input terminal of the first amplification unit, the first capacitor is connected between the third terminal of the first bias unit and the first signal input terminal, and the second capacitor is connected between the first terminal of the first bias unit and the output terminal of the first amplification unit.

[0009] The aforementioned power amplifier, by setting a first capacitor and a second capacitor in the first bias circuit, can reduce the bias current input from the first bias circuit to the first amplification unit due to the small capacitance values ​​of the first and second capacitors, thereby reducing the output current of the first amplification unit at high power. Therefore, it can improve the amplitude distortion and phase distortion of the power amplifier, not only optimizing the linearity of the power amplifier, but also ensuring that the durability is not deteriorated, thereby improving the power-added efficiency of the power amplifier.

[0010] Thirdly, this application also provides a power amplifier having a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. The power amplifier includes: a first amplification branch connected between the first signal input terminal and the first signal output terminal, and a second amplification branch connected between the second signal input terminal and the second signal output terminal; the first amplification branch includes a cascaded first amplification unit and a second amplification unit; the second amplification branch includes a cascaded third amplification unit and a fourth amplification unit.

[0011] A first bias circuit includes a first bias unit, a first capacitor, and a second capacitor. A first terminal of the first bias unit is connected to a first bias power supply terminal, a second terminal of the first bias unit is connected to a first bias power supply terminal, a third terminal of the first bias unit is connected to the input terminal of the first amplification unit, the first capacitor is connected between the third terminal of the first bias unit and the second signal input terminal, and the second capacitor is connected between the first terminal of the first bias unit and the output terminal of the third amplification unit.

[0012] The second bias circuit includes a second bias unit, a third capacitor, and a fourth capacitor. The first terminal of the second bias unit is connected to the second bias power supply terminal, the second terminal of the second bias unit is connected to the second bias power supply terminal, the third terminal of the second bias unit is connected to the input terminal of the second amplification unit, the third capacitor is connected between the third terminal of the second bias unit and the output terminal of the third amplification unit, and the fourth capacitor is connected between the first terminal of the second bias unit and the output terminal of the fourth amplification unit.

[0013] The third bias circuit includes a third bias unit, a fifth capacitor, and a sixth capacitor. The first terminal of the third bias unit is connected to the third bias power supply terminal, the second terminal of the third bias unit is connected to the third bias power supply terminal, the third terminal of the third bias unit is connected to the input terminal of the third amplification unit, the fifth capacitor is connected between the third terminal of the third bias unit and the first signal input terminal, and the sixth capacitor is connected between the first terminal of the third bias unit and the output terminal of the first amplification unit.

[0014] The fourth bias circuit includes a fourth bias unit, a seventh capacitor, and an eighth capacitor. The first terminal of the fourth bias unit is connected to the fourth bias power supply terminal, the second terminal of the fourth bias unit is connected to the fourth bias power supply terminal, the third terminal of the fourth bias unit is connected to the input terminal of the fourth amplification unit, the seventh capacitor is connected between the third terminal of the fourth bias unit and the output terminal of the first amplification unit, and the eighth capacitor is connected between the first terminal of the fourth bias unit and the output terminal of the second amplification unit.

[0015] The aforementioned power amplifier, by incorporating a first capacitor and a second capacitor in the first bias circuit, reduces the bias current input from the first bias circuit to the first amplification unit due to their small capacitance values, thereby reducing the output current of the first amplification unit at high power. Similarly, by incorporating a third capacitor and a fourth capacitor in the second bias circuit, the small capacitance values ​​of the third and fourth capacitors further reduce the bias current input from the second bias circuit to the second amplification unit, thus reducing the output current of the second amplification unit at high power. Finally, by incorporating a fifth capacitor and a sixth capacitor in the third bias circuit, the small capacitance values ​​of the fifth and sixth capacitors further reduce the bias current input from the second bias circuit to the second amplification unit, thereby reducing the output current of the second amplification unit at high power. The smaller capacitance value of the capacitor reduces the bias current input from the third bias circuit to the third amplification unit, thereby reducing the output current of the third amplification unit at high power. Similarly, by including the seventh and eighth capacitors in the fourth bias circuit, their smaller capacitance values ​​further reduce the bias current input from the fourth bias circuit to the fourth amplification unit, thus reducing the output current of the fourth amplification unit at high power. Therefore, the amplitude and phase distortion of the power amplifier can be improved, optimizing its linearity and ensuring its durability is not compromised, thereby increasing the power-added efficiency of the power amplifier.

[0016] Fourthly, this application also provides a power amplifier having a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal, wherein the power amplifier includes:

[0017] An amplifier circuit, comprising a first amplification unit and a third amplification unit, wherein the first amplification unit is connected between the first signal input terminal and the first signal output terminal, and the third amplification unit is connected between the second signal input terminal and the second signal output terminal;

[0018] A first bias circuit includes a first bias unit, a first capacitor, and a second capacitor. A first terminal of the first bias unit is connected to a first bias power supply terminal, a second terminal of the first bias unit is connected to a first bias power supply terminal, a third terminal of the first bias unit is connected to the input terminal of the first amplification unit, the first capacitor is connected between the third terminal of the first bias unit and the second signal input terminal, and the second capacitor is connected between the first terminal of the first bias unit and the output terminal of the third amplification unit.

[0019] The third bias circuit includes a third bias unit, a fifth capacitor, and a sixth capacitor. The first terminal of the third bias unit is connected to the third bias power supply terminal, the second terminal of the third bias unit is connected to the third bias power supply terminal, the third terminal of the third bias unit is connected to the input terminal of the third amplification unit, the fifth capacitor is connected between the third terminal of the third bias unit and the first signal input terminal, and the sixth capacitor is connected between the first terminal of the third bias unit and the output terminal of the first amplification unit.

[0020] The aforementioned power amplifier, by incorporating a first capacitor and a second capacitor in the first bias circuit, reduces the bias current input from the first bias circuit to the first amplification unit due to their small capacitance values, thereby reducing the output current of the first amplification unit at high power. Similarly, by incorporating a fifth capacitor and a sixth capacitor in the third bias circuit, the bias current input from the third bias circuit to the third amplification unit, also with smaller capacitance values, reduces the output current of the third amplification unit at high power. Therefore, the amplitude and phase distortion of the power amplifier can be improved, optimizing its linearity and ensuring its durability is not compromised, thus enhancing its power-added efficiency.

[0021] Fifthly, this application also provides a radio frequency front-end module, which includes the power amplifier described above. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit diagram of a power amplifier in related technologies;

[0024] Figure 2This is a schematic diagram of the circuit structure of a radio frequency front-end module provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the circuit structure of a power amplifier provided in an embodiment of this application;

[0026] Figure 4 This is a schematic curve showing the amplitude distortion level of the power amplifier provided by the prior art and the amplitude distortion level of the power amplifier provided in the embodiments of this application;

[0027] Figure 5 This is a schematic curve showing the phase distortion level of a power amplifier in the prior art and the phase distortion level of a power amplifier provided in the embodiments of this application;

[0028] Figure 6 This is a schematic curve showing the bias current output by the bias circuit in the prior art and the bias current output by the bias circuit provided in the embodiments of this application.

[0029] Figure 7 This is a schematic graph showing the power-added efficiency of power amplifiers in the prior art and the power-added efficiency of power amplifiers provided in the embodiments of this application.

[0030] Figure 8 This is a schematic graph showing the power-added efficiency of power amplifiers in the prior art and the power-added efficiency of power amplifiers provided in the embodiments of this application.

[0031] Figure 9 This is a schematic diagram of the circuit structure of another power amplifier provided in an embodiment of this application;

[0032] Figure 10 This is a schematic diagram of the circuit structure of another power amplifier provided in an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the circuit structure of another power amplifier provided in an embodiment of this application;

[0034] Figure 12 This is a schematic diagram of the circuit structure of another power amplifier provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0037] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0038] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0040] Please see Figure 1 , Figure 1 This is a circuit diagram of a power amplifier in related technologies. For example... Figure 1 As shown, the relevant technology uses capacitor C0 to collect the feedback input RF signal and generates a corresponding bias current input to the amplifier circuit based on the input RF signal. In high-power scenarios, increasing the bias current input from the bias circuit to the amplifier circuit can improve the gain of the amplifier circuit, enhance the gain compression characteristics of the power amplifier, and thus improve the linearity of the power amplifier. However, increasing the bias current input from the bias circuit to the amplifier circuit can easily lead to lower power-added efficiency and reduced durability of the amplifier circuit at high power. It is understandable that when the bias current input from the bias circuit to the amplifier circuit increases, the conduction angle of the amplifier circuit increases, causing the overall current waveform of the amplifier circuit to rise, thus resulting in lower power-added efficiency of the amplifier circuit at high power. Simultaneously, when the bias current input from the bias circuit to the amplifier circuit increases, the output current of the amplifier circuit increases. In scenarios such as high and low temperatures, load mismatch, and input power over-push, the transistors in the amplifier circuit (e.g., heterojunction bipolar transistors (HBTs)) are prone to failure due to excessively high output current, reducing the durability of the amplifier circuit.

[0041] Therefore, this application provides a power amplifier and an RF front-end module. By setting a first capacitor and a second capacitor in the first bias circuit, the bias current input from the first bias circuit to the first amplification unit can be reduced due to their small capacitance values, thereby reducing the output current of the first amplification unit at high power. Similarly, by setting a third capacitor and a fourth capacitor in the second bias circuit, the bias current input from the second bias circuit to the second amplification unit can be reduced due to their small capacitance values, thereby reducing the output current of the second amplification unit at high power. Therefore, the amplitude distortion and phase distortion of the power amplifier can be improved, optimizing the linearity of the power amplifier and ensuring that ruggedness is not deteriorated, thus improving the power-added efficiency (PAE) of the power amplifier. The structure of the power amplifier will be described in detail below.

[0042] Please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a radio frequency front-end module 10 provided in an embodiment of this application, as shown below. Figure 2 As shown, the radio frequency front-end module 10 may include a power amplifier 100.

[0043] It should be noted that the RF front-end module 10 is a component that integrates two or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers into a single independent module, thereby improving integration and hardware performance, and miniaturizing the size. In this embodiment, the RF front-end module 10 supports carrier aggregation, dual connectivity, and multiple-input multiple-output (MIMO).

[0044] Specifically, the radio frequency front-end module 10 can be applied to communication devices such as smartphones, tablets, smartwatches, and routers. These communication devices can include electronic devices such as smartphones, tablets, and smartwatches, as well as communication devices such as base stations and NFC (Near Field Communication) devices. The radio frequency front-end module 10 can receive or transmit radio frequency signals through the antenna in the communication device, and the power amplifier 100 is used to amplify the received or transmitted radio frequency signals.

[0045] Please see Figure 3 , Figure 3 This is a circuit structure diagram of a power amplifier 100 provided in an embodiment of this application, as shown below. Figure 3As shown, the power amplifier 100 may include a first signal input terminal 101, a first signal output terminal 102, an amplification circuit 20, a first bias circuit 30, and a second bias circuit 40.

[0046] like Figure 3 As shown, the amplifier circuit 20 includes a first amplifier unit 201 and a second amplifier unit 202. The first amplifier unit 201 is connected between the first signal input terminal 101 and the second amplifier unit 202, and the second amplifier unit 202 is connected between the first amplifier unit 201 and the first signal output terminal 102.

[0047] In at least one embodiment, the first amplification unit 201 and the second amplification unit 202 can be any two stages of amplification circuits in the amplifier circuit 20. For example, the first amplification unit 201 is a first-stage amplifier circuit, the second amplification unit 202 is a second-stage amplifier circuit, the input terminal of the first amplification unit 201 is connected to the first signal input terminal 101, the output terminal of the first amplification unit 201 is connected to the input terminal of the second amplification unit 202, and the output terminal of the second amplification unit 202 is connected to the first signal output terminal 102.

[0048] The first bias circuit 30 includes a first bias unit 301, a first capacitor C1, and a second capacitor C2. The first terminal of the first bias unit 301 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias unit 301 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias unit 301 is connected to the input terminal of the first amplification unit 201. The first capacitor C1 is connected between the third terminal of the first bias unit 301 and the first signal input terminal 101, and the second capacitor C2 is connected between the first terminal of the first bias unit 301 and the output terminal of the first amplification unit 201. The first bias unit 301 is used to input bias current to the first amplification unit 201.

[0049] By incorporating a first capacitor C1 and a second capacitor C2 in the first bias circuit 30, the relatively small capacitance values ​​of C1 and C2 reduce the bias current input from the first bias circuit 30 to the first amplification unit 201, thereby reducing the output current of the first amplification unit 201 at high power. Therefore, the input-output amplitude modulation comparison (AM-AM) and the input amplitude modulation-output phase modulation comparison (AM-PM) of the power amplifier 100 can be improved. This not only optimizes the linearity of the power amplifier 100 but also ensures that its robustness is not compromised, thereby improving the power-added efficiency of the power amplifier 100. It should be noted that the input-output amplitude modulation comparison is typically used to evaluate the degree of amplitude distortion, while the input amplitude modulation-output phase modulation comparison is typically used to evaluate the degree of phase distortion.

[0050] The second bias circuit 40 includes a second bias unit 401, a third capacitor C3, and a fourth capacitor C4. The first terminal of the second bias unit 401 is connected to the second bias power supply terminal Vreg2, the second terminal of the second bias unit 404 is connected to the second bias power supply terminal Vbat2, and the third terminal of the second bias unit 404 is connected to the input terminal of the second amplification unit 202. The third capacitor C3 is connected between the third terminal of the second bias unit 401 and the output terminal of the first amplification unit 201, and the fourth capacitor C4 is connected between the first terminal of the second bias unit 401 and the output terminal of the second amplification unit 202. The second bias unit 401 is used to input bias current to the second amplification unit 202.

[0051] By setting a third capacitor C3 and a fourth capacitor C4 in the second bias circuit 40, the bias current input from the second bias circuit 40 to the second amplification unit 202 can be reduced due to their small capacitance values. This reduces the output current of the second amplification unit 202 at high power, thereby improving the amplitude and phase distortion of the power amplifier 100. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not compromised, thus improving the power-added efficiency of the power amplifier 100.

[0052] In some embodiments, the capacitance value of the first capacitor C1 is in the range of [0pF, 4pF]; the capacitance value of the second capacitor C2 is in the range of [0pF, 1pF]. The capacitance value of the first capacitor C1 is positively correlated with the magnitude of the radio frequency signal fed back by the first capacitor C1. The capacitance value of the second capacitor C2 is positively correlated with the magnitude of the radio frequency signal fed back by the second capacitor C2. For example, the capacitance value of the first capacitor C1 is 2pF, and the capacitance value of the second capacitor C2 is 0.5pF.

[0053] In the above embodiments, after adding the second capacitor C2, by setting a first capacitor C1 with a smaller capacitance value, and ensuring that the capacitance value of the first capacitor C1 is positively correlated with the magnitude of the radio frequency signal fed back by the first capacitor C1, the capacitance value of the first capacitor C1 can be reduced while maintaining the linearity of the first amplification unit 201. This reduces the bias current input from the first bias circuit 301 to the first amplification unit 201, thereby improving the durability and power-added efficiency of the power amplifier 100. By setting a second capacitor C2 with a smaller capacitance value, and ensuring that the capacitance value of the second capacitor C2 is positively correlated with the magnitude of the radio frequency signal fed back by the second capacitor C2, the amplitude distortion and phase distortion of the power amplifier 100 can be improved using the second capacitor C2, thereby improving the linearity of the power amplifier 100.

[0054] Please see Figure 4 , Figure 4 This is a schematic graph comparing the amplitude distortion of power amplifiers provided by existing technologies with the amplitude distortion of power amplifiers provided in the embodiments of this application. Figure 4 As shown, the horizontal axis represents output power, and the vertical axis represents amplitude distortion. Curve 1 represents the amplitude distortion of a power amplifier provided by the prior art, and curve 2 represents the amplitude distortion of a power amplifier provided by the embodiments of this application. Figure 3 The power amplifier in this application is equipped with a second capacitor C2, which increases the gain at high power. The second capacitor C2 can be used to improve the amplitude distortion of the power amplifier 100, thereby improving the linearity of the power amplifier 100.

[0055] Please see Figure 5 , Figure 5 This is a schematic graph showing the phase distortion levels of power amplifiers in the prior art compared to those of the power amplifiers provided in the embodiments of this application. Figure 5 As shown, the horizontal axis represents the output power, and the vertical axis represents the phase distortion level. Curve 1 represents the phase distortion level of the power amplifier provided by the prior art, and curve 2 represents the phase distortion level of the power amplifier provided by the embodiment of this application. Figure 3The power amplifier in this application is provided with a second capacitor C2, which can improve the phase distortion of the power amplifier 100. Compared with the power amplifier in the prior art, the phase distortion of the power amplifier 100 provided in this application embodiment is reduced from 3° to 2°, which can effectively improve the linearity of the power amplifier 100.

[0056] Please see Figures 6 to 8 , Figure 6 This is a schematic graph showing the bias current output by the bias circuit in the prior art and the bias current output by the bias circuit provided in the embodiments of this application. Figure 7 This is a schematic graph showing the power-added efficiency of power amplifiers in the prior art and the power-added efficiency of power amplifiers provided in the embodiments of this application. Figure 8 This is a schematic graph showing the power-added efficiency of power amplifiers in the prior art and the power-added efficiency of power amplifiers provided in the embodiments of this application.

[0057] like Figure 6 As shown, the horizontal axis represents time, and the vertical axis represents output current. Curve 1 represents the bias current output by the bias circuit in the prior art, and curve 2 represents the bias current output by the bias circuit provided in the embodiment of this application. Figure 3 In this application, after adding a second capacitor C2, the power amplifier can reduce the capacitance value of the first capacitor C1 by setting a smaller capacitance value, while keeping the linearity of the power amplifier unchanged. This can reduce the bias current input from the first bias circuit 301 to the first amplification unit 201, thereby improving the durability of the power amplifier 100 and increasing the power-added efficiency of the power amplifier 100.

[0058] like Figure 7 As shown, the horizontal axis represents output power, and the vertical axis represents power-added efficiency. Curve 3 represents the power-added efficiency of a power amplifier in the prior art, and curve 4 represents the power-added efficiency of a power amplifier provided in the embodiments of this application. Figure 3 In this application, after adding a second capacitor C2, the power amplifier can reduce the capacitance value of a first capacitor C1 with a smaller capacitance value by setting the first capacitor C1 to keep the linearity of the power amplifier unchanged. Compared with the power amplifier in the prior art, this can improve the power-added efficiency of the power amplifier 100.

[0059] like Figure 8 As shown, the horizontal axis represents output power, and the vertical axis represents power-added efficiency. Curve 5 is a curve of the power-added efficiency of a power amplifier in the prior art. Curve 6 is a curve of the power-added efficiency of a power amplifier provided in the embodiments of this application, and in conjunction with... Figure 3In this application, after adding a second capacitor C2, the power amplifier can reduce the capacitance value of the first capacitor C1 by setting a smaller capacitance value, while keeping the linearity of the power amplifier unchanged. Compared with the power amplifier in the prior art, the power amplifier in this application improves the power-added efficiency of the power amplifier 100 at high power as the output power increases, thereby effectively improving the power-added efficiency of the power amplifier 100.

[0060] In some embodiments, the capacitance value of the third capacitor C3 is in the range of [1pF, 4pF]; the capacitance value of the fourth capacitor C4 is in the range of [0.5pF, 1pF]. The capacitance value of the third capacitor C3 is positively correlated with the magnitude of the radio frequency signal fed back by the third capacitor C3. The capacitance value of the fourth capacitor C4 is positively correlated with the magnitude of the radio frequency signal fed back by the fourth capacitor C4. For example, the capacitance value of the third capacitor C3 is 2pF, and the capacitance value of the fourth capacitor C4 is 0.8pF.

[0061] In other embodiments, the capacitance value of the third capacitor C3 is in the range of [1pF, 2pF].

[0062] In the above embodiments, after adding a fourth capacitor C4, by setting a third capacitor C3 with a smaller capacitance value, and ensuring that the capacitance value of the third capacitor C3 is positively correlated with the magnitude of the radio frequency signal fed back by the third capacitor C3, the capacitance value of the third capacitor C3 can be reduced while maintaining the linearity of the second amplification unit 202. This reduces the bias current input from the second bias circuit 401 to the second amplification unit 202, thereby improving the durability and power-added efficiency of the power amplifier 100. By setting a fourth capacitor C4 with a smaller capacitance value, and ensuring that the capacitance value of the fourth capacitor C4 is positively correlated with the magnitude of the radio frequency signal fed back by the fourth capacitor C4, the bias current input from the second bias circuit 401 to the second amplification unit 202 can be reduced using the fourth capacitor C4. This improves the amplitude and phase distortion of the power amplifier 100, thereby improving the linearity of the power amplifier 100.

[0063] In some embodiments, such as Figure 3 As shown, the first bias unit 301 includes a first bias transistor P1. The first terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias transistor P1 is connected to the input terminal of the first amplification unit 201.

[0064] The second bias unit 401 includes a second bias transistor P2. The first terminal of the second bias transistor P2 is connected to the second bias power supply terminal Vreg2, the second terminal of the second bias transistor P2 is connected to the second bias power supply terminal Vbat2, and the third terminal of the second bias transistor P2 is connected to the input terminal of the second amplification unit 202.

[0065] In some embodiments, the first bias transistor P1 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first terminal of the first bias transistor P1 is the gate, the second terminal is the drain or source, and the third terminal is the source or drain. By configuring the first bias transistor P1 as a MOSFET, the logic controlling the first bias unit 30 can be simplified, improving the operating efficiency of the first bias unit 30 and reducing costs, due to the simple driving circuit and low noise characteristics of MOSFETs.

[0066] In other embodiments, the first bias transistor P1 is a bipolar junction transistor (BJT), with its first terminal as the base, its second terminal as the collector, and its third terminal as the emitter; or, the first terminal of the first bias transistor P1 is the base, its second terminal as the emitter, and its third terminal as the collector. By configuring the first bias transistor P1 as a BJT, the low input impedance of the BJT allows it to withstand a larger current, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0067] In some embodiments, the second bias transistor P2 is a metal-oxide-semiconductor field-effect transistor (MOSFET), with its first terminal serving as the gate, its second terminal as the drain or source, and its third terminal as the source or drain. By configuring the second bias transistor P2 as a MOSFET, the logic controlling the second bias unit 40 can be simplified, improving its efficiency and reducing its cost, due to the MOSFET's simple driving circuitry and low noise characteristics.

[0068] In other embodiments, the second bias transistor P2 is a bipolar junction transistor (BJT), with its first terminal as the base, its second terminal as the collector, and its third terminal as the emitter; or, the first terminal of the second bias transistor P2 is the base, its second terminal as the emitter, and its third terminal as the collector. By configuring the second bias transistor P2 as a BJT, the low input impedance of the BJT allows it to withstand a larger current, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0069] In some embodiments, such as Figure 3 As shown, the first amplification unit 201 includes a first amplification transistor Q1 and a first inductor L1, and the second amplification unit 202 includes a second amplification transistor Q2 and a second inductor L2.

[0070] The first terminal of the first amplifying transistor Q1 is connected to the first signal input terminal 101, the second terminal of the first amplifying transistor Q1 is grounded, the third terminal of the first amplifying transistor Q1 is connected to the first power supply terminal Vcc1 through the first inductor L1, and the third terminal of the first amplifying transistor Q1 is the output terminal of the first amplifying unit 201.

[0071] The first terminal of the second amplifying transistor Q2 is connected to the third terminal of the first amplifying transistor Q1. The second terminal of the second amplifying transistor Q2 is grounded. The third terminal of the second amplifying transistor Q2 is connected to the second power supply terminal Vcc2 through the second inductor L2. The third terminal of the second amplifying transistor Q2 is the output terminal of the second amplifying unit 202.

[0072] For example, the first power supply terminal Vcc1 and the second power supply terminal Vcc2 can be voltage terminals or current terminals. The first power supply terminal Vcc1 and the second power supply terminal Vcc2 can be two independent power supply terminals or the same power supply terminal. The first power supply terminal Vcc1 provides current to the third terminal of the first amplifying transistor Q1 through the first inductor L1. The second power supply terminal Vcc2 provides current to the third terminal of the second amplifying transistor Q2 through the second inductor L2.

[0073] For example, the first amplifying transistor Q1 and the second amplifying transistor Q2 may include, but are not limited to, transistors, metal-oxide-semiconductor field-effect transistors, and insulated-gate bipolar transistors (IGBTs), etc. The first amplifying transistor Q1 amplifies the power of the radio frequency (RF) signal output from the first signal input terminal 101 and outputs the amplified RF signal to the second amplifying transistor Q2. The second amplifying transistor Q2 amplifies the power of the RF signal output from the first amplifying transistor Q1 and outputs the amplified RF signal to the first signal output terminal 102.

[0074] Please see Figure 9 , Figure 9 This is a schematic diagram of the circuit structure of another power amplifier 100 provided in an embodiment of this application, as shown below. Figure 9 As shown, the power amplifier 100 may include a first signal input terminal 101, a first signal output terminal 102, an amplifier circuit 20, and a first bias circuit 30.

[0075] like Figure 9 As shown, the amplifier circuit 20 includes a first amplification unit 201, which is connected between the first signal input terminal 101 and the first signal output terminal 102. The first amplification unit 201 can be any stage of the amplifier circuit 20; for example, it can be either a pre-amplifier or a post-amplifier in the amplifier circuit 20.

[0076] The first bias circuit 30 includes a first bias unit 301, a first capacitor C1, and a second capacitor C2. The first terminal of the first bias unit 301 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias unit 301 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias unit 301 is connected to the input terminal of the first amplification unit 201. The first capacitor C1 is connected between the third terminal of the first bias unit 301 and the first signal input terminal 101, and the second capacitor C2 is connected between the first terminal of the first bias unit 301 and the output terminal of the first amplification unit 201. The first bias unit 301 is used to input bias current to the first amplification unit 201.

[0077] By setting a first capacitor C1 and a second capacitor C2 in the first bias circuit 30, the bias current input from the first bias circuit 30 to the first amplification unit 201 can be reduced due to the small capacitance values ​​of the first capacitor C1 and the second capacitor C2. This reduces the output current of the first amplification unit 201 at high power. Therefore, the amplitude distortion and phase distortion of the power amplifier 100 can be improved. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thereby improving the power-added efficiency of the power amplifier 100.

[0078] In some embodiments, such as Figure 9 As shown, the first bias unit 301 includes a first bias transistor P1. The first terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias transistor P1 is connected to the input terminal of the first amplification unit 201.

[0079] In some embodiments, the first bias transistor P1 is a metal-oxide-semiconductor field-effect transistor (MOSFET), with its first terminal serving as the gate, its second terminal as the drain or source, and its third terminal as the source or drain. By configuring the first bias transistor P1 as a MOSFET, the logic controlling the first bias unit 30 can be simplified, improving its efficiency and reducing its cost, due to the MOSFET's simple driving circuitry and low noise characteristics.

[0080] In other embodiments, the first bias transistor P1 is a bipolar junction transistor (BJT), with its first terminal as the base, its second terminal as the collector, and its third terminal as the emitter; or, the first terminal of the first bias transistor P1 is the base, its second terminal as the emitter, and its third terminal as the collector. By configuring the first bias transistor P1 as a BJT, the low input impedance of the BJT allows it to withstand a larger current, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0081] In some embodiments, such as Figure 9 As shown, the first amplification unit 201 includes a first amplification transistor Q1 and a first inductor L1.

[0082] For example, the first amplifying transistor Q1 may include, but is not limited to, a transistor, a field-effect transistor, and an insulated-gate bipolar transistor, etc. The first amplifying transistor Q1 is used to amplify the power of the radio frequency signal output from the first signal input terminal 101 and output the amplified radio frequency signal to the first signal output terminal 102. The following description will use a transistor as the first amplifying transistor Q1.

[0083] like Figure 9 As shown, the base of the first amplifying transistor Q1 is connected to the first signal input terminal 101, the emitter of the first amplifying transistor Q1 is grounded, the collector of the first amplifying transistor Q1 is connected to the first power supply terminal Vcc1 through the first inductor L1, and the collector of the first amplifying transistor Q1 is the output terminal of the first amplification unit 201.

[0084] For example, the first power supply terminal Vcc1 can be a voltage terminal or a current terminal. The first power supply terminal Vcc1 provides collector current to the first amplifying transistor Q1 through the first inductor L1.

[0085] Please see Figure 10 , Figure 10 This is a schematic diagram of the circuit structure of another power amplifier 100 provided in an embodiment of this application, as shown below. Figure 10 As shown, the power amplifier 100 may include a first signal input terminal 101, a first signal output terminal 102, a second signal input terminal 103, a second signal output terminal 104, a first amplification branch 20 connected between the first signal input terminal 101 and the first signal output terminal 102, a second amplification branch 21 connected between the second signal input terminal 103 and the second signal output terminal 104, a first bias circuit 30, a second bias circuit 40, a third bias circuit 50, and a fourth bias circuit 60.

[0086] like Figure 10 As shown, the first amplification branch 20 includes a cascaded first amplification unit 201 and a second amplification unit 202. The first amplification unit 201 is connected between the first signal input terminal 101 and the second amplification unit 202, and the second amplification unit 202 is connected between the first amplification unit 201 and the first signal output terminal 102. The second amplification branch 21 includes a cascaded third amplification unit 211 and a fourth amplification unit 212. The third amplification unit 211 is connected between the second signal input terminal 103 and the fourth amplification unit 212, and the fourth amplification unit 212 is connected between the third amplification unit 211 and the second signal output terminal 104.

[0087] like Figure 10As shown, the first bias circuit 30 includes a first bias unit 301, a first capacitor C1, and a second capacitor C2. The first terminal of the first bias unit 301 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias unit 301 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias unit 301 is connected to the input terminal of the first amplification unit 201. The first capacitor C1 is connected between the third terminal of the first bias unit 301 and the second signal input terminal 103, and the second capacitor C2 is connected between the first terminal of the first bias unit 301 and the output terminal of the third amplification unit 211. The first bias unit 301 is used to input bias current to the first amplification unit 201.

[0088] By setting a first capacitor C1 and a second capacitor C2 in the first bias circuit 30, the bias current input from the first bias circuit 30 to the first amplification unit 201 can be reduced due to the small capacitance values ​​of the first capacitor C1 and the second capacitor C2. This reduces the output current of the first amplification unit 201 at high power. Therefore, the amplitude distortion and phase distortion of the power amplifier 100 can be improved. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thereby improving the power-added efficiency of the power amplifier 100.

[0089] like Figure 10 As shown, the second bias circuit 40 includes a second bias unit 401, a third capacitor C3, and a fourth capacitor C4. The first terminal of the second bias unit 401 is connected to the second bias power supply terminal Vreg2, the second terminal of the second bias unit 404 is connected to the second bias power supply terminal Vbat2, and the third terminal of the second bias unit 404 is connected to the input terminal of the second amplification unit 202. The third capacitor C3 is connected between the third terminal of the second bias unit 401 and the output terminal of the third amplification unit 211, and the fourth capacitor C4 is connected between the first terminal of the second bias unit 401 and the output terminal of the fourth amplification unit 212. The second bias unit 401 is used to input bias current to the second amplification unit 202.

[0090] By setting a third capacitor C3 and a fourth capacitor C4 in the second bias circuit 40, the bias current input from the second bias circuit 40 to the second amplification unit 202 can be reduced due to their small capacitance values. This reduces the output current of the second amplification unit 202 at high power, thereby improving the amplitude and phase distortion of the power amplifier 100. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not compromised, thus improving the power-added efficiency of the power amplifier 100.

[0091] like Figure 10As shown, the third bias circuit 50 includes a third bias unit 501, a fifth capacitor C5, and a sixth capacitor C6. The first end of the third bias unit 501 is connected to the third bias power supply terminal Vreg3, the second end of the third bias unit 501 is connected to the third bias power supply terminal Vbat3, the third end of the third bias unit 501 is connected to the input terminal of the third amplification unit 211, the fifth capacitor C5 is connected between the third end of the third bias unit 501 and the first signal input terminal 101, and the sixth capacitor C6 is connected between the first end of the third bias unit 501 and the output terminal of the first amplification unit 201.

[0092] By setting a fifth capacitor C5 and a sixth capacitor C6 in the third bias circuit 50, the bias current input from the third bias circuit 50 to the third amplification unit 211 can be reduced due to their small capacitance values. This reduces the output current of the third amplification unit 211 at high power, thereby improving the amplitude and phase distortion of the power amplifier 100. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thus improving the power-added efficiency of the power amplifier 100.

[0093] like Figure 10 As shown, the fourth bias circuit 60 includes a fourth bias unit 601, a seventh capacitor C7, and an eighth capacitor C8. The first terminal of the fourth bias unit 601 is connected to the fourth bias power supply terminal Vreg4, the second terminal of the fourth bias unit 601 is connected to the fourth bias power supply terminal Vbat4, the third terminal of the fourth bias unit 601 is connected to the input terminal of the fourth amplification unit 212, the seventh capacitor C7 is connected between the third terminal of the fourth bias unit 601 and the output terminal of the first amplification unit 201, and the eighth capacitor C8 is connected between the first terminal of the fourth bias unit 601 and the output terminal of the second amplification unit 202.

[0094] By setting a seventh capacitor C7 and an eighth capacitor C8 in the fourth bias circuit 60, the bias current input from the fourth bias circuit 60 to the fourth amplification unit 212 can be reduced due to their small capacitance values. This reduces the output current of the fourth amplification unit 212 at high power, thereby improving the amplitude and phase distortion of the power amplifier 100. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thus improving the power-added efficiency of the power amplifier 100.

[0095] like Figure 10As shown, the first bias unit 301 includes a first bias transistor P1. The first terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias transistor P1 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias transistor P1 is connected to the input terminal of the first amplification unit 201.

[0096] In some embodiments, the first bias transistor P1 is a metal-oxide-semiconductor field-effect transistor (MOSFET), with its first terminal serving as the gate, its second terminal as the drain or source, and its third terminal as the source or drain. By configuring the first bias transistor P1 as a MOSFET, the logic controlling the first bias unit 30 can be simplified, improving its efficiency and reducing its cost, due to the MOSFET's simple driving circuitry and low noise characteristics.

[0097] In other embodiments, the first bias transistor P1 is a bipolar junction transistor (BJT), with its first terminal being the base, its second terminal being the collector or emitter, and its third terminal being the emitter or collector. By configuring the first bias transistor P1 as a BJT, the low input impedance of the BJT allows it to withstand larger currents, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0098] like Figure 10 As shown, the second bias unit 401 includes a second bias transistor P2. The first terminal of the second bias transistor P2 is connected to the second bias power supply terminal Vreg2, the second terminal of the second bias transistor P2 is connected to the second bias power supply terminal Vbat2, and the third terminal of the second bias transistor P2 is connected to the input terminal of the second amplification unit 202.

[0099] In some embodiments, the second bias transistor P2 is a metal-oxide-semiconductor field-effect transistor (MOSFET), with its first terminal serving as the gate, its second terminal as the drain or source, and its third terminal as the source or drain. By configuring the second bias transistor P2 as a MOSFET, the logic controlling the second bias unit 40 can be simplified, improving its efficiency and reducing its cost, due to the MOSFET's simple driving circuitry and low noise characteristics.

[0100] In other embodiments, the second bias transistor P2 is a bipolar junction transistor (BJT). The first terminal of the second bias transistor P2 is the base, the second terminal is the collector or emitter, and the third terminal is the emitter or collector. By configuring the second bias transistor P2 as a BJT, the low input impedance of the BJT allows it to withstand larger currents, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0101] like Figure 10 As shown, the third bias unit 501 includes a third bias transistor P3. The first terminal of the third bias transistor P3 is connected to the third bias power supply terminal Vreg3, the second terminal of the third bias transistor P3 is connected to the third bias power supply terminal Vbat3, and the third terminal of the third bias transistor P3 is connected to the input terminal of the third amplification unit 211.

[0102] In some embodiments, the third bias transistor P3 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first terminal of the third bias transistor P3 is the gate, the second terminal is the drain or source, and the third terminal is the source or drain. By configuring the third bias transistor P3 as a MOSFET, the logic controlling the third bias unit 50 can be simplified, improving its efficiency and reducing its cost, due to the simple driving circuitry and low noise characteristics of MOSFETs.

[0103] In other embodiments, the third bias transistor P3 is a bipolar junction transistor (BJT). The first terminal of the third bias transistor P3 is the base, the second terminal is the collector or emitter, and the third terminal is the emitter or collector. By configuring the third bias transistor P3 as a BJT, the low input impedance of the BJT allows it to withstand larger currents, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0104] like Figure 10 As shown, the fourth bias unit 601 includes a fourth bias transistor P4. The first terminal of the fourth bias transistor P4 is connected to the fourth bias power supply terminal Vreg4, the second terminal of the fourth bias transistor P4 is connected to the fourth bias power supply terminal Vbat4, and the third terminal of the fourth bias transistor P4 is connected to the input terminal of the fourth amplification unit 212.

[0105] In some embodiments, the fourth bias transistor P4 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first terminal of the fourth bias transistor P4 is the gate, the second terminal is the drain or source, and the third terminal is the source or drain. By configuring the fourth bias transistor P4 as a MOSFET, the logic controlling the fourth bias unit 60 can be simplified, improving its efficiency and reducing its cost, due to the simple driving circuitry and low noise characteristics of MOSFETs.

[0106] In other embodiments, the fourth bias transistor P4 is a bipolar junction transistor (BJT). The first terminal of the fourth bias transistor P4 is the base, the second terminal is the collector or emitter, and the third terminal is the emitter or collector. By configuring the fourth bias transistor P4 as a BJT, the low input impedance of the BJT allows it to withstand larger currents, thus meeting the requirements of the power amplifier 100 operating in high-current scenarios.

[0107] In some embodiments, such as Figure 10 As shown, the first amplification unit 201 includes a first amplification transistor Q1 and a first inductor L1, the second amplification unit 202 includes a second amplification transistor Q2 and a second inductor L2, the third amplification unit 211 includes a third amplification transistor Q3 and a third inductor L3, and the fourth amplification unit 212 includes a fourth amplification transistor Q4 and a fourth inductor L4.

[0108] For example, the first amplifying transistor Q1, the second amplifying transistor Q2, the third amplifying transistor Q3, and the fourth amplifying transistor Q4 can all be, but are not limited to, transistors, field-effect transistors, and insulated-gate bipolar transistors, etc. Specifically, the first amplifying transistor Q1 amplifies the power of the radio frequency (RF) signal output from the first signal input terminal 101 and outputs the amplified RF signal to the second amplifying transistor Q2. The second amplifying transistor Q2 amplifies the power of the RF signal output from the first amplifying transistor Q1 and outputs the amplified RF signal to the first signal output terminal 102. The third amplifying transistor Q3 amplifies the power of the RF signal output from the second signal input terminal 103 and outputs the amplified RF signal to the fourth amplifying transistor Q4. The fourth amplifying transistor Q4 amplifies the power of the RF signal output from the third amplifying transistor Q3 and outputs the amplified RF signal to the second signal output terminal 104. The following description will assume that the first amplifying transistor Q1, the second amplifying transistor Q2, the third amplifying transistor Q3, and the fourth amplifying transistor Q4 are all transistors.

[0109] The base of the first amplifying transistor Q1 is connected to the first signal input terminal 101, the emitter of the first amplifying transistor Q1 is grounded, and the collector of the first amplifying transistor Q1 is connected to the first power supply terminal Vcc1 via the first inductor L1. The collector of the first amplifying transistor Q1 is the output terminal of the first amplifying unit 201. The base of the second amplifying transistor Q2 is connected to the collector of the first amplifying transistor Q1, the emitter of the second amplifying transistor Q2 is grounded, and the collector of the second amplifying transistor Q2 is connected to the second power supply terminal Vcc2 via the second inductor L2. The collector of the second amplifying transistor Q2 is the output terminal of the second amplifying unit 202. The base of the third amplifying transistor Q3 is connected to the second signal input terminal 103, the emitter of the third amplifying transistor Q3 is grounded, and the collector of the third amplifying transistor Q3 is connected to the third power supply terminal Vcc3 via the third inductor L3. The collector of the third amplifying transistor Q3 is the output terminal of the third amplifying unit 211. The base of the fourth amplifying transistor Q4 is connected to the collector of the third amplifying transistor Q3. The emitter of the fourth amplifying transistor Q4 is grounded. The collector of the fourth amplifying transistor Q4 is connected to the fourth power supply terminal Vcc4 through the fourth inductor L4. The collector of the fourth amplifying transistor Q4 is the output terminal of the fourth amplification unit 212.

[0110] For example, the first power supply terminal Vcc1, the second power supply terminal Vcc2, the third power supply terminal Vcc3, and the fourth power supply terminal Vcc4 can be voltage terminals or current terminals. These terminals can be independent or a single terminal. The first power supply terminal Vcc1 provides collector current to the third terminal of the first amplifying transistor Q1 through the first inductor L1. The second power supply terminal Vcc2 provides collector current to the third terminal of the second amplifying transistor Q2 through the second inductor L2. The third power supply terminal Vcc3 provides collector current to the third terminal of the third amplifying transistor Q3 through the third inductor L3. The fourth power supply terminal Vcc4 provides collector current to the third terminal of the fourth amplifying transistor Q4 through the fourth inductor L4.

[0111] In some embodiments, the phase difference between the radio frequency signal transmitted by the first amplification branch 20 and the radio frequency signal transmitted by the second amplification branch is 180°.

[0112] In this embodiment, the power amplifier 100 can be a differential amplifier, in which case the phase difference between the radio frequency signal transmitted by the first amplification branch 20 and the radio frequency signal transmitted by the second amplification branch 21 is 180°. By configuring the power amplifier 100 as a differential amplifier, the power amplifier 100 can transmit multiple differential signals simultaneously, thereby improving the output power of the power amplifier 100.

[0113] In some embodiments, the power amplifier 100 may be a Dougherty amplifier. When the power amplifier 100 is a Dougherty amplifier, the phase difference between the radio frequency signal transmitted by the first amplification branch 20 and the radio frequency signal transmitted by the second amplification branch 21 is 90°, the first amplification unit 201 and the second amplification unit 202 are carrier amplification circuits, and the third amplification unit 211 and the fourth amplification unit 212 are peak amplification circuits, or the first amplification unit 201 and the second amplification unit 202 are peak amplification circuits, and the third amplification unit 211 and the fourth amplification unit 212 are carrier amplification circuits.

[0114] In the above embodiments, by configuring the power amplifier 100 as a Dougherty amplifier, not only can the problem of deterioration in the gain amplitude and phase amplitude of the power amplifier 100 be improved, but the linear power back-off of the power amplifier 100 can also be improved, thereby improving the power-added efficiency of the power amplifier 100. Furthermore, the power amplifier 100 can also have high power-added efficiency, wide bandwidth and high power handling capability, thereby improving the power amplification performance and adaptability of the power amplifier 100.

[0115] In some embodiments, the power amplifier 100 may be a balanced amplifier. When the power amplifier 100 is a balanced amplifier, the phase difference between the radio frequency signal transmitted by the first amplification branch 20 and the radio frequency signal transmitted by the second amplification branch 21 is 90°. The first amplification unit 201, the second amplification unit 202, the third amplification unit 211 and the fourth amplification unit 212 are similar amplification circuits.

[0116] In the above embodiments, by configuring the power amplifier 100 as a balanced amplifier, not only can the problem of the deterioration of the gain amplitude and phase amplitude of the power amplifier 100 be improved, but the linear power back-off of the power amplifier 100 can also be improved, thereby improving the power-added efficiency of the power amplifier 100, and also improving the output capability and output matching characteristics of the power amplifier 100.

[0117] In some embodiments, such as Figure 11 As shown, the power amplifier 100 also includes a power distribution circuit 70 and a combining circuit 80. The input terminal of the power distribution circuit 70 is connected to the radio frequency signal input terminal RFIN. The first output terminal of the power distribution circuit 70 is connected to the first signal input terminal 101. The second output terminal of the power distribution circuit 70 is connected to the second signal input terminal 103. The first input terminal of the combining circuit 80 is connected to the first signal output terminal 102. The second input terminal of the combining circuit 80 is connected to the second signal output terminal 104. The output terminal of the combining circuit 80 is connected to the radio frequency signal output terminal RFout.

[0118] It should be noted that the power distribution circuit 70 is a circuit used to divide an input signal into at least two output signals with equal or unequal power according to a certain ratio; the combining circuit 80 is a circuit used to combine multiple signals into one output signal.

[0119] In the above embodiments, by setting a power distribution circuit 70 and a combining circuit 80 in the power amplifier 100, the power distribution circuit 70 can be used to split the radio frequency signal input to the power amplifier 100 into multiple signals to different amplification branches for power amplification, and the combining circuit 80 can be used to synthesize and output the power-amplified radio frequency signals output from different amplification branches. This allows the radio frequency signal input to the power amplifier 100 to be amplified by different factors, thereby enriching the application scenarios of the power amplifier 100.

[0120] Please see Figure 12 , Figure 12 This is a schematic diagram of the circuit structure of another power amplifier 100 provided in an embodiment of this application, as shown below. Figure 12 As shown, the power amplifier 100 may include a first signal input terminal 101, a first signal output terminal 102, a second signal input terminal 103, a second signal output terminal 104, an amplifier circuit 20, a first bias circuit 30, and a third bias circuit 50.

[0121] like Figure 12 As shown, the amplifier circuit 20 includes a first amplifier unit 201 and a third amplifier unit 211. The first amplifier unit 201 is connected between the first signal input terminal 101 and the first signal output terminal 102, and the third amplifier unit 211 is connected between the second signal input terminal 103 and the second signal output terminal 104.

[0122] The first bias circuit 30 includes a first bias unit 301, a first capacitor C1, and a second capacitor C2. The first terminal of the first bias unit 301 is connected to the first bias power supply terminal Vreg1, the second terminal of the first bias unit 301 is connected to the first bias power supply terminal Vbat1, and the third terminal of the first bias unit 301 is connected to the input terminal of the first amplification unit 201. The first capacitor C1 is connected between the third terminal of the first bias unit 301 and the second signal input terminal 103, and the second capacitor C2 is connected between the first terminal of the first bias unit 301 and the output terminal of the third amplification unit 211. The first bias unit 301 is used to input bias current to the first amplification unit 201.

[0123] By setting a first capacitor C1 and a second capacitor C2 in the first bias circuit 30, the bias current input from the first bias circuit 30 to the first amplification unit 201 can be reduced due to the small capacitance values ​​of the first capacitor C1 and the second capacitor C2. This reduces the output current of the first amplification unit 201 at high power. Therefore, the amplitude distortion and phase distortion of the power amplifier 100 can be improved. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thereby improving the power-added efficiency of the power amplifier 100.

[0124] The third bias circuit 50 includes a third bias unit 501, a fifth capacitor C5, and a sixth capacitor C6. The first end of the third bias unit 501 is connected to the third bias power supply terminal Vreg3, the second end of the third bias unit 501 is connected to the third bias power supply terminal Vbat3, the third end of the third bias unit 501 is connected to the input terminal of the third amplification unit 211, the fifth capacitor C5 is connected between the third end of the third bias unit 501 and the first signal input terminal 101, and the sixth capacitor C6 is connected between the first end of the third bias unit 501 and the output terminal of the first amplification unit 201.

[0125] By setting a fifth capacitor C5 and a sixth capacitor C6 in the third bias circuit 50, the bias current input from the third bias circuit 50 to the third amplification unit 211 can be reduced due to their small capacitance values. This reduces the output current of the third amplification unit 211 at high power, thereby improving the amplitude and phase distortion of the power amplifier 100. This not only optimizes the linearity of the power amplifier 100 but also ensures that its durability is not deteriorated, thus improving the power-added efficiency of the power amplifier 100.

[0126] like Figure 12 As shown, the power amplifier 100 may further include a ninth capacitor C9 and a tenth capacitor C10. The first terminal of the ninth capacitor C9 is connected to the first signal input terminal 101, and the second terminal of the ninth capacitor C9 is connected to the common terminal between the third terminal of the first bias unit 301 and the input terminal of the first amplification unit 201. The first terminal of the tenth capacitor C10 is connected to the second signal input terminal 103, and the second terminal of the tenth capacitor C10 is connected to the common terminal between the third terminal of the third bias unit 501 and the input terminal of the third amplification unit 211. The ninth capacitor C9 and the tenth capacitor C10 not only function as DC blocking capacitors but also as matching capacitors.

[0127] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power amplifier, characterized in that, The power amplifier includes a first signal input terminal and a first signal output terminal. An amplifier circuit, comprising a first amplification unit and a second amplification unit, wherein the first amplification unit is connected between the first signal input terminal and the second amplification unit, and the second amplification unit is connected between the first amplification unit and the first signal output terminal; A first bias circuit, the first bias circuit including a first bias unit. 、 The first capacitor and the second capacitor are connected as follows: the first end of the first bias unit is connected to the first bias power supply terminal; the second end of the first bias unit is connected to the first bias power supply terminal; the third end of the first bias unit is connected to the input terminal of the first amplification unit; the first capacitor is connected between the third end of the first bias unit and the first signal input terminal; and the second capacitor is connected between the first end of the first bias unit and the output terminal of the first amplification unit. The second bias circuit includes a second bias unit. 、 The third capacitor and the fourth capacitor are connected as follows: the first end of the second bias unit is connected to the second bias power supply terminal; the second end of the second bias unit is connected to the second bias power supply terminal; the third end of the second bias unit is connected to the input terminal of the second amplification unit; the third capacitor is connected between the third end of the second bias unit and the output terminal of the first amplification unit; and the fourth capacitor is connected between the first end of the second bias unit and the output terminal of the second amplification unit.

2. The power amplifier according to claim 1, characterized in that, The capacitance value of the first capacitor is in the range of [0pF, 4pF]; the capacitance value of the second capacitor is in the range of [0pF, 1pF].

3. The power amplifier according to claim 1, characterized in that, The capacitance value of the third capacitor is in the range of [1pF, 4pF]; the capacitance value of the fourth capacitor is in the range of [0.5pF, 1pF].

4. The power amplifier according to claim 3, characterized in that, The capacitance value of the third capacitor is in the range of [1pF, 2pF].

5. The power amplifier according to claim 1, characterized in that, The first bias unit includes a first bias transistor, a first terminal of the first bias transistor is connected to the first bias power supply terminal, a second terminal of the first bias transistor is connected to the first bias power supply terminal, and a third terminal of the first bias transistor is connected to the input terminal of the first amplification unit. The second bias unit includes a second bias transistor, a first terminal of which is connected to a second bias power supply terminal, a second terminal of which is connected to a second bias power supply terminal, and a third terminal of which is connected to the input terminal of the second amplification unit.

6. The power amplifier according to claim 5, characterized in that, The first bias transistor is a metal-oxide-semiconductor field-effect transistor. The first terminal of the first bias transistor is the gate, the second terminal of the first bias transistor is the drain or the source, and the third terminal of the first bias transistor is the source or the drain. Alternatively, the first bias transistor is a bipolar junction transistor, with its first terminal being the base, its second terminal being the collector, and its third terminal being the emitter; or, the first terminal of the first bias transistor is the base, its second terminal is the emitter, and its third terminal is the collector. The second bias transistor is a metal-oxide-semiconductor field-effect transistor. The first terminal of the second bias transistor is the gate, the second terminal of the second bias transistor is the drain or source, and the third terminal of the second bias transistor is the source or drain. Alternatively, the second bias transistor is a bipolar junction transistor, with its first terminal being the base, its second terminal being the collector, and its third terminal being the emitter; or, the second bias transistor has its first terminal being the base, its second terminal being the emitter, and its third terminal being the collector.

7. The power amplifier according to claim 1, characterized in that, The first amplification unit includes a first amplification transistor and a first inductor, and the second amplification unit includes a second amplification transistor and a second inductor; The first terminal of the first amplifying transistor is connected to the first signal input terminal, the second terminal of the first amplifying transistor is grounded, the third terminal of the first amplifying transistor is connected to the first power supply terminal through the first inductor, and the third terminal of the first amplifying transistor is the output terminal of the first amplifying unit. The first terminal of the second amplifying transistor is connected to the third terminal of the first amplifying transistor, the second terminal of the second amplifying transistor is grounded, the third terminal of the second amplifying transistor is connected to the second power supply terminal through the second inductor, and the third terminal of the second amplifying transistor is the output terminal of the second amplifying unit.

8. A power amplifier, characterized in that, The power amplifier includes a first signal input terminal and a first signal output terminal. An amplifier circuit, the amplifier circuit including a first amplification unit, the first amplification unit being connected between the first signal input terminal and the first signal output terminal; A first bias circuit, the first bias circuit including a first bias unit. 、 The first capacitor and the second capacitor are connected as follows: the first end of the first bias unit is connected to the first bias power supply terminal; the second end of the first bias unit is connected to the first bias power supply terminal; the third end of the first bias unit is connected to the input terminal of the first amplification unit; the first capacitor is connected between the third end of the first bias unit and the first signal input terminal; and the second capacitor is connected between the first end of the first bias unit and the output terminal of the first amplification unit.

9. The power amplifier according to claim 8, characterized in that, The first bias unit includes a first bias transistor, a first terminal of the first bias transistor is connected to the first bias power supply terminal, a second terminal of the first bias transistor is connected to the first bias power supply terminal, and a third terminal of the first bias transistor is connected to the input terminal of the first amplification unit.

10. The power amplifier according to claim 9, characterized in that, The first bias transistor is a metal-oxide-semiconductor field-effect transistor. The first terminal of the first bias transistor is the gate, the second terminal of the first bias transistor is the drain or the source, and the third terminal of the first bias transistor is the source or the drain. Alternatively, the first bias transistor is a bipolar junction transistor, with its first terminal being the base, its second terminal being the collector, and its third terminal being the emitter; or, the first terminal of the first bias transistor is the base, its second terminal is the emitter, and its third terminal is the collector.

11. The power amplifier according to claim 8, characterized in that, The first amplification unit includes a first amplification transistor and a first inductor; The base of the first amplifying transistor is connected to the first signal input terminal, the emitter of the first amplifying transistor is grounded, the collector of the first amplifying transistor is connected to the first power supply terminal through the first inductor, and the collector of the first amplifying transistor is the output terminal of the first amplification unit.

12. A power amplifier, characterized in that, The power amplifier has a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. It includes a first amplification branch connected between the first signal input terminal and the first signal output terminal, and a second amplification branch connected between the second signal input terminal and the second signal output terminal. The first amplification branch includes a cascaded first amplification unit and a second amplification unit; the second amplification branch includes a cascaded third amplification unit and a fourth amplification unit. A first bias circuit, the first bias circuit including a first bias unit. 、 The first capacitor and the second capacitor are connected as follows: the first end of the first bias unit is connected to the first bias power supply terminal; the second end of the first bias unit is connected to the first bias power supply terminal; the third end of the first bias unit is connected to the input terminal of the first amplification unit; the first capacitor is connected between the third end of the first bias unit and the second signal input terminal; and the second capacitor is connected between the first end of the first bias unit and the output terminal of the third amplification unit. The second bias circuit includes a second bias unit. 、 The third capacitor and the fourth capacitor are connected as follows: the first terminal of the second bias unit is connected to the second bias power supply terminal; the second terminal of the second bias unit is connected to the second bias power supply terminal; the third terminal of the second bias unit is connected to the input terminal of the second amplification unit; the third capacitor is connected between the third terminal of the second bias unit and the output terminal of the third amplification unit; and the fourth capacitor is connected between the first terminal of the second bias unit and the output terminal of the fourth amplification unit. The third bias circuit includes a third bias unit. 、 The fifth capacitor and the sixth capacitor are provided. The first end of the third bias unit is connected to the third bias power supply terminal, the second end of the third bias unit is connected to the third bias power supply terminal, the third end of the third bias unit is connected to the input terminal of the third amplification unit, the fifth capacitor is connected between the third end of the third bias unit and the first signal input terminal, and the sixth capacitor is connected between the first end of the third bias unit and the output terminal of the first amplification unit. The fourth bias circuit includes a fourth bias unit. 、 The seventh capacitor and the eighth capacitor are provided. The first end of the fourth bias unit is connected to the fourth bias power supply terminal, the second end of the fourth bias unit is connected to the fourth bias power supply terminal, the third end of the fourth bias unit is connected to the input terminal of the fourth amplification unit, the seventh capacitor is connected between the third end of the fourth bias unit and the output terminal of the first amplification unit, and the eighth capacitor is connected between the first end of the fourth bias unit and the output terminal of the second amplification unit.

13. The power amplifier according to claim 12, characterized in that, The first bias unit includes a first bias transistor, a first terminal of the first bias transistor is connected to the first bias power supply terminal, a second terminal of the first bias transistor is connected to the first bias power supply terminal, and a third terminal of the first bias transistor is connected to the input terminal of the first amplification unit. The second bias unit includes a second bias transistor, a first terminal of the second bias transistor is connected to a second bias power supply terminal, a second terminal of the second bias transistor is connected to a second bias power supply terminal, and a third terminal of the second bias transistor is connected to the input terminal of the second amplification unit. The third bias unit includes a third bias transistor, the first terminal of which is connected to the third bias power supply terminal, the second terminal of which is connected to the third bias power supply terminal, and the third terminal of which is connected to the input terminal of the third amplification unit. The fourth bias unit includes a fourth bias transistor, the first terminal of which is connected to the fourth bias power supply terminal, the second terminal of which is connected to the fourth bias power supply terminal, and the third terminal of which is connected to the input terminal of the fourth amplification unit.

14. The power amplifier according to claim 12, characterized in that, The first amplification unit includes a first amplification transistor and a first inductor; the second amplification unit includes a second amplification transistor and a second inductor; the third amplification unit includes a third amplification transistor and a third inductor; and the fourth amplification unit includes a fourth amplification transistor and a fourth inductor. The base of the first amplifying transistor is connected to the first signal input terminal, the emitter of the first amplifying transistor is grounded, the collector of the first amplifying transistor is connected to the first power supply terminal through the first inductor, and the collector of the first amplifying transistor is the output terminal of the first amplifying unit. The base of the second amplifying transistor is connected to the collector of the first amplifying transistor, the emitter of the second amplifying transistor is grounded, the collector of the second amplifying transistor is connected to the second power supply terminal through the second inductor, and the collector of the second amplifying transistor is the output terminal of the second amplifying unit. The base of the third amplifying transistor is connected to the second signal input terminal, the emitter of the third amplifying transistor is grounded, the collector of the third amplifying transistor is connected to the third power supply terminal through the third inductor, and the collector of the third amplifying transistor is the output terminal of the third amplifying unit. The base of the fourth amplifying transistor is connected to the collector of the third amplifying transistor, the emitter of the fourth amplifying transistor is grounded, the collector of the fourth amplifying transistor is connected to the fourth power supply terminal through the fourth inductor, and the collector of the fourth amplifying transistor is the output terminal of the fourth amplifying unit.

15. The power amplifier according to claim 12, characterized in that, The phase difference between the radio frequency signal transmitted by the first amplification branch and the radio frequency signal transmitted by the second amplification branch is 180°.

16. The power amplifier according to claim 12, characterized in that, The phase difference between the radio frequency signal transmitted by the first amplification branch and the radio frequency signal transmitted by the second amplification branch is 90°. The first amplification unit and the second amplification unit are carrier amplification circuits, and the third amplification unit and the fourth amplification unit are peak amplification circuits. Alternatively, the first amplification unit and the second amplification unit are peak amplification circuits, and the third amplification unit and the fourth amplification unit are carrier amplification circuits.

17. The power amplifier according to claim 12, characterized in that, The phase difference between the radio frequency signal transmitted by the first amplification branch and the radio frequency signal transmitted by the second amplification branch is 90°, and the first amplification unit, the second amplification unit, the third amplification unit and the fourth amplification unit are similar amplification circuits.

18. The power amplifier according to claim 12, characterized in that, The power amplifier further includes a power distribution circuit and a combining circuit. The input terminal of the power distribution circuit is connected to the radio frequency signal input terminal. The first output terminal of the power distribution circuit is connected to the first signal input terminal. The second output terminal of the power distribution circuit is connected to the second signal input terminal. The first input terminal of the combining circuit is connected to the first signal output terminal. The second input terminal of the combining circuit is connected to the second signal output terminal. The output terminal of the combining circuit is connected to the radio frequency signal output terminal.

19. A power amplifier, characterized in that, The power amplifier includes a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. An amplifier circuit, comprising a first amplification unit and a third amplification unit, wherein the first amplification unit is connected between the first signal input terminal and the first signal output terminal, and the third amplification unit is connected between the second signal input terminal and the second signal output terminal; A first bias circuit includes a first bias unit, a first capacitor, and a second capacitor. A first terminal of the first bias unit is connected to a first bias power supply terminal, a second terminal of the first bias unit is connected to a first bias power supply terminal, a third terminal of the first bias unit is connected to the input terminal of the first amplification unit, the first capacitor is connected between the third terminal of the first bias unit and the second signal input terminal, and the second capacitor is connected between the first terminal of the first bias unit and the output terminal of the third amplification unit. The third bias circuit includes a third bias unit, a fifth capacitor, and a sixth capacitor. The first terminal of the third bias unit is connected to the third bias power supply terminal, the second terminal of the third bias unit is connected to the third bias power supply terminal, the third terminal of the third bias unit is connected to the input terminal of the third amplification unit, the fifth capacitor is connected between the third terminal of the third bias unit and the first signal input terminal, and the sixth capacitor is connected between the first terminal of the third bias unit and the output terminal of the first amplification unit.

20. A radio frequency front-end module, characterized in that, The radio frequency front-end module includes a power amplifier as described in any one of claims 1 to 7, or a power amplifier as described in any one of claims 8 to 11, or a power amplifier as described in any one of claims 12 to 18, or a power amplifier as described in claim 19.

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