Radio frequency front-end module and communication equipment

Abstract

The utility model discloses a radio frequency front-end module and communication equipment, and the radio frequency front-end module comprises a substrate, a first chip, a second chip and a connecting piece. The substrate comprises a first surface and a second surface which are opposite to each other, the first chip and the second chip are arranged on the first surface, and the second surface is provided with a metal layer; the first chip is integrated with an amplification transistor, the second chip is integrated with a capacitance network, and the output end of the amplification transistor is connected to the capacitance network through the connecting piece. According to the radio frequency front-end module provided by the invention, the amplification transistor is integrated on the first chip, and the capacitor network is integrated on the second chip, so that the amplification transistor is placed on different chips, and the situation that the amplification transistor and the capacitor network are arranged on the same chip is avoided; therefore, a capacitor device in the capacitor network has an adverse effect on the amplification effect of the amplification transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a radio frequency front-end module and a communication device. BACKGROUND

[0002] The key performance target of the fifth and sixth generation mobile communication technology is to greatly improve the transmission rate compared with 4G, so that the new generation of communication technology needs to use a radio frequency front-end with higher frequency, larger bandwidth and higher order QAM modulation, which puts forward more stringent requirements for the design of the radio frequency front-end module.

[0003] The radio frequency power amplifier transistor is an important device of the radio frequency front-end module. Usually, the radio frequency power amplifier transistor is integrated in a power amplifier chip. In the related art, in order to realize the miniaturization of the radio frequency front-end module, a capacitor device is also integrated in the power amplifier chip. However, it is found in practice that the capacitor device arranged in the power amplifier chip has an impact on the radio frequency power amplification performance, especially the impact on the radio frequency power amplification performance applied to a higher frequency band is more obvious, which finally affects the overall performance of the radio frequency front-end module. SUMMARY

[0004] Based on this, the embodiments of the present application provide a radio frequency front-end module and a communication device.

[0005] In a first aspect, the embodiments of the present application provide a radio frequency front-end module, characterized in that it comprises a substrate, a first chip, a second chip and a connecting piece; wherein the substrate comprises a first surface and a second surface opposite to each other, the first chip and the second chip are arranged on the first surface, and the second surface is provided with a metal layer; the first chip is integrated with an amplifying transistor, the second chip is integrated with a capacitor network, and the output end of the amplifying transistor is connected to the capacitor network through the connecting piece.

[0006] In some embodiments, the thickness of the first chip is less than the thickness of the second chip.

[0007] In some embodiments, the second chip is an IPD chip, and / or the thickness of the second chip is 60um-120um.

[0008] In some embodiments, the amplifying transistor comprises a first amplifying transistor and a second amplifying transistor, the capacitor network comprises a first capacitor network and a second capacitor network, and the connecting piece comprises a first connecting piece and a second connecting piece.

[0009] The first chip is provided with a third pad and a fourth pad, the second chip is provided with a first pad and a second pad, the output end of the first amplification transistor is connected to the third pad, the output end of the second amplification transistor is connected to the fourth pad, the first capacitor network is connected to the first pad, the second capacitor network is connected to the second pad, the first connecting piece is connected to the third pad and the first pad, and the second connecting piece is connected to the fourth pad and the second pad.

[0010] In some embodiments, the first chip and the second chip are arranged in a first direction.

[0011] The first pad and the second pad are arranged in a column in a second direction on the side of the second chip close to the first chip.

[0012] The third pad and the fourth pad are arranged in a column in the second direction on the side of the first chip close to the second chip, and the second direction and the first direction are perpendicular to each other.

[0013] In some embodiments, a plurality of the first amplification transistors are arranged in the second direction on the side of the third pad away from the second chip, and the plurality of the first amplification transistors form a first transistor arrangement area which is the minimum rectangular area required to accommodate the plurality of the first amplification transistors; and the third pad has a first projection in the first direction, the first transistor arrangement area has a second projection in the first direction, the first projection and the second projection at least partially overlap, and the overlapping part of the first projection and the second projection in the second direction extends for 30% to 100% of the extension length of the second projection in the second direction.

[0014] And / or, a plurality of the second amplification transistors are arranged in the second direction on the side of the fourth pad away from the second chip, and the plurality of the second amplification transistors form a second transistor arrangement area which is the minimum rectangular area required to accommodate the plurality of the second amplification transistors; and the fourth pad has a third projection in the first direction, the second transistor arrangement area has a fourth projection in the first direction, the third projection and the fourth projection at least partially overlap, and the overlapping part of the third projection and the fourth projection in the second direction extends for 30% to 100% of the extension length of the fourth projection in the second direction.

[0015] In some embodiments, a plurality of the first amplification transistors are arranged along the second direction on a side of the third pad away from the second chip, and the plurality of the first amplification transistors form a first transistor arrangement region, a middle line of the first transistor arrangement region coincides with a middle line of the third pad in the second direction.

[0016] In some embodiments, a plurality of the second amplification transistors are arranged along the second direction on a side of the fourth pad away from the second chip, and the plurality of the second amplification transistors form a second transistor arrangement region, a middle line of the second transistor arrangement region coincides with a middle line of the fourth pad in the second direction.

[0017] In some embodiments, the first connecting member includes at least a first lead wire, and a parasitic inductance of the first lead wire forms a first inductance.

[0018] In some embodiments, the second connecting member includes at least a second lead wire, and a parasitic inductance of the second lead wire forms a second inductance.

[0019] In some embodiments, the first surface is further provided with a first power port and a second power port, the connecting member further includes a third connecting member and a fourth connecting member, the first power port is connected to the first pad through the third connecting member, and the second power port is connected to the second pad through the fourth connecting member.

[0020] In some embodiments, the third connecting member includes at least a third lead wire, and a parasitic inductance of the third lead wire forms a third inductance.

[0021] In some embodiments, the fourth connecting member includes at least a fourth lead wire, and a parasitic inductance of the fourth lead wire forms a fourth inductance.

[0022] In some embodiments, the first chip is arranged adjacent to a first side edge of the second chip, the first power port and the second power port are arranged on a second side edge and a third side edge of the second chip opposite to each other, and the first side edge is adjacent to the second side edge and the third side edge respectively.

[0023] In some embodiments, the first chip is further provided with a third capacitor, a fourth capacitor, a fifth pad and a sixth pad, a first end of the third capacitor is connected to an output end of the first amplification transistor, a second end of the third capacitor is connected to the fifth pad, a first end of the fourth capacitor is connected to an output end of the second amplification transistor, and a second end of the fourth capacitor is connected to the sixth pad.

[0024] In some embodiments, the capacitance value of the third capacitor is less than the capacitance value of the first capacitor network; and / or, the capacitance value of the fourth capacitor is less than the capacitance value of the second capacitor network.

[0025] In some embodiments, the first surface is further provided with a first grounding pad and a second grounding pad, and the connector further includes a fifth connector and a sixth connector;

[0026] The first end of the fifth connector is connected to the fifth pad, and the second end of the fifth connector is connected to the first ground pad; the first end of the sixth connector is connected to the sixth pad, and the second end of the sixth connector is connected to the second ground pad.

[0027] In some embodiments, the fifth connector includes at least a fifth lead, the parasitic inductance of which forms a fifth inductance; the sixth connector includes at least a sixth lead, the parasitic inductance of which forms a sixth inductance.

[0028] The fifth inductor and the third capacitor form a first LC resonant circuit, and the sixth inductor and the fourth capacitor form a second LC resonant circuit.

[0029] In some embodiments, the RF front-end module further includes a balun disposed on the second chip, wherein a first end of the first capacitor network is connected to the first pad, and a second end of the first capacitor network is connected to a first input terminal of the balun; a first end of the second capacitor network is connected to the second pad, and a second end of the second capacitor network is connected to a second input terminal of the balun.

[0030] In some embodiments, the balun includes a first primary coil and a second primary coil, and a first secondary coil coupled to the first primary coil and the second primary coil;

[0031] Wherein, the second end of the first capacitor network is connected to the first end of the first primary coil, the second end of the second capacitor network is connected to the second end of the second primary coil, the second end of the first primary coil is connected to the first end of the second primary coil, and the first end of the second primary coil is grounded; or, the second end of the first capacitor network is connected to the first end of the first primary coil, the second end of the second capacitor network is connected to the second end of the second primary coil, and both the second end of the first primary coil and the first end of the second primary coil are grounded.

[0032] In some embodiments, the RF front-end module further includes a matching circuit, wherein a first end of the primary coil is coupled to or connected to the matching circuit, and a second end of the primary coil is grounded.

[0033] In some embodiments, the matching circuit includes a fifth capacitor, a seventh inductor, and a sixth capacitor;

[0034] The fifth capacitor is disposed on the second chip, and the second chip is also provided with a third grounding pad. The first end of the fifth capacitor is connected to the output end of the first primary coil, and the second end of the fifth capacitor is connected to the third grounding pad.

[0035] The radio frequency front-end module also includes a third chip, the sixth capacitor is disposed on the third chip, and the third chip is also provided with a fourth ground pad, the second end of the sixth capacitor is connected to the fourth ground pad;

[0036] The connector further includes a seventh connector, the first end of which is connected to the first end of the fifth capacitor, the second end of which is connected to the first end of the sixth capacitor, and the parasitic inductance of the seventh connector forms the seventh inductance.

[0037] In some embodiments, the capacitance value of the first capacitor network is in the range of [3pF, 20pF]; and / or, the capacitance value of the second capacitor network is in the range of [3pF, 20pF].

[0038] In some embodiments, the radio frequency front-end module operates at a frequency of 5.1 GHz. Z Up to 5.9GH Z .

[0039] Secondly, embodiments of this application provide a communication device, which includes the aforementioned radio frequency front-end module.

[0040] As can be seen from the above technical solution, the RF front-end module provided in this application integrates the amplifying transistor into the first chip and the capacitor network into the second chip, thereby placing the amplifying transistor into different chips. Compared with placing the amplifying transistor and the capacitor network into the same chip, this can reduce the adverse effect of the parasitic capacitance formed between the capacitor network and the metal layer of the substrate on the amplifying transistor, so as to effectively enable the RF front-end module to have better working performance.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic cross-sectional view of the radio frequency power amplifier provided in the embodiments of this application;

[0044] Figure 2 This is a top view of the radio frequency power amplifier provided in the embodiments of this application;

[0045] Figure 3 This is a schematic diagram of a modified embodiment of the radio frequency power amplifier provided in this application.

[0046] Figure 4 This is a schematic diagram of another modified embodiment of the radio frequency power amplifier provided in this application;

[0047] Figure 5 This is a schematic diagram showing the projection relationship between the pads and the first amplifying transistor connected to the pads in the RF front-end module.

[0048] Figure 6 This is a schematic diagram of the structure in the RF front-end module where the projected center lines of the pads and the first amplifying transistor connected to the pads coincide.

[0049] Figure 7 This is a schematic diagram of another modified embodiment of the radio frequency power amplifier provided in this application;

[0050] Figure 8 This is a block diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0053] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. They can refer to a mechanical connection or an electrical connection. They can refer to a direct connection or an indirect connection through an intermediate medium, and they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0054] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0055] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0056] Please see Figures 1 to 2 , Figure 1 This is a block diagram of a radio frequency front-end module provided in an embodiment of this application.

[0057] like Figure 1 and Figure 2 As shown, the RF front-end module 100 includes a substrate 50, a first chip 30, a second chip 40, and a connector 80. The substrate 50 includes a first surface 501 and a second surface 502 facing away from each other. The first chip 30 and the second chip 40 are disposed on the first surface 501, and the second surface 502 has a metal layer 503. The first chip 30 integrates an amplifying transistor 10, and the second chip 40 integrates a capacitor network 17. The output terminal of the amplifying transistor is connected to the capacitor network 17 via the connector 80.

[0058] It is understood that the amplifying transistor 10 can be a BJT transistor or a field-effect transistor (FET). Optionally, the amplifying transistor 10 includes at least one BJT transistor (e.g., an HBT transistor) or at least one field-effect transistor. Exemplarily, the amplifying transistor 10 can be formed by multiple BJT transistors connected in parallel. Optionally, the amplifying transistor 10 can be any amplification stage in the amplification circuit formed by the first chip 30. Exemplarily, this amplification stage can be any of the amplification stages of a driver stage, an intermediate stage, or an output stage.

[0059] It can also be understood that the amplification circuit formed by the amplifying transistors 10 in the first chip 30 can be a single-ended input amplification circuit. For example, the first chip 30 includes multiple amplifying transistors 10 connected in series, and the input terminals of the multiple amplifying transistors 10 connected in series are used to receive radio frequency signals, and the output terminals of the multiple amplifying transistors 10 connected in series are connected to the capacitor network 17 through connectors 80, such as... Figure 3 As shown.

[0060] Alternatively, the amplifier circuit formed by the amplifying transistor 10 in the first chip 30 can also be a differential amplifier circuit. For example, the amplifying transistor 10 forms a first amplifying branch and a second amplifying branch, and the input terminals of the first amplifying branch and the second amplifying branch are both used to receive radio frequency signals.

[0061] Since the substrate has a metal layer (also known as back gold), if the capacitor network and the amplifying transistor are integrated into the same chip, a large parasitic capacitance will be generated between the capacitor network and the amplifying transistor and the back gold of the substrate, which will affect the amplification performance of the amplifying transistor and thus affect the working performance of the RF front-end module 100.

[0062] Based on this, the RF front-end module 100 provided in this application integrates the amplifying transistor 10 into the first chip 30 and the capacitor network 17 into the second chip 40. Compared with placing the amplifying transistor 10 and the capacitor network 17 on the same chip, the influence of the parasitic capacitance generated between the capacitor network and the metal layer of the substrate on the amplifying performance of the amplifying transistor can be reduced, thereby improving the working performance of the RF front-end module 100.

[0063] Meanwhile, the first chip 30 and the second chip 40 are placed on the same surface of the substrate, and the output terminal of the amplifying transistor 10 and the capacitor network 17 are connected by the connector 80. The capacitor network 17 and the connector 80 form an output matching circuit to achieve impedance matching of the output terminal of the amplifying transistor 10, thereby achieving better impedance matching, reducing losses and improving the operating efficiency of the RF power amplifier.

[0064] In some implementations, the RF front-end module 100 operates in a target frequency band, which is a high-frequency band. Optionally, the RF power amplifier 10 operates in a target frequency band of 2 GHz or higher.

[0065] In an exemplary embodiment, the target frequency band for the RF power amplifier 10 is between 2GHz and 8GHz, optionally between 5.1GHz and 5.9GHz. When the RF front-end module 100 is used in a high-frequency band, the impedance matching requirements are more stringent. This application integrates the amplifying transistor 10 into the first chip 30 and the capacitor network 17 into the second chip 40, avoiding the generation of large parasitic capacitance between the amplifying transistor 10 and the metal layer of the substrate due to their placement on the same chip. This effectively reduces the impact of large parasitic capacitance on the amplification performance of the amplifying transistor, thereby improving the operating performance of the RF front-end module 100.

[0066] Meanwhile, the first chip 30 and the second chip 40 are placed on the same surface of the substrate, and the output terminal of the amplifying transistor 10 and the capacitor network 17 are connected by the connector 80. The capacitor network 17 and the connector 80 form an output matching circuit to achieve impedance matching of the output terminal of the amplifying transistor 10, thereby achieving better impedance matching, reducing losses and improving the operating efficiency of the RF power amplifier.

[0067] In some embodiments, the first chip 30 has a first substrate 301, the second chip 40 has a second substrate 401, and the thickness of the second substrate 401 is greater than or equal to the thickness of the first substrate 301. An amplifying transistor 10 is formed on the first substrate 301, and a capacitor network 17 is formed on the second substrate 401.

[0068] like Figure 1 As shown, exemplarily, the first chip 30 is a power amplifier chip, also known as a PA chip. For example, if the amplifying transistor 10 is an HBT transistor, then the first chip 30 is an HBT chip manufactured using HBT technology. The second chip is a non-power amplifier chip, such as an IPD chip manufactured using IPD technology. Since the first chip 30 contains the amplifying transistor 10, and the amplifying transistor 10 requires grounding, it is typically grounded via leads. If the leads are too long, the parasitic inductance attached to the leads will be large, thus affecting the operating performance of the first chip 30. Therefore, the thickness of the first substrate 301 of the first chip 30 cannot be too thick. Simultaneously, the amplifying transistor 10 generates considerable heat during operation. To improve the heat dissipation performance of the first chip 30, the thickness of the first substrate 301 of the first chip 30 cannot be too thick. In summary, the industry typically defines the first substrate 301 of the first chip 30 as a standard substrate, and its thickness is usually a fixed value.

[0069] In this embodiment, by placing the capacitor network 17 on the second chip 40, and ensuring that the thickness of the second substrate 401 of the second chip 40 is greater than the thickness of the first substrate 301 of the first chip 30, the capacitor network 17 can be formed after the second substrate 401. The capacitor network 17 and the first chip 30 are then connected via a connector 80. Due to the greater thickness of the second substrate 401, sufficient spacing is provided between the capacitor network 17 and the metal layer 503 of the substrate 50, reducing parasitic capacitance between the capacitor network 17 and the metal layer 503 of the substrate 50. Since the thickness of the first substrate 301 is less than the thickness of the second substrate 401, the thickness of the packaged first chip 30 is less than the thickness of the second chip 40. Optionally, the thickness of the second chip 40 is 60µm-120µm.

[0070] In some embodiments, the amplifying transistor 10 includes a first amplifying transistor 11 and a second amplifying transistor 12, the capacitor network 17 includes a first capacitor network 171 and a second capacitor network 172, and the connector 80 includes a first connector 81 and a second connector 82. The first chip 30 is provided with a third pad 301 and a fourth pad 302, and the second chip 40 is provided with a first pad 401 and a second pad 402. The output terminal of the first amplifying transistor 11 is connected to the third pad 301, the output terminal of the second amplifying transistor 12 is connected to the fourth pad 302, the first capacitor network 171 is connected to the first pad 401, the second capacitor network 172 is connected to the second pad 402, the first connector 81 connects the third pad 301 and the first pad 401, and the second connector 82 connects the fourth pad 302 and the second pad 402.

[0071] In some embodiments, the capacitance values ​​of the first capacitor network 171 and / or the second capacitor network 172 are in the range of [3pF, 20pF]. In this application, a capacitor network with a large capacitance value, such as a capacitor network with a capacitance value greater than or equal to 3pF, is disposed in the second chip 40, which can reduce the impact of the parasitic capacitance generated between the capacitor network and the metal layer 503 of the substrate 50 on the amplifying transistor 10.

[0072] Optionally, for example, if the target frequency band for the operation of the RF front-end module 100 is in the high-frequency band (e.g., 5.1GHz-5.9GHz), the capacitance values ​​of the first capacitor network 172 and / or the second capacitor network 173 can be in the range of [3pF, 10pF]. Alternatively, the capacitance values ​​of the first capacitor network 172 and / or the second capacitor network 173 can be in the range of [3pF, 5pF]. Combined with the parasitic inductance generated by the connector 80, better impedance matching can be achieved.

[0073] Optionally, the first chip 30 and the second chip 40 are disposed at a distance from each other on the substrate 50 along the first direction, and the first pad 401 and the second pad 402 are arranged in a row along the second direction on the side of the second chip 40 near the first chip 30; the third pad 301 and the fourth pad 302 are arranged in a row along the second direction on the side of the first chip 30 near the second chip 40, and the second direction and the first direction are perpendicular to each other.

[0074] In the above embodiment, the first amplifying transistor 11, the second amplifying transistor 12, the first capacitor network 171, and the second capacitor network 172 cooperate to form a differential amplifier circuit, wherein the first amplifying transistor 11 and the first capacitor network 171 form a first differential amplification branch. The second amplifying transistor 12 and the second capacitor network 172 form a second differential amplification branch, thereby realizing differential amplification of the input signal.

[0075] Furthermore, by arranging the first chip 30 and the second chip 40 at intervals along the first direction on the substrate 50, and arranging the first pad 401 and the second pad 402 in a row along the second direction on the side of the second chip 40 near the first chip 30, and arranging the third pad 301 and the fourth pad 302 in a row along the second direction on the side of the first chip 30 near the second chip 40, the length of the first connector 81 is relatively short during the connection process between the first amplifying transistor 11 disposed on the first chip 30 and the first capacitor network 171 disposed on the second chip 40. At the same time, the length of the second connector 82 is relatively short during the connection process between the second amplifying transistor 12 disposed on the first chip 30 and the second capacitor network 172 disposed on the second chip 40.

[0076] like Figure 2 and Figure 4 As shown, in some embodiments, the first connector 81 includes at least a first lead, the parasitic inductance Lx1 of the first lead forming a first inductance; and / or, the second connector 82 includes at least a second lead, the parasitic inductance Lx2 of the second lead forming a second inductance.

[0077] It is understood that the first connector 81 and the second connector 82 can be leads or connection bumps of flip chips, such as solder balls, copper pillars, etc., and are not specifically limited in the embodiments of this application.

[0078] For example, the first connector 81 and the second connector 82 are leads, also known as bonding wires. The first pad 401 and the third pad 301 are connected through the first lead, and the second pad 402 and the fourth pad 302 are connected through the second lead. Furthermore, the parasitic inductance Lx1 of the first lead forms the first inductance, and the parasitic inductance Lx2 of the second lead forms the second inductance. The first inductance enables the first amplifying transistor 11 and the first capacitor network 171 to form a first differential amplification branch, achieving better impedance matching. Similarly, the second inductance enables the second amplifying transistor 12 and the second capacitor network 172 to form a second differential amplification branch, achieving better impedance matching.

[0079] It is understandable that the number of leads can be set according to the required inductance between the two connection points. That is, the first lead and the second lead can be one or more, and there is no limitation here.

[0080] like Figure 2 and Figure 4 As shown, in some embodiments, the first surface 501 of the substrate 50 is further provided with a first power port 60 and a second power port 70. The connector 80 further includes a third connector 83 and a fourth connector 84. The first power port 60 is connected to the first pad 401 through the third connector 83, and the second power port 70 is connected to the second pad 402 through the fourth connector 84. Optionally, the third connector 83 includes at least a third lead, and the parasitic inductance Lx3 of the third lead forms a third inductance; and / or, the fourth connector 84 includes at least a fourth lead, and the parasitic inductance Lx4 of the fourth lead forms a fourth inductance.

[0081] For example, the third connector 83 and the fourth connector 84 are leads, also known as bonding wires. The first power port 60 is connected to the first pad 401 through the third lead, and the second power port 70 is connected to the second pad 402 through the fourth lead. Furthermore, the parasitic inductance Lx3 of the third lead forms the third inductor, and the parasitic inductance Lx4 of the fourth lead forms the fourth inductor. The third inductor enables the first amplifying transistor 11 and the first capacitor network 171 to form a first differential amplification branch, achieving better impedance matching. Similarly, the fourth inductor enables the second amplifying transistor 12 and the second capacitor network 172 to form a second differential amplification branch, achieving better impedance matching.

[0082] like Figure 2 and Figure 4 As shown, in some embodiments, the first chip 30 is disposed adjacent to the first side of the second chip 40, and the first power port 60 and the second power port 70 are disposed on the opposite second and third sides of the second chip 40, wherein the first side is adjacent to the second side and the third side, respectively.

[0083] By placing the first power port 60 and the second power port 70 on opposite sides of the second chip 40 and connecting them to corresponding pads on the second chip 40 via leads, impedance matching of the amplifying transistors in the first chip can be effectively achieved. For example, taking the first amplifying transistor 11 as an example, the first power port 60 utilizes the parasitic inductance generated by the third lead, combined with the first capacitor network 172 and the parasitic inductance generated by the first lead, to form an impedance matching circuit connected to the output terminal of the first amplifying transistor 11, which is beneficial for impedance matching at the output terminal of the first amplifying transistor 11.

[0084] Please see Figure 2 and Figure 5 In some embodiments, a plurality of first amplifying transistors 11 are spaced apart along a second direction on the side of the third pad 301 away from the second chip 40, and the plurality of first amplifying transistors 11 form a first transistor arrangement area. The third pad 301 has a first projection in the first direction, and the first transistor arrangement area has a second projection in the first direction. The first projection and the second projection at least partially overlap, and the extension length of the overlapping portion of the first projection and the second projection in the second direction is 30%-100% of the extension length of the second projection in the second direction. Optionally, the first transistor arrangement area is the minimum rectangular area required to accommodate the plurality of first amplifying transistors 11.

[0085] like Figure 5 As shown, for example, multiple first amplifying transistors 11 form a first transistor arrangement area S1. Projecting along a first direction, the first projection can have a first projection on plane M, and the extension length of the first projection in a second direction is L1. The third pad 401 is projected along the first direction, and it can have a second projection on plane M, and the extension length of the second projection in the second direction is L2. The overlapping part of the first projection and the second projection has an extension length of L3 in the second direction, where L3≤L2, and 0.3L1≤L3≤L1. This makes the lead lengths corresponding to the connection paths between the third pad 401 and each first amplifying transistor 11 relatively consistent, avoiding a large signal transmission time difference introduced by the different lengths of the connection paths between the third pad 401 and each first amplifying transistor 11. This is more conducive to reducing the path difference between each first amplifying transistor 11 and the corresponding pad, thereby reducing the phase difference between the output signals of each first amplifying transistor 11, which is beneficial to signal synthesis.

[0086] In some embodiments, a plurality of second amplifying transistors 12 are spaced apart along a second direction on the side of the fourth pad 302 away from the second chip 40, and the plurality of second amplifying transistors 12 form a second transistor arrangement area. The fourth pad 302 has a third projection in a first direction, and the second transistor arrangement area has a fourth projection in the first direction. The third projection and the fourth projection at least partially overlap, and the extension length of the overlapping portion of the third projection and the fourth projection in the second direction is 30%-100% of the extension length of the fourth projection in the second direction. Optionally, the second transistor arrangement area is the minimum rectangular area required to accommodate the plurality of second amplifying transistors 12.

[0087] Multiple second amplifying transistors 12 form a second transistor arrangement area S2. Projecting along the first direction, the second transistor arrangement area S2 can have a third projection on the plane M. The extension length of the third projection in the second direction is L3. The fourth pad 402 can have a fourth projection on the plane M. The extension length of the fourth projection in the second direction is L4. The overlapping part of the third projection and the fourth projection has an extension length of L5 in the second direction, where L5≤L4 and 0.3L3≤L5≤L3. This ensures that the lead lengths corresponding to the connection paths between the fourth pad 402 and each second amplifying transistor 12 are relatively consistent. This avoids the difference in the length of the connection paths between the fourth pad 402 and each second amplifying transistor 12, which is more conducive to reducing the path difference between each second amplifying transistor 12 and its corresponding pad. This reduces the phase difference between the output signals of each second amplifying transistor 12 and is beneficial for signal synthesis.

[0088] like Figure 6 As shown, the first amplifying transistor 11 is arranged along the second direction on the side of the third pad away from the second chip, and multiple first amplifying transistors 11 form a first transistor arrangement area. In the second direction, the center line of the first transistor arrangement area coincides with the center line of the third pad.

[0089] And / or, a plurality of second amplifying transistors 12 are arranged along a second direction on the side of the fourth pad away from the second chip, and the plurality of second amplifying transistors 12 form a second transistor arrangement area, wherein the center line of the second transistor arrangement area coincides with the center line of the fourth pad in the second direction. That is, the first center line X1 of the first projection and the second center line X2 of the second projection coincide. And / or, the third center line X3 of the third projection and the fourth center line X4 of the fourth projection coincide.

[0090] In this embodiment, the extension directions of the first center line X1 and the second center line X2 are parallel to the first direction. The first center line X1 and the second center line X2 coincide, so that the multiple first amplifying transistors 11 are axially symmetrically distributed about the center line, which helps to reduce the path difference between each first amplifying transistor 11 and the corresponding pad.

[0091] Meanwhile, the extension directions of the third center line X3 and the fourth center line X4 are parallel to the first direction. The third center line X3 and the fourth center line X4 coincide, so that the multiple second amplifying transistors 12 are axially symmetrically distributed about the center line, which helps to reduce the path difference between each second amplifying transistor 12 and the corresponding pad.

[0092] In summary, by arranging the positional relationship between the third pad and the first amplifying transistor 11, the lead lengths of the leads connecting the third pad 401 and each of the first amplifying transistors 11 are relatively consistent, thus avoiding a large signal transmission time difference caused by the different lengths of the leads connecting the third pad 401 and each of the first amplifying transistors 11.

[0093] By arranging the positional relationship between the fourth pad and the second amplifying transistor, the lead lengths of the leads connecting the fourth pad 402 and each of the second amplifying transistors 12 are made relatively consistent, thus avoiding a large signal transmission time difference caused by the different lengths of the leads connecting the fourth pad 402 and each of the second amplifying transistors 12.

[0094] Please see Figure 7 In some embodiments, the first chip 30 is further provided with a third capacitor 211, a fourth capacitor 221, a fifth pad 303 and a sixth pad 304. The first end of the third capacitor 211 is connected to the output end of the first amplifying transistor 11, and the second end of the third capacitor 211 is connected to the fifth pad 303. The first end of the fourth capacitor 221 is connected to the output end of the second amplifying transistor 12, and the second end of the fourth capacitor 221 is connected to the sixth pad 304.

[0095] Optionally, the capacitance value of the third capacitor 211 is less than the capacitance value of the first capacitor network 171; and / or, the capacitance value of the fourth capacitor 221 is less than the capacitance value of the second capacitor network 172.

[0096] This application places a capacitor network with a large capacitance value, such as a capacitor network with a capacitance value greater than or equal to 3pF, in the second chip, which can reduce the impact of the parasitic capacitance generated between the capacitor network and the metal layer 503 of the substrate 50 on the amplifying transistor 10.

[0097] It can be understood that the capacitance value of the first capacitor network 171 refers to the total capacitance value of the capacitor network 17, and the capacitance value of the third capacitor 211 is less than the capacitance value of the first capacitor network 171. That is, the capacitance value of the third capacitor 211 is less than the total capacitance value of the first capacitor network 171. The first capacitor network 171 includes at least one capacitor. When the first capacitor network 171 includes at least two capacitors, the at least two capacitors can be connected in series or in parallel, which is not limited here.

[0098] likeFigure 7 As shown, in some embodiments, the first surface 501 is further provided with a first grounding pad 504 and a second grounding pad 505, and the connector 80 further includes a fifth connector 85 and a sixth connector 86; the first end of the fifth connector 85 is connected to the fifth pad 303, and the second end of the fifth connector 85 is connected to the first grounding pad 504; the first end of the sixth connector 86 is connected to the sixth pad 304, and the second end of the sixth connector 86 is connected to the second grounding pad 505.

[0099] Optionally, the fifth connector 85 includes at least a fifth lead, and the parasitic inductance Lx5 of the fifth lead forms a fifth inductor; the sixth connector 86 includes at least a sixth lead, and the parasitic inductance Lx6 of the sixth lead forms a sixth inductor; wherein the fifth inductor and the third capacitor 211 form a first LC resonant circuit 21, and the sixth inductor and the fourth capacitor 221 form a second LC resonant circuit 22.

[0100] In this embodiment, a first LC resonant circuit 21 is formed by a fifth inductor and a third capacitor 211, and a second LC resonant circuit 22 is formed by a sixth inductor and a fourth capacitor 221. The first LC resonant circuit 21 achieves second-order impedance matching for the first amplification branch, thereby effectively suppressing harmonics generated in the first amplification branch. Similarly, the second LC resonant circuit 22 achieves second-order impedance matching for the second amplification branch, thereby effectively suppressing harmonics generated in the second amplification branch.

[0101] like Figure 7 As shown, in some embodiments, the RF front-end module 100 further includes a balun 18, which is disposed on the second chip 40. The first end of the first capacitor network 171 is connected to the first pad 401, and the second end of the first capacitor network 171 is connected to the first input terminal of the balun 18. The first end of the second capacitor network 172 is connected to the second pad 402, and the second end of the second capacitor network 172 is connected to the second input terminal of the balun 18.

[0102] In some embodiments, the balun 18 includes a first primary coil 181 and a second primary coil 182, and a first primary coil 183 coupled to the first primary coil 181 and the second primary coil 182. The second end of the first capacitor network 171 is connected to the first end of the first primary coil 181, the second end of the second capacitor network 172 is connected to the second end of the second primary coil 182, the second end of the first primary coil 181 is connected to the first end of the second primary coil 182, and the first end of the second primary coil 182 is grounded; or, the second end of the first capacitor network 171 is connected to the first end of the first primary coil 181, the second end of the second capacitor network 172 is connected to the second end of the second primary coil 182, and both the second end of the first primary coil 181 and the first end of the second primary coil 182 are grounded.

[0103] Wherein, the second end of the first primary coil 181 and the first end of the second primary coil 182 are both used for grounding, which can be understood as follows: Figure 4 and Figure 7 As shown, the second end of the first primary coil 181 and the first end of the second primary coil 182 can be connected to a common ground, and the second end of the first primary coil 181 and the first end of the second primary coil 182 can also be grounded separately. Of course, in some embodiments, the second end of the first primary coil 181 and the first end of the second primary coil 182 can also be directly connected in series, and this application does not make specific limitations.

[0104] In some embodiments, the amplifying transistor 10 includes a first amplifying transistor 11 and a second amplifying transistor 12. The capacitor network 17 is disposed in the second chip 40 and can be connected between the second end of the first primary coil 181 and the first end of the second primary coil 182 (not shown in the figure). This application does not make specific limitations.

[0105] In this embodiment, by placing the capacitor network connected to the output terminal of the amplifying transistor and the balun in a second chip different from the first chip, not only can the impact of the parasitic capacitance generated between the capacitor network and the back gold of the substrate on the operating efficiency of the amplifying transistor be reduced, but the capacitor network, in conjunction with the balun, can also achieve better impedance matching.

[0106] like Figure 7 As shown, in some embodiments, the RF front-end module 100 further includes a matching circuit 23, with the first end of the primary coil 183 coupled / connected to the matching circuit 23 and the second end of the primary coil 183 grounded.

[0107] Optionally, the matching circuit 23 includes a fifth capacitor 231, a seventh inductor, and a sixth capacitor 233. The fifth capacitor 231 is disposed on the second chip 40, and the second chip 40 is also provided with a third grounding pad. The first end of the fifth capacitor 231 is connected to the output end of the first primary coil 183, and the second end of the fifth capacitor 231 is connected to the third grounding pad.

[0108] In this embodiment, by setting a matching circuit, better impedance matching can be achieved at the output of the amplifying transistor by combining the matching circuit with capacitor networks, baluns, etc. The RF front-end module 100 also includes a third chip 90, a sixth capacitor 233 is disposed on the third chip 90, and the third chip 90 is also provided with a fourth ground pad. The second end of the sixth capacitor 233 is connected to the fourth ground pad. Optionally, the third chip 90 can be a pHEMT chip, that is, a chip manufactured using pHEMT technology.

[0109] The connector 80 also includes a seventh connector 87, the first end of which is connected to the first end of the fifth capacitor 231, the second end of which is connected to the first end of the sixth capacitor 233, and the parasitic inductance Lx7 of the seventh connector 87 forms the seventh inductor.

[0110] In this embodiment, by placing one capacitor of the matching circuit on the second chip and the other on the third chip and connecting them with a connector, the parasitic inductance of the connector is used to form an inductor, thus making the circuit layout simpler and enabling the miniaturization of the RF front-end module.

[0111] Please see Figure 8 The communication device 200 achieves wireless communication with external communication devices through a built-in antenna device. The antenna device, through its internal modules, transmits and receives radio frequency signals in relevant frequency bands. Of course, the communication device 100 includes not only the antenna device but also other modules, such as signal processing devices, processors, user interfaces, and memory. Communication devices include, but are not limited to, personal digital assistants (PDAs), mobile phones, card slots in laptops, and wireless tablet computers.

[0112] like Figure 8 As shown, the antenna device in this example includes a radio frequency (RF) front-end module 100 and an antenna module 101. The RF front-end module 100 can operate in either a transmit or receive mode. The operating mode of the RF front-end module 100 can be switched via a transmit / receive switch. When the RF front-end module 100 operates in transmit mode, it transmits the received RF analog signal to the antenna module 101 for signal transmission. When the RF front-end module 100 operates in receive mode, it receives the RF analog signal received by the antenna module 101 and performs amplification, filtering, and other processing on the RF analog signal.

[0113] It should be noted that the circuit structure, components or circuit parameters and related beneficial effects that are the same as those in the first and second embodiments are not repeated here. For detailed descriptions, please refer to the foregoing implementation methods.

[0114] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A radio frequency front-end module, characterized in that, include: Substrate, first chip, second chip, and connectors; The substrate includes a first side and a second side facing away from each other, the first chip and the second chip are disposed on the first side, and the second side is provided with a metal layer; The first chip integrates an amplifying transistor, and the second chip integrates a capacitor network. The output terminal of the amplifying transistor is connected to the capacitor network through the connector.

2. The radio frequency front-end module according to claim 1, characterized in that, The thickness of the first chip is less than the thickness of the second chip.

3. The radio frequency front-end module according to claim 2, characterized in that, The second chip is an IPD chip, and / or the thickness of the second chip is 60um-120um.

4. The radio frequency front-end module according to claim 1, characterized in that, The amplifying transistor includes a first amplifying transistor and a second amplifying transistor, the capacitor network includes a first capacitor network and a second capacitor network, and the connector includes a first connector and a second connector. The first chip has a third pad and a fourth pad, the second chip has a first pad and a second pad, the output terminal of the first amplifying transistor is connected to the third pad, the output terminal of the second amplifying transistor is connected to the fourth pad, the first capacitor network is connected to the first pad, the second capacitor network is connected to the second pad, the first connector is connected to the third pad and the first pad, and the second connector is connected to the fourth pad and the second pad.

5. The radio frequency front-end module according to claim 4, characterized in that, The first chip and the second chip are disposed at a distance from each other on the substrate along a first direction; The first pad and the second pad are arranged in a row along the second direction on the side of the second chip close to the first chip; The third pad and the fourth pad are arranged in a row along the second direction on the side of the first chip near the second chip, and the second direction and the first direction are perpendicular to each other.

6. The radio frequency front-end module according to claim 5, characterized in that, A plurality of first amplifying transistors are arranged along the second direction on the side of the third pad away from the second chip, and the plurality of first amplifying transistors form a first transistor arrangement area; and the third pad has a first projection in the first direction, the first transistor arrangement area has a second projection in the first direction, the first projection and the second projection at least partially overlap, and the extension length of the overlapping portion of the first projection and the second projection in the second direction is 30% to 100% of the extension length of the second projection in the second direction; And / or, a plurality of second amplifying transistors are disposed along the second direction on the side of the fourth pad away from the second chip, and the plurality of second amplifying transistors form a second transistor arrangement area; and, the fourth pad has a third projection in the first direction, the second transistor arrangement area has a fourth projection in the first direction, the third projection and the fourth projection at least partially overlap, and the extension length of the overlapping portion of the third projection and the fourth projection in the second direction is 30% to 100% of the extension length of the fourth projection in the second direction.

7. The radio frequency front-end module according to claim 5, characterized in that, A plurality of first amplifying transistors are arranged along the second direction on the side of the third pad away from the second chip, and the plurality of first amplifying transistors form a first transistor arrangement area. In the second direction, the center line of the first transistor arrangement area coincides with the center line of the third pad. And / or, a plurality of second amplifying transistors are arranged along the second direction on the side of the fourth pad away from the second chip, and the plurality of second amplifying transistors form a second transistor arrangement area, wherein the center line of the second transistor arrangement area coincides with the center line of the fourth pad in the second direction.

8. The radio frequency front-end module according to claim 4, characterized in that, The first connector includes at least a first lead, and the parasitic inductance of the first lead forms a first inductance; And / or, the second connector includes at least a second lead, the parasitic inductance of which forms a second inductance.

9. The radio frequency front-end module according to claim 4, characterized in that, The first side is also provided with a first power port and a second power port. The connector further includes a third connector and a fourth connector. The first power port is connected to the first pad through the third connector, and the second power port is connected to the second pad through the fourth connector.

10. The radio frequency front-end module according to claim 9, characterized in that, The third connector includes at least a third lead, and the parasitic inductance of the third lead forms a third inductance; And / or, the fourth connector includes at least a fourth lead, the parasitic inductance of which forms a fourth inductance.

11. The radio frequency front-end module according to claim 9, characterized in that, The first chip is disposed adjacent to the first side of the second chip, and the first power port and the second power port are disposed on the second side and the third side of the second chip respectively, wherein the first side is adjacent to the second side and the third side respectively.

12. The radio frequency front-end module according to claim 4, characterized in that, The first chip is further provided with a third capacitor, a fourth capacitor, a fifth pad, and a sixth pad. The first end of the third capacitor is connected to the output terminal of the first amplifying transistor, the second end of the third capacitor is connected to the fifth pad, the first end of the fourth capacitor is connected to the output terminal of the second amplifying transistor, and the second end of the fourth capacitor is connected to the sixth pad.

13. The radio frequency front-end module according to claim 12, characterized in that, The capacitance value of the third capacitor is less than the capacitance value of the first capacitor network; and / or, the capacitance value of the fourth capacitor is less than the capacitance value of the second capacitor network.

14. The radio frequency front-end module according to claim 12, characterized in that, The first surface is also provided with a first grounding pad and a second grounding pad, and the connector further includes a fifth connector and a sixth connector; The first end of the fifth connector is connected to the fifth pad, and the second end of the fifth connector is connected to the first ground pad; the first end of the sixth connector is connected to the sixth pad, and the second end of the sixth connector is connected to the second ground pad.

15. The radio frequency front-end module according to claim 14, characterized in that, The fifth connector includes at least a fifth lead, the parasitic inductance of which forms a fifth inductance; the sixth connector includes at least a sixth lead, the parasitic inductance of which forms a sixth inductance. The fifth inductor and the third capacitor form a first LC resonant circuit, and the sixth inductor and the fourth capacitor form a second LC resonant circuit.

16. The radio frequency front-end module according to claim 4, characterized in that, The RF front-end module also includes a balun, which is disposed on the second chip. The first end of the first capacitor network is connected to the first pad, and the second end of the first capacitor network is connected to the first input terminal of the balun. The first end of the second capacitor network is connected to the second pad, and the second end of the second capacitor network is connected to the second input terminal of the balun.

17. The radio frequency front-end module according to claim 16, characterized in that, The balun includes a first primary coil and a second primary coil, and a first secondary coil coupled to the first primary coil and the second primary coil; Wherein, the second end of the first capacitor network is connected to the first end of the first primary coil, the second end of the second capacitor network is connected to the second end of the second primary coil, the second end of the first primary coil is connected to the first end of the second primary coil, and the first end of the second primary coil is grounded; or, the second end of the first capacitor network is connected to the first end of the first primary coil, the second end of the second capacitor network is connected to the second end of the second primary coil, and both the second end of the first primary coil and the first end of the second primary coil are grounded.

18. The radio frequency front-end module according to claim 17, characterized in that, The radio frequency front-end module also includes a matching circuit, wherein the first end of the primary coil is coupled to or connected to the matching circuit, and the second end of the primary coil is grounded.

19. The radio frequency front-end module according to claim 18, characterized in that, The matching circuit includes a fifth capacitor, a seventh inductor, and a sixth capacitor; The fifth capacitor is disposed on the second chip, and the second chip is also provided with a third grounding pad. The first end of the fifth capacitor is connected to the output end of the first primary coil, and the second end of the fifth capacitor is connected to the third grounding pad. The radio frequency front-end module also includes a third chip, the sixth capacitor is disposed on the third chip, and the third chip is also provided with a fourth ground pad, the second end of the sixth capacitor is connected to the fourth ground pad; The connector further includes a seventh connector, the first end of which is connected to the first end of the fifth capacitor, the second end of which is connected to the first end of the sixth capacitor, and the parasitic inductance of the seventh connector forms the seventh inductance.

20. The radio frequency front-end module according to claim 4, characterized in that, The capacitance value of the first capacitor network ranges from [3pF to 20pF]; and / or, the capacitance value of the second capacitor network ranges from [3pF to 20pF].

21. The radio frequency front-end module according to any one of claims 1-20, characterized in that, The operating frequency band of the radio frequency front-end module is 5.1 GHz. Z Up to 5.9GH Z .

22. A communication device, characterized in that, The communication device includes at least the radio frequency front-end module as described in any one of claims 1-21.

Images